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hw/arm/virt-acpi-build: Generate MCFG table
Generate MCFG table for PCIe controller. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-14-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -39,6 +39,7 @@
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#include "hw/loader.h"
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#include "hw/hw.h"
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#include "hw/acpi/aml-build.h"
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#include "hw/pci/pcie_host.h"
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#define ARM_SPI_BASE 32
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@ -180,6 +181,25 @@ build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
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return rsdp_table;
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}
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static void
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build_mcfg(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
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{
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AcpiTableMcfg *mcfg;
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const MemMapEntry *memmap = guest_info->memmap;
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int len = sizeof(*mcfg) + sizeof(mcfg->allocation[0]);
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mcfg = acpi_data_push(table_data, len);
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mcfg->allocation[0].address = cpu_to_le64(memmap[VIRT_PCIE_ECAM].base);
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/* Only a single allocation so no need to play with segments */
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mcfg->allocation[0].pci_segment = cpu_to_le16(0);
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mcfg->allocation[0].start_bus_number = 0;
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mcfg->allocation[0].end_bus_number = (memmap[VIRT_PCIE_ECAM].size
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/ PCIE_MMCFG_SIZE_MIN) - 1;
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build_header(linker, table_data, (void *)mcfg, "MCFG", len, 5);
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}
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/* GTDT */
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static void
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build_gtdt(GArray *table_data, GArray *linker)
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@ -350,6 +370,9 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
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acpi_add_table(table_offsets, tables_blob);
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build_gtdt(tables_blob, tables->linker);
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acpi_add_table(table_offsets, tables_blob);
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build_mcfg(tables_blob, tables->linker, guest_info);
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/* RSDT is pointed to by RSDP */
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rsdt = tables_blob->len;
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build_rsdt(tables_blob, tables->linker, table_offsets);
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