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target/xtensa updates:
- make mini-bootloader independent of the initial CPU state; - add noMMU XTFPGA variants; - add two noMMU cores: de212 and sample_controller; - fix issues reported by coverity against xtensa translator and disassembler. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJaZkLBAAoJEFH5zJH4P6BE6mIQAJT1hjEhfgm3xiGfVJZYGo34 Eo/KeyKC7QOUbr0R+E+J3h2yxSXWYbweoAZvFXkH5V4w/fhdvrCXZPVvDW0QjYY/ wG0h+YfV/8cgVxq8AiaPHie//bLhKvJKpqH4A0HnCE4pBcslKwjOtFcG20RfOgk8 PeQSa15QsyhOtTgdlg8rdRDECL6Lm8mXTWtOdxx8HQsl73REmNgkOZzQDSK6D5gM EcAJQTCcPNoDKblJKae/msSG/Vbv3PxECGaj6B72pKDSUW5Z/OqzxXDnwWXQyOgu q1WoPwL5U0u7uH5JE5wdD0EqwypQAbMAuzFTsove5pQlaCWdxDJzK+74NFOh6BcL JmLZbA4UIlA19KXiZdNKRbeH5O1U1E9xBe0wxLsqVagrwkBfpRAhI3MG1qZE1Id3 3O6qsk26ATBGmJgTb80Wk1lPKZgKzdgcCJpzj+nz7slXp4uIQ6R3rU+6huONsGNJ bvz+25RAMzbFLd1l0sDsEegxmQ2BqC2Y8JqO5EKgKtT72Aooax3X6pWc8GCPuwxd 1MCoi/ZfDcYQXNS++A3hpiKI6+qrn2t51TuyB2aUnHXtFrhlBDN1W+d+tcxl23gr pHIaOKbZ0nL1TmUOklAZicFMoxbDz1uebqetNS3OIYkpmuf7hMrAnKkbXUeqq9qo gy8+yJrXbEWPHeWZ4MtX =qf0K -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/xtensa/tags/20180122-xtensa' into staging target/xtensa updates: - make mini-bootloader independent of the initial CPU state; - add noMMU XTFPGA variants; - add two noMMU cores: de212 and sample_controller; - fix issues reported by coverity against xtensa translator and disassembler. # gpg: Signature made Mon 22 Jan 2018 20:00:01 GMT # gpg: using RSA key 0x51F9CC91F83FA044 # gpg: Good signature from "Max Filippov <filippov@cadence.com>" # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20180122-xtensa: target/xtensa: disas/xtensa: fix coverity warnings target/xtensa: add sample_controller core target/xtensa: allow different default CPU for MMU/noMMU target/xtensa: add de212 core hw/xtensa/xtfpga: support noMMU cores hw/xtensa/xtfpga: extract flash configuration hw/xtensa: extract xtensa_create_memory_regions target/xtensa: fix default sysrom/sysram addresses hw/xtensa/xtfpga: clean up function/structure names hw/xtensa/xtfpga: rewrite mini bootloader Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
82de978a8b
@ -37,7 +37,7 @@ int print_insn_xtensa(bfd_vma memaddr, struct disassemble_info *info)
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bfd_byte *buffer = g_malloc(1);
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int status = info->read_memory_func(memaddr, buffer, 1, info);
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xtensa_format fmt;
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unsigned slot, slots;
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int slot, slots;
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unsigned len;
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if (status) {
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@ -79,7 +79,7 @@ int print_insn_xtensa(bfd_vma memaddr, struct disassemble_info *info)
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for (slot = 0; slot < slots; ++slot) {
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xtensa_opcode opc;
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unsigned opnd, vopnd, opnds;
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int opnd, vopnd, opnds;
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if (slot) {
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info->fprintf_func(info->stream, "; ");
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@ -1,3 +1,4 @@
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obj-y += pic_cpu.o
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obj-y += sim.o
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obj-y += xtensa_memory.o
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obj-y += xtfpga.o
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@ -36,25 +36,7 @@
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#include "exec/memory.h"
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#include "exec/address-spaces.h"
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#include "qemu/error-report.h"
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static void xtensa_create_memory_regions(const XtensaMemory *memory,
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const char *name)
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{
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unsigned i;
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GString *num_name = g_string_new(NULL);
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for (i = 0; i < memory->num; ++i) {
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MemoryRegion *m;
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g_string_printf(num_name, "%s%u", name, i);
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m = g_new(MemoryRegion, 1);
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memory_region_init_ram(m, NULL, num_name->str,
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memory->location[i].size, &error_fatal);
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memory_region_add_subregion(get_system_memory(),
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memory->location[i].addr, m);
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}
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g_string_free(num_name, true);
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}
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#include "xtensa_memory.h"
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static uint64_t translate_phys_addr(void *opaque, uint64_t addr)
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{
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@ -94,12 +76,18 @@ static void xtensa_sim_init(MachineState *machine)
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XtensaMemory sysram = env->config->sysram;
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sysram.location[0].size = ram_size;
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xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom");
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xtensa_create_memory_regions(&env->config->instram, "xtensa.instram");
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xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom");
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xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram");
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xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom");
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xtensa_create_memory_regions(&sysram, "xtensa.sysram");
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xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom",
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get_system_memory());
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xtensa_create_memory_regions(&env->config->instram, "xtensa.instram",
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get_system_memory());
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xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom",
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get_system_memory());
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xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram",
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get_system_memory());
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xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom",
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get_system_memory());
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xtensa_create_memory_regions(&sysram, "xtensa.sysram",
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get_system_memory());
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}
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if (serial_hds[0]) {
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55
hw/xtensa/xtensa_memory.c
Normal file
55
hw/xtensa/xtensa_memory.c
Normal file
@ -0,0 +1,55 @@
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/*
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* Copyright (c) 2017, Max Filippov, Open Source and Linux Lab.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
|
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Open Source and Linux Lab nor the
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* names of its contributors may be used to endorse or promote products
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||||
* derived from this software without specific prior written permission.
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||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu-common.h"
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#include "cpu.h"
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#include "sysemu/sysemu.h"
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#include "hw/boards.h"
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#include "exec/memory.h"
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#include "qemu/error-report.h"
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#include "xtensa_memory.h"
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void xtensa_create_memory_regions(const XtensaMemory *memory,
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const char *name,
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MemoryRegion *super)
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{
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unsigned i;
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GString *num_name = g_string_new(NULL);
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for (i = 0; i < memory->num; ++i) {
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MemoryRegion *m;
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g_string_printf(num_name, "%s%u", name, i);
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m = g_new(MemoryRegion, 1);
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memory_region_init_ram(m, NULL, num_name->str,
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memory->location[i].size, &error_fatal);
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memory_region_add_subregion(super, memory->location[i].addr, m);
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}
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g_string_free(num_name, true);
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}
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40
hw/xtensa/xtensa_memory.h
Normal file
40
hw/xtensa/xtensa_memory.h
Normal file
@ -0,0 +1,40 @@
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/*
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* Copyright (c) 2017, Max Filippov, Open Source and Linux Lab.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
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||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of the Open Source and Linux Lab nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _XTENSA_MEMORY_H
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#define _XTENSA_MEMORY_H
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "cpu.h"
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#include "exec/memory.h"
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void xtensa_create_memory_regions(const XtensaMemory *memory,
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const char *name,
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MemoryRegion *super);
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#endif
|
@ -44,33 +44,39 @@
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#include "sysemu/device_tree.h"
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#include "qemu/error-report.h"
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#include "bootparam.h"
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#include "xtensa_memory.h"
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typedef struct LxBoardDesc {
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hwaddr flash_base;
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size_t flash_size;
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size_t flash_boot_base;
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size_t flash_sector_size;
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typedef struct XtfpgaFlashDesc {
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hwaddr base;
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size_t size;
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size_t boot_base;
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size_t sector_size;
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} XtfpgaFlashDesc;
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typedef struct XtfpgaBoardDesc {
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const XtfpgaFlashDesc *flash;
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size_t sram_size;
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} LxBoardDesc;
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const hwaddr *io;
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} XtfpgaBoardDesc;
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typedef struct Lx60FpgaState {
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typedef struct XtfpgaFpgaState {
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MemoryRegion iomem;
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uint32_t leds;
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uint32_t switches;
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} Lx60FpgaState;
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} XtfpgaFpgaState;
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static void lx60_fpga_reset(void *opaque)
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static void xtfpga_fpga_reset(void *opaque)
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{
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Lx60FpgaState *s = opaque;
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XtfpgaFpgaState *s = opaque;
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s->leds = 0;
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s->switches = 0;
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}
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static uint64_t lx60_fpga_read(void *opaque, hwaddr addr,
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static uint64_t xtfpga_fpga_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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Lx60FpgaState *s = opaque;
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XtfpgaFpgaState *s = opaque;
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switch (addr) {
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case 0x0: /*build date code*/
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@ -88,10 +94,10 @@ static uint64_t lx60_fpga_read(void *opaque, hwaddr addr,
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return 0;
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}
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static void lx60_fpga_write(void *opaque, hwaddr addr,
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static void xtfpga_fpga_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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Lx60FpgaState *s = opaque;
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XtfpgaFpgaState *s = opaque;
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switch (addr) {
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case 0x8: /*LEDs (off = 0, on = 1)*/
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@ -106,26 +112,26 @@ static void lx60_fpga_write(void *opaque, hwaddr addr,
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}
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}
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static const MemoryRegionOps lx60_fpga_ops = {
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.read = lx60_fpga_read,
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.write = lx60_fpga_write,
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static const MemoryRegionOps xtfpga_fpga_ops = {
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.read = xtfpga_fpga_read,
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.write = xtfpga_fpga_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static Lx60FpgaState *lx60_fpga_init(MemoryRegion *address_space,
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static XtfpgaFpgaState *xtfpga_fpga_init(MemoryRegion *address_space,
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hwaddr base)
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{
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Lx60FpgaState *s = g_malloc(sizeof(Lx60FpgaState));
|
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XtfpgaFpgaState *s = g_malloc(sizeof(XtfpgaFpgaState));
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memory_region_init_io(&s->iomem, NULL, &lx60_fpga_ops, s,
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"lx60.fpga", 0x10000);
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memory_region_init_io(&s->iomem, NULL, &xtfpga_fpga_ops, s,
|
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"xtfpga.fpga", 0x10000);
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memory_region_add_subregion(address_space, base, &s->iomem);
|
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lx60_fpga_reset(s);
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qemu_register_reset(lx60_fpga_reset, s);
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xtfpga_fpga_reset(s);
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||||
qemu_register_reset(xtfpga_fpga_reset, s);
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return s;
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}
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|
||||
static void lx60_net_init(MemoryRegion *address_space,
|
||||
static void xtfpga_net_init(MemoryRegion *address_space,
|
||||
hwaddr base,
|
||||
hwaddr descriptors,
|
||||
hwaddr buffers,
|
||||
@ -154,7 +160,7 @@ static void lx60_net_init(MemoryRegion *address_space,
|
||||
}
|
||||
|
||||
static pflash_t *xtfpga_flash_init(MemoryRegion *address_space,
|
||||
const LxBoardDesc *board,
|
||||
const XtfpgaBoardDesc *board,
|
||||
DriveInfo *dinfo, int be)
|
||||
{
|
||||
SysBusDevice *s;
|
||||
@ -163,14 +169,14 @@ static pflash_t *xtfpga_flash_init(MemoryRegion *address_space,
|
||||
qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
|
||||
&error_abort);
|
||||
qdev_prop_set_uint32(dev, "num-blocks",
|
||||
board->flash_size / board->flash_sector_size);
|
||||
qdev_prop_set_uint64(dev, "sector-length", board->flash_sector_size);
|
||||
board->flash->size / board->flash->sector_size);
|
||||
qdev_prop_set_uint64(dev, "sector-length", board->flash->sector_size);
|
||||
qdev_prop_set_uint8(dev, "width", 2);
|
||||
qdev_prop_set_bit(dev, "big-endian", be);
|
||||
qdev_prop_set_string(dev, "name", "lx60.io.flash");
|
||||
qdev_prop_set_string(dev, "name", "xtfpga.io.flash");
|
||||
qdev_init_nofail(dev);
|
||||
s = SYS_BUS_DEVICE(dev);
|
||||
memory_region_add_subregion(address_space, board->flash_base,
|
||||
memory_region_add_subregion(address_space, board->flash->base,
|
||||
sysbus_mmio_get_region(s, 0));
|
||||
return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01");
|
||||
}
|
||||
@ -182,31 +188,31 @@ static uint64_t translate_phys_addr(void *opaque, uint64_t addr)
|
||||
return cpu_get_phys_page_debug(CPU(cpu), addr);
|
||||
}
|
||||
|
||||
static void lx60_reset(void *opaque)
|
||||
static void xtfpga_reset(void *opaque)
|
||||
{
|
||||
XtensaCPU *cpu = opaque;
|
||||
|
||||
cpu_reset(CPU(cpu));
|
||||
}
|
||||
|
||||
static uint64_t lx60_io_read(void *opaque, hwaddr addr,
|
||||
static uint64_t xtfpga_io_read(void *opaque, hwaddr addr,
|
||||
unsigned size)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void lx60_io_write(void *opaque, hwaddr addr,
|
||||
static void xtfpga_io_write(void *opaque, hwaddr addr,
|
||||
uint64_t val, unsigned size)
|
||||
{
|
||||
}
|
||||
|
||||
static const MemoryRegionOps lx60_io_ops = {
|
||||
.read = lx60_io_read,
|
||||
.write = lx60_io_write,
|
||||
static const MemoryRegionOps xtfpga_io_ops = {
|
||||
.read = xtfpga_io_read,
|
||||
.write = xtfpga_io_write,
|
||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
||||
};
|
||||
|
||||
static void lx_init(const LxBoardDesc *board, MachineState *machine)
|
||||
static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine)
|
||||
{
|
||||
#ifdef TARGET_WORDS_BIGENDIAN
|
||||
int be = 1;
|
||||
@ -216,7 +222,7 @@ static void lx_init(const LxBoardDesc *board, MachineState *machine)
|
||||
MemoryRegion *system_memory = get_system_memory();
|
||||
XtensaCPU *cpu = NULL;
|
||||
CPUXtensaState *env = NULL;
|
||||
MemoryRegion *ram, *rom, *system_io;
|
||||
MemoryRegion *system_io;
|
||||
DriveInfo *dinfo;
|
||||
pflash_t *flash = NULL;
|
||||
QemuOpts *machine_opts = qemu_get_machine_opts();
|
||||
@ -224,6 +230,7 @@ static void lx_init(const LxBoardDesc *board, MachineState *machine)
|
||||
const char *kernel_cmdline = qemu_opt_get(machine_opts, "append");
|
||||
const char *dtb_filename = qemu_opt_get(machine_opts, "dtb");
|
||||
const char *initrd_filename = qemu_opt_get(machine_opts, "initrd");
|
||||
const unsigned system_io_size = 224 * 1024 * 1024;
|
||||
int n;
|
||||
|
||||
for (n = 0; n < smp_cpus; n++) {
|
||||
@ -231,25 +238,43 @@ static void lx_init(const LxBoardDesc *board, MachineState *machine)
|
||||
env = &cpu->env;
|
||||
|
||||
env->sregs[PRID] = n;
|
||||
qemu_register_reset(lx60_reset, cpu);
|
||||
qemu_register_reset(xtfpga_reset, cpu);
|
||||
/* Need MMU initialized prior to ELF loading,
|
||||
* so that ELF gets loaded into virtual addresses
|
||||
*/
|
||||
cpu_reset(CPU(cpu));
|
||||
}
|
||||
|
||||
ram = g_malloc(sizeof(*ram));
|
||||
memory_region_init_ram(ram, NULL, "lx60.dram", machine->ram_size,
|
||||
&error_fatal);
|
||||
memory_region_add_subregion(system_memory, 0, ram);
|
||||
if (env) {
|
||||
XtensaMemory sysram = env->config->sysram;
|
||||
|
||||
sysram.location[0].size = machine->ram_size;
|
||||
xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom",
|
||||
system_memory);
|
||||
xtensa_create_memory_regions(&env->config->instram, "xtensa.instram",
|
||||
system_memory);
|
||||
xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom",
|
||||
system_memory);
|
||||
xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram",
|
||||
system_memory);
|
||||
xtensa_create_memory_regions(&sysram, "xtensa.sysram",
|
||||
system_memory);
|
||||
}
|
||||
|
||||
system_io = g_malloc(sizeof(*system_io));
|
||||
memory_region_init_io(system_io, NULL, &lx60_io_ops, NULL, "lx60.io",
|
||||
224 * 1024 * 1024);
|
||||
memory_region_add_subregion(system_memory, 0xf0000000, system_io);
|
||||
lx60_fpga_init(system_io, 0x0d020000);
|
||||
memory_region_init_io(system_io, NULL, &xtfpga_io_ops, NULL, "xtfpga.io",
|
||||
system_io_size);
|
||||
memory_region_add_subregion(system_memory, board->io[0], system_io);
|
||||
if (board->io[1]) {
|
||||
MemoryRegion *io = g_malloc(sizeof(*io));
|
||||
|
||||
memory_region_init_alias(io, NULL, "xtfpga.io.cached",
|
||||
system_io, 0, system_io_size);
|
||||
memory_region_add_subregion(system_memory, board->io[1], io);
|
||||
}
|
||||
xtfpga_fpga_init(system_io, 0x0d020000);
|
||||
if (nd_table[0].used) {
|
||||
lx60_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000,
|
||||
xtfpga_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000,
|
||||
xtensa_get_extint(env, 1), nd_table);
|
||||
}
|
||||
|
||||
@ -269,21 +294,24 @@ static void lx_init(const LxBoardDesc *board, MachineState *machine)
|
||||
if (kernel_filename) {
|
||||
uint32_t entry_point = env->pc;
|
||||
size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */
|
||||
uint32_t tagptr = 0xfe000000 + board->sram_size;
|
||||
uint32_t tagptr = env->config->sysrom.location[0].addr +
|
||||
board->sram_size;
|
||||
uint32_t cur_tagptr;
|
||||
BpMemInfo memory_location = {
|
||||
.type = tswap32(MEMORY_TYPE_CONVENTIONAL),
|
||||
.start = tswap32(0),
|
||||
.end = tswap32(machine->ram_size),
|
||||
.start = tswap32(env->config->sysram.location[0].addr),
|
||||
.end = tswap32(env->config->sysram.location[0].addr +
|
||||
machine->ram_size),
|
||||
};
|
||||
uint32_t lowmem_end = machine->ram_size < 0x08000000 ?
|
||||
machine->ram_size : 0x08000000;
|
||||
uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096);
|
||||
|
||||
rom = g_malloc(sizeof(*rom));
|
||||
memory_region_init_ram(rom, NULL, "lx60.sram", board->sram_size,
|
||||
&error_fatal);
|
||||
memory_region_add_subregion(system_memory, 0xfe000000, rom);
|
||||
lowmem_end += env->config->sysram.location[0].addr;
|
||||
cur_lowmem += env->config->sysram.location[0].addr;
|
||||
|
||||
xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom",
|
||||
system_memory);
|
||||
|
||||
if (kernel_cmdline) {
|
||||
bp_size += get_tag_size(strlen(kernel_cmdline) + 1);
|
||||
@ -372,146 +400,308 @@ static void lx_init(const LxBoardDesc *board, MachineState *machine)
|
||||
}
|
||||
}
|
||||
if (entry_point != env->pc) {
|
||||
static const uint8_t jx_a0[] = {
|
||||
uint8_t boot[] = {
|
||||
#ifdef TARGET_WORDS_BIGENDIAN
|
||||
0x0a, 0, 0,
|
||||
0x60, 0x00, 0x08, /* j 1f */
|
||||
0x00, /* .literal_position */
|
||||
0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
|
||||
0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
|
||||
/* 1: */
|
||||
0x10, 0xff, 0xfe, /* l32r a0, entry_pc */
|
||||
0x12, 0xff, 0xfe, /* l32r a2, entry_a2 */
|
||||
0x0a, 0x00, 0x00, /* jx a0 */
|
||||
#else
|
||||
0xa0, 0, 0,
|
||||
0x06, 0x02, 0x00, /* j 1f */
|
||||
0x00, /* .literal_position */
|
||||
0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
|
||||
0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
|
||||
/* 1: */
|
||||
0x01, 0xfe, 0xff, /* l32r a0, entry_pc */
|
||||
0x21, 0xfe, 0xff, /* l32r a2, entry_a2 */
|
||||
0xa0, 0x00, 0x00, /* jx a0 */
|
||||
#endif
|
||||
};
|
||||
env->regs[0] = entry_point;
|
||||
cpu_physical_memory_write(env->pc, jx_a0, sizeof(jx_a0));
|
||||
uint32_t entry_pc = tswap32(entry_point);
|
||||
uint32_t entry_a2 = tswap32(tagptr);
|
||||
|
||||
memcpy(boot + 4, &entry_pc, sizeof(entry_pc));
|
||||
memcpy(boot + 8, &entry_a2, sizeof(entry_a2));
|
||||
cpu_physical_memory_write(env->pc, boot, sizeof(boot));
|
||||
}
|
||||
} else {
|
||||
if (flash) {
|
||||
MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash);
|
||||
MemoryRegion *flash_io = g_malloc(sizeof(*flash_io));
|
||||
uint32_t size = env->config->sysrom.location[0].size;
|
||||
|
||||
memory_region_init_alias(flash_io, NULL, "lx60.flash",
|
||||
flash_mr, board->flash_boot_base,
|
||||
board->flash_size - board->flash_boot_base < 0x02000000 ?
|
||||
board->flash_size - board->flash_boot_base : 0x02000000);
|
||||
memory_region_add_subregion(system_memory, 0xfe000000,
|
||||
flash_io);
|
||||
if (board->flash->size - board->flash->boot_base < size) {
|
||||
size = board->flash->size - board->flash->boot_base;
|
||||
}
|
||||
|
||||
memory_region_init_alias(flash_io, NULL, "xtfpga.flash",
|
||||
flash_mr, board->flash->boot_base, size);
|
||||
memory_region_add_subregion(system_memory,
|
||||
env->config->sysrom.location[0].addr,
|
||||
flash_io);
|
||||
} else {
|
||||
xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom",
|
||||
system_memory);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void xtensa_lx60_init(MachineState *machine)
|
||||
static const hwaddr xtfpga_mmu_io[2] = {
|
||||
0xf0000000,
|
||||
};
|
||||
|
||||
static const hwaddr xtfpga_nommu_io[2] = {
|
||||
0x90000000,
|
||||
0x70000000,
|
||||
};
|
||||
|
||||
static const XtfpgaFlashDesc lx60_flash = {
|
||||
.base = 0x08000000,
|
||||
.size = 0x00400000,
|
||||
.sector_size = 0x10000,
|
||||
};
|
||||
|
||||
static void xtfpga_lx60_init(MachineState *machine)
|
||||
{
|
||||
static const LxBoardDesc lx60_board = {
|
||||
.flash_base = 0x08000000,
|
||||
.flash_size = 0x00400000,
|
||||
.flash_sector_size = 0x10000,
|
||||
static const XtfpgaBoardDesc lx60_board = {
|
||||
.flash = &lx60_flash,
|
||||
.sram_size = 0x20000,
|
||||
.io = xtfpga_mmu_io,
|
||||
};
|
||||
lx_init(&lx60_board, machine);
|
||||
xtfpga_init(&lx60_board, machine);
|
||||
}
|
||||
|
||||
static void xtensa_lx200_init(MachineState *machine)
|
||||
static void xtfpga_lx60_nommu_init(MachineState *machine)
|
||||
{
|
||||
static const LxBoardDesc lx200_board = {
|
||||
.flash_base = 0x08000000,
|
||||
.flash_size = 0x01000000,
|
||||
.flash_sector_size = 0x20000,
|
||||
.sram_size = 0x2000000,
|
||||
static const XtfpgaBoardDesc lx60_board = {
|
||||
.flash = &lx60_flash,
|
||||
.sram_size = 0x20000,
|
||||
.io = xtfpga_nommu_io,
|
||||
};
|
||||
lx_init(&lx200_board, machine);
|
||||
xtfpga_init(&lx60_board, machine);
|
||||
}
|
||||
|
||||
static void xtensa_ml605_init(MachineState *machine)
|
||||
static const XtfpgaFlashDesc lx200_flash = {
|
||||
.base = 0x08000000,
|
||||
.size = 0x01000000,
|
||||
.sector_size = 0x20000,
|
||||
};
|
||||
|
||||
static void xtfpga_lx200_init(MachineState *machine)
|
||||
{
|
||||
static const LxBoardDesc ml605_board = {
|
||||
.flash_base = 0x08000000,
|
||||
.flash_size = 0x01000000,
|
||||
.flash_sector_size = 0x20000,
|
||||
static const XtfpgaBoardDesc lx200_board = {
|
||||
.flash = &lx200_flash,
|
||||
.sram_size = 0x2000000,
|
||||
.io = xtfpga_mmu_io,
|
||||
};
|
||||
lx_init(&ml605_board, machine);
|
||||
xtfpga_init(&lx200_board, machine);
|
||||
}
|
||||
|
||||
static void xtensa_kc705_init(MachineState *machine)
|
||||
static void xtfpga_lx200_nommu_init(MachineState *machine)
|
||||
{
|
||||
static const LxBoardDesc kc705_board = {
|
||||
.flash_base = 0x00000000,
|
||||
.flash_size = 0x08000000,
|
||||
.flash_boot_base = 0x06000000,
|
||||
.flash_sector_size = 0x20000,
|
||||
static const XtfpgaBoardDesc lx200_board = {
|
||||
.flash = &lx200_flash,
|
||||
.sram_size = 0x2000000,
|
||||
.io = xtfpga_nommu_io,
|
||||
};
|
||||
lx_init(&kc705_board, machine);
|
||||
xtfpga_init(&lx200_board, machine);
|
||||
}
|
||||
|
||||
static void xtensa_lx60_class_init(ObjectClass *oc, void *data)
|
||||
static const XtfpgaFlashDesc ml605_flash = {
|
||||
.base = 0x08000000,
|
||||
.size = 0x01000000,
|
||||
.sector_size = 0x20000,
|
||||
};
|
||||
|
||||
static void xtfpga_ml605_init(MachineState *machine)
|
||||
{
|
||||
static const XtfpgaBoardDesc ml605_board = {
|
||||
.flash = &ml605_flash,
|
||||
.sram_size = 0x2000000,
|
||||
.io = xtfpga_mmu_io,
|
||||
};
|
||||
xtfpga_init(&ml605_board, machine);
|
||||
}
|
||||
|
||||
static void xtfpga_ml605_nommu_init(MachineState *machine)
|
||||
{
|
||||
static const XtfpgaBoardDesc ml605_board = {
|
||||
.flash = &ml605_flash,
|
||||
.sram_size = 0x2000000,
|
||||
.io = xtfpga_nommu_io,
|
||||
};
|
||||
xtfpga_init(&ml605_board, machine);
|
||||
}
|
||||
|
||||
static const XtfpgaFlashDesc kc705_flash = {
|
||||
.base = 0x00000000,
|
||||
.size = 0x08000000,
|
||||
.boot_base = 0x06000000,
|
||||
.sector_size = 0x20000,
|
||||
};
|
||||
|
||||
static void xtfpga_kc705_init(MachineState *machine)
|
||||
{
|
||||
static const XtfpgaBoardDesc kc705_board = {
|
||||
.flash = &kc705_flash,
|
||||
.sram_size = 0x2000000,
|
||||
.io = xtfpga_mmu_io,
|
||||
};
|
||||
xtfpga_init(&kc705_board, machine);
|
||||
}
|
||||
|
||||
static void xtfpga_kc705_nommu_init(MachineState *machine)
|
||||
{
|
||||
static const XtfpgaBoardDesc kc705_board = {
|
||||
.flash = &kc705_flash,
|
||||
.sram_size = 0x2000000,
|
||||
.io = xtfpga_nommu_io,
|
||||
};
|
||||
xtfpga_init(&kc705_board, machine);
|
||||
}
|
||||
|
||||
static void xtfpga_lx60_class_init(ObjectClass *oc, void *data)
|
||||
{
|
||||
MachineClass *mc = MACHINE_CLASS(oc);
|
||||
|
||||
mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
|
||||
mc->init = xtensa_lx60_init;
|
||||
mc->init = xtfpga_lx60_init;
|
||||
mc->max_cpus = 4;
|
||||
mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
|
||||
}
|
||||
|
||||
static const TypeInfo xtensa_lx60_type = {
|
||||
static const TypeInfo xtfpga_lx60_type = {
|
||||
.name = MACHINE_TYPE_NAME("lx60"),
|
||||
.parent = TYPE_MACHINE,
|
||||
.class_init = xtensa_lx60_class_init,
|
||||
.class_init = xtfpga_lx60_class_init,
|
||||
};
|
||||
|
||||
static void xtensa_lx200_class_init(ObjectClass *oc, void *data)
|
||||
static void xtfpga_lx60_nommu_class_init(ObjectClass *oc, void *data)
|
||||
{
|
||||
MachineClass *mc = MACHINE_CLASS(oc);
|
||||
|
||||
mc->desc = "lx60 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
|
||||
mc->init = xtfpga_lx60_nommu_init;
|
||||
mc->max_cpus = 4;
|
||||
mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
|
||||
}
|
||||
|
||||
static const TypeInfo xtfpga_lx60_nommu_type = {
|
||||
.name = MACHINE_TYPE_NAME("lx60-nommu"),
|
||||
.parent = TYPE_MACHINE,
|
||||
.class_init = xtfpga_lx60_nommu_class_init,
|
||||
};
|
||||
|
||||
static void xtfpga_lx200_class_init(ObjectClass *oc, void *data)
|
||||
{
|
||||
MachineClass *mc = MACHINE_CLASS(oc);
|
||||
|
||||
mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
|
||||
mc->init = xtensa_lx200_init;
|
||||
mc->init = xtfpga_lx200_init;
|
||||
mc->max_cpus = 4;
|
||||
mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
|
||||
}
|
||||
|
||||
static const TypeInfo xtensa_lx200_type = {
|
||||
static const TypeInfo xtfpga_lx200_type = {
|
||||
.name = MACHINE_TYPE_NAME("lx200"),
|
||||
.parent = TYPE_MACHINE,
|
||||
.class_init = xtensa_lx200_class_init,
|
||||
.class_init = xtfpga_lx200_class_init,
|
||||
};
|
||||
|
||||
static void xtensa_ml605_class_init(ObjectClass *oc, void *data)
|
||||
static void xtfpga_lx200_nommu_class_init(ObjectClass *oc, void *data)
|
||||
{
|
||||
MachineClass *mc = MACHINE_CLASS(oc);
|
||||
|
||||
mc->desc = "lx200 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
|
||||
mc->init = xtfpga_lx200_nommu_init;
|
||||
mc->max_cpus = 4;
|
||||
mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
|
||||
}
|
||||
|
||||
static const TypeInfo xtfpga_lx200_nommu_type = {
|
||||
.name = MACHINE_TYPE_NAME("lx200-nommu"),
|
||||
.parent = TYPE_MACHINE,
|
||||
.class_init = xtfpga_lx200_nommu_class_init,
|
||||
};
|
||||
|
||||
static void xtfpga_ml605_class_init(ObjectClass *oc, void *data)
|
||||
{
|
||||
MachineClass *mc = MACHINE_CLASS(oc);
|
||||
|
||||
mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
|
||||
mc->init = xtensa_ml605_init;
|
||||
mc->init = xtfpga_ml605_init;
|
||||
mc->max_cpus = 4;
|
||||
mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
|
||||
}
|
||||
|
||||
static const TypeInfo xtensa_ml605_type = {
|
||||
static const TypeInfo xtfpga_ml605_type = {
|
||||
.name = MACHINE_TYPE_NAME("ml605"),
|
||||
.parent = TYPE_MACHINE,
|
||||
.class_init = xtensa_ml605_class_init,
|
||||
.class_init = xtfpga_ml605_class_init,
|
||||
};
|
||||
|
||||
static void xtensa_kc705_class_init(ObjectClass *oc, void *data)
|
||||
static void xtfpga_ml605_nommu_class_init(ObjectClass *oc, void *data)
|
||||
{
|
||||
MachineClass *mc = MACHINE_CLASS(oc);
|
||||
|
||||
mc->desc = "ml605 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
|
||||
mc->init = xtfpga_ml605_nommu_init;
|
||||
mc->max_cpus = 4;
|
||||
mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
|
||||
}
|
||||
|
||||
static const TypeInfo xtfpga_ml605_nommu_type = {
|
||||
.name = MACHINE_TYPE_NAME("ml605-nommu"),
|
||||
.parent = TYPE_MACHINE,
|
||||
.class_init = xtfpga_ml605_nommu_class_init,
|
||||
};
|
||||
|
||||
static void xtfpga_kc705_class_init(ObjectClass *oc, void *data)
|
||||
{
|
||||
MachineClass *mc = MACHINE_CLASS(oc);
|
||||
|
||||
mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
|
||||
mc->init = xtensa_kc705_init;
|
||||
mc->init = xtfpga_kc705_init;
|
||||
mc->max_cpus = 4;
|
||||
mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
|
||||
}
|
||||
|
||||
static const TypeInfo xtensa_kc705_type = {
|
||||
static const TypeInfo xtfpga_kc705_type = {
|
||||
.name = MACHINE_TYPE_NAME("kc705"),
|
||||
.parent = TYPE_MACHINE,
|
||||
.class_init = xtensa_kc705_class_init,
|
||||
.class_init = xtfpga_kc705_class_init,
|
||||
};
|
||||
|
||||
static void xtensa_lx_machines_init(void)
|
||||
static void xtfpga_kc705_nommu_class_init(ObjectClass *oc, void *data)
|
||||
{
|
||||
type_register_static(&xtensa_lx60_type);
|
||||
type_register_static(&xtensa_lx200_type);
|
||||
type_register_static(&xtensa_ml605_type);
|
||||
type_register_static(&xtensa_kc705_type);
|
||||
MachineClass *mc = MACHINE_CLASS(oc);
|
||||
|
||||
mc->desc = "kc705 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
|
||||
mc->init = xtfpga_kc705_nommu_init;
|
||||
mc->max_cpus = 4;
|
||||
mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
|
||||
}
|
||||
|
||||
type_init(xtensa_lx_machines_init)
|
||||
static const TypeInfo xtfpga_kc705_nommu_type = {
|
||||
.name = MACHINE_TYPE_NAME("kc705-nommu"),
|
||||
.parent = TYPE_MACHINE,
|
||||
.class_init = xtfpga_kc705_nommu_class_init,
|
||||
};
|
||||
|
||||
static void xtfpga_machines_init(void)
|
||||
{
|
||||
type_register_static(&xtfpga_lx60_type);
|
||||
type_register_static(&xtfpga_lx200_type);
|
||||
type_register_static(&xtfpga_ml605_type);
|
||||
type_register_static(&xtfpga_kc705_type);
|
||||
type_register_static(&xtfpga_lx60_nommu_type);
|
||||
type_register_static(&xtfpga_lx200_nommu_type);
|
||||
type_register_static(&xtfpga_ml605_nommu_type);
|
||||
type_register_static(&xtfpga_kc705_nommu_type);
|
||||
}
|
||||
|
||||
type_init(xtfpga_machines_init)
|
||||
|
@ -1,7 +1,9 @@
|
||||
obj-y += xtensa-semi.o
|
||||
obj-y += core-dc232b.o
|
||||
obj-y += core-dc233c.o
|
||||
obj-y += core-de212.o
|
||||
obj-y += core-fsf.o
|
||||
obj-y += core-sample_controller.o
|
||||
obj-$(CONFIG_SOFTMMU) += monitor.o
|
||||
obj-y += xtensa-isa.o
|
||||
obj-y += translate.o op_helper.o helper.o cpu.o
|
||||
|
53
target/xtensa/core-de212.c
Normal file
53
target/xtensa/core-de212.c
Normal file
@ -0,0 +1,53 @@
|
||||
/*
|
||||
* Copyright (c) 2018, Max Filippov, Open Source and Linux Lab.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of the Open Source and Linux Lab nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#include "cpu.h"
|
||||
#include "exec/exec-all.h"
|
||||
#include "exec/gdbstub.h"
|
||||
#include "qemu-common.h"
|
||||
#include "qemu/host-utils.h"
|
||||
|
||||
#include "core-de212/core-isa.h"
|
||||
#include "overlay_tool.h"
|
||||
|
||||
#define xtensa_modules xtensa_modules_de212
|
||||
#include "core-de212/xtensa-modules.c"
|
||||
|
||||
static XtensaConfig de212 __attribute__((unused)) = {
|
||||
.name = "de212",
|
||||
.gdb_regmap = {
|
||||
.reg = {
|
||||
#include "core-de212/gdb-config.c"
|
||||
}
|
||||
},
|
||||
.isa_internal = &xtensa_modules,
|
||||
.clock_freq_khz = 40000,
|
||||
DEFAULT_SECTIONS
|
||||
};
|
||||
|
||||
REGISTER_CORE(de212)
|
622
target/xtensa/core-de212/core-isa.h
Normal file
622
target/xtensa/core-de212/core-isa.h
Normal file
@ -0,0 +1,622 @@
|
||||
/*
|
||||
* xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
|
||||
* processor CORE configuration
|
||||
*
|
||||
* See <xtensa/config/core.h>, which includes this file, for more details.
|
||||
*/
|
||||
|
||||
/* Xtensa processor core configuration information.
|
||||
|
||||
Copyright (c) 1999-2015 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
#ifndef _XTENSA_CORE_CONFIGURATION_H
|
||||
#define _XTENSA_CORE_CONFIGURATION_H
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
Parameters Useful for Any Code, USER or PRIVILEGED
|
||||
****************************************************************************/
|
||||
|
||||
/*
|
||||
* Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
|
||||
* configured, and a value of 0 otherwise. These macros are always defined.
|
||||
*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
ISA
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
|
||||
#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
|
||||
#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */
|
||||
#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */
|
||||
#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */
|
||||
#define XCHAL_HAVE_DEBUG 1 /* debug option */
|
||||
#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
|
||||
#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
|
||||
#define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
|
||||
#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
|
||||
#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
|
||||
#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
|
||||
#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */
|
||||
#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
|
||||
#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
|
||||
#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
|
||||
#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */
|
||||
#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */
|
||||
#define XCHAL_HAVE_L32R 1 /* L32R instruction */
|
||||
#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
|
||||
#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
|
||||
#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
|
||||
#define XCHAL_HAVE_EXCLUSIVE 0 /* L32EX/S32EX instructions */
|
||||
#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
|
||||
#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
|
||||
#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
|
||||
#define XCHAL_HAVE_ABS 1 /* ABS instruction */
|
||||
/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
|
||||
/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
|
||||
#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
|
||||
#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
|
||||
#define XCHAL_HAVE_SPECULATION 0 /* speculation */
|
||||
#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
|
||||
#define XCHAL_NUM_CONTEXTS 1 /* */
|
||||
#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */
|
||||
#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
|
||||
#define XCHAL_HAVE_PRID 1 /* processor ID register */
|
||||
#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
|
||||
#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */
|
||||
#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
|
||||
#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
|
||||
#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
|
||||
#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */
|
||||
#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */
|
||||
#define XCHAL_HAVE_THREADPTR 0 /* THREADPTR register */
|
||||
#define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */
|
||||
#define XCHAL_HAVE_CP 0 /* CPENABLE reg (coprocessor) */
|
||||
#define XCHAL_CP_MAXCFG 0 /* max allowed cp id plus one */
|
||||
#define XCHAL_HAVE_MAC16 1 /* MAC16 package */
|
||||
|
||||
#define XCHAL_HAVE_FUSION 0 /* Fusion*/
|
||||
#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */
|
||||
#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */
|
||||
#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */
|
||||
#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */
|
||||
#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */
|
||||
#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */
|
||||
#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */
|
||||
#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */
|
||||
#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */
|
||||
#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */
|
||||
#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */
|
||||
#define XCHAL_HAVE_HIFI_MINI 0
|
||||
|
||||
|
||||
|
||||
#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
|
||||
#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */
|
||||
#define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */
|
||||
#define XCHAL_HAVE_FP 0 /* single prec floating point */
|
||||
#define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */
|
||||
#define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */
|
||||
#define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */
|
||||
#define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */
|
||||
#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
|
||||
#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */
|
||||
#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/
|
||||
#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */
|
||||
#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/
|
||||
#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */
|
||||
#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */
|
||||
|
||||
#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */
|
||||
#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */
|
||||
#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
|
||||
#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
|
||||
#define XCHAL_HAVE_PDX4 0 /* PDX4 */
|
||||
#define XCHAL_HAVE_PDX8 0 /* PDX8 */
|
||||
#define XCHAL_HAVE_PDX16 0 /* PDX16 */
|
||||
#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
|
||||
#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */
|
||||
#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
|
||||
#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */
|
||||
#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */
|
||||
#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */
|
||||
#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */
|
||||
#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
|
||||
#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */
|
||||
#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
|
||||
#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */
|
||||
#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
|
||||
#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
|
||||
#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
|
||||
#define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */
|
||||
#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
|
||||
|
||||
#define XCHAL_HAVE_VISION 0 /* Vision */
|
||||
#define XCHAL_VISION_TYPE 0 /* Vision P5 or P3 */
|
||||
#define XCHAL_VISION_SIMD16 0 /* Vision simd16 */
|
||||
#define XCHAL_HAVE_VISION_HISTOGRAM 0 /* histogram option on Vision */
|
||||
#define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MISC
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */
|
||||
#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */
|
||||
#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */
|
||||
#define XCHAL_DATA_WIDTH 4 /* data width in bytes */
|
||||
#define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay
|
||||
(1 = 5-stage, 2 = 7-stage) */
|
||||
#define XCHAL_CLOCK_GATING_GLOBAL 0 /* global clock gating */
|
||||
#define XCHAL_CLOCK_GATING_FUNCUNIT 0 /* funct. unit clock gating */
|
||||
/* In T1050, applies to selected core load and store instructions (see ISA): */
|
||||
#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
|
||||
#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
|
||||
#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */
|
||||
#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/
|
||||
|
||||
#define XCHAL_SW_VERSION 1200000 /* sw version of this header */
|
||||
|
||||
#define XCHAL_CORE_ID "de212_371077" /* alphanum core name
|
||||
(CoreID) set in the Xtensa
|
||||
Processor Generator */
|
||||
|
||||
#define XCHAL_BUILD_UNIQUE_ID 0x0005A9EB /* 22-bit sw build ID */
|
||||
|
||||
/*
|
||||
* These definitions describe the hardware targeted by this software.
|
||||
*/
|
||||
#define XCHAL_HW_CONFIGID0 0xC283DFFE /* ConfigID hi 32 bits*/
|
||||
#define XCHAL_HW_CONFIGID1 0x1C85A985 /* ConfigID lo 32 bits*/
|
||||
#define XCHAL_HW_VERSION_NAME "LX6.0.2" /* full version name */
|
||||
#define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */
|
||||
#define XCHAL_HW_VERSION_MINOR 2 /* minor ver# of targeted hw */
|
||||
#define XCHAL_HW_VERSION 260002 /* major*100+minor */
|
||||
#define XCHAL_HW_REL_LX6 1
|
||||
#define XCHAL_HW_REL_LX6_0 1
|
||||
#define XCHAL_HW_REL_LX6_0_2 1
|
||||
#define XCHAL_HW_CONFIGID_RELIABLE 1
|
||||
/* If software targets a *range* of hardware versions, these are the bounds: */
|
||||
#define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */
|
||||
#define XCHAL_HW_MIN_VERSION_MINOR 2 /* minor v of earliest tgt hw */
|
||||
#define XCHAL_HW_MIN_VERSION 260002 /* earliest targeted hw */
|
||||
#define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */
|
||||
#define XCHAL_HW_MAX_VERSION_MINOR 2 /* minor v of latest tgt hw */
|
||||
#define XCHAL_HW_MAX_VERSION 260002 /* latest targeted hw */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
CACHE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */
|
||||
#define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */
|
||||
#define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */
|
||||
#define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */
|
||||
|
||||
#define XCHAL_ICACHE_SIZE 8192 /* I-cache size in bytes or 0 */
|
||||
#define XCHAL_DCACHE_SIZE 8192 /* D-cache size in bytes or 0 */
|
||||
|
||||
#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
|
||||
#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
|
||||
|
||||
#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */
|
||||
#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */
|
||||
#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */
|
||||
#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */
|
||||
#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */
|
||||
#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */
|
||||
#define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */
|
||||
#define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */
|
||||
#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */
|
||||
#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */
|
||||
|
||||
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
|
||||
****************************************************************************/
|
||||
|
||||
|
||||
#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
CACHE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_PIF 1 /* any outbound bus present */
|
||||
#define XCHAL_HAVE_AXI 0 /* AXI bus */
|
||||
#define XCHAL_HAVE_AXI_ECC 0 /* ECC on AXI bus */
|
||||
#define XCHAL_HAVE_ACELITE 0 /* ACELite bus */
|
||||
|
||||
/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
|
||||
|
||||
/* Number of cache sets in log2(lines per way): */
|
||||
#define XCHAL_ICACHE_SETWIDTH 7
|
||||
#define XCHAL_DCACHE_SETWIDTH 7
|
||||
|
||||
/* Cache set associativity (number of ways): */
|
||||
#define XCHAL_ICACHE_WAYS 2
|
||||
#define XCHAL_DCACHE_WAYS 2
|
||||
|
||||
/* Cache features: */
|
||||
#define XCHAL_ICACHE_LINE_LOCKABLE 1
|
||||
#define XCHAL_DCACHE_LINE_LOCKABLE 1
|
||||
#define XCHAL_ICACHE_ECC_PARITY 0
|
||||
#define XCHAL_DCACHE_ECC_PARITY 0
|
||||
|
||||
/* Cache access size in bytes (affects operation of SICW instruction): */
|
||||
#define XCHAL_ICACHE_ACCESS_SIZE 4
|
||||
#define XCHAL_DCACHE_ACCESS_SIZE 4
|
||||
|
||||
#define XCHAL_DCACHE_BANKS 1 /* number of banks */
|
||||
|
||||
/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
|
||||
#define XCHAL_CA_BITS 4
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
INTERNAL I/D RAM/ROMs and XLMI
|
||||
----------------------------------------------------------------------*/
|
||||
#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
|
||||
#define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */
|
||||
#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
|
||||
#define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */
|
||||
#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
|
||||
#define XCHAL_NUM_XLMI 1 /* number of core XLMI ports */
|
||||
|
||||
/* Instruction RAM 0: */
|
||||
#define XCHAL_INSTRAM0_VADDR 0x40000000 /* virtual address */
|
||||
#define XCHAL_INSTRAM0_PADDR 0x40000000 /* physical address */
|
||||
#define XCHAL_INSTRAM0_SIZE 131072 /* size in bytes */
|
||||
#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
|
||||
#define XCHAL_HAVE_INSTRAM0
|
||||
#define XCHAL_INSTRAM0_HAVE_IDMA 0 /* idma supported by this local memory */
|
||||
|
||||
/* Data RAM 0: */
|
||||
#define XCHAL_DATARAM0_VADDR 0x3FFE0000 /* virtual address */
|
||||
#define XCHAL_DATARAM0_PADDR 0x3FFE0000 /* physical address */
|
||||
#define XCHAL_DATARAM0_SIZE 131072 /* size in bytes */
|
||||
#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
|
||||
#define XCHAL_DATARAM0_BANKS 1 /* number of banks */
|
||||
#define XCHAL_HAVE_DATARAM0
|
||||
#define XCHAL_DATARAM0_HAVE_IDMA 0 /* idma supported by this local memory */
|
||||
|
||||
/* XLMI Port 0: */
|
||||
#define XCHAL_XLMI0_VADDR 0x3FFC0000 /* virtual address */
|
||||
#define XCHAL_XLMI0_PADDR 0x3FFC0000 /* physical address */
|
||||
#define XCHAL_XLMI0_SIZE 131072 /* size in bytes */
|
||||
#define XCHAL_XLMI0_ECC_PARITY 0 /* ECC/parity type, 0=none */
|
||||
|
||||
#define XCHAL_HAVE_IDMA 0
|
||||
#define XCHAL_HAVE_IDMA_TRANSPOSE 0
|
||||
|
||||
#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
INTERRUPTS and TIMERS
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
|
||||
#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
|
||||
#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
|
||||
#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
|
||||
#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
|
||||
#define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */
|
||||
#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
|
||||
#define XCHAL_NUM_EXTINTERRUPTS 17 /* num of external interrupts */
|
||||
#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
|
||||
(not including level zero) */
|
||||
#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */
|
||||
/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
|
||||
|
||||
/* Masks of interrupts at each interrupt level: */
|
||||
#define XCHAL_INTLEVEL1_MASK 0x001F80FF
|
||||
#define XCHAL_INTLEVEL2_MASK 0x00000100
|
||||
#define XCHAL_INTLEVEL3_MASK 0x00200E00
|
||||
#define XCHAL_INTLEVEL4_MASK 0x00001000
|
||||
#define XCHAL_INTLEVEL5_MASK 0x00002000
|
||||
#define XCHAL_INTLEVEL6_MASK 0x00000000
|
||||
#define XCHAL_INTLEVEL7_MASK 0x00004000
|
||||
|
||||
/* Masks of interrupts at each range 1..n of interrupt levels: */
|
||||
#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x001F80FF
|
||||
#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x001F81FF
|
||||
#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x003F8FFF
|
||||
#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x003F9FFF
|
||||
#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x003FBFFF
|
||||
#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x003FBFFF
|
||||
#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF
|
||||
|
||||
/* Level of each interrupt: */
|
||||
#define XCHAL_INT0_LEVEL 1
|
||||
#define XCHAL_INT1_LEVEL 1
|
||||
#define XCHAL_INT2_LEVEL 1
|
||||
#define XCHAL_INT3_LEVEL 1
|
||||
#define XCHAL_INT4_LEVEL 1
|
||||
#define XCHAL_INT5_LEVEL 1
|
||||
#define XCHAL_INT6_LEVEL 1
|
||||
#define XCHAL_INT7_LEVEL 1
|
||||
#define XCHAL_INT8_LEVEL 2
|
||||
#define XCHAL_INT9_LEVEL 3
|
||||
#define XCHAL_INT10_LEVEL 3
|
||||
#define XCHAL_INT11_LEVEL 3
|
||||
#define XCHAL_INT12_LEVEL 4
|
||||
#define XCHAL_INT13_LEVEL 5
|
||||
#define XCHAL_INT14_LEVEL 7
|
||||
#define XCHAL_INT15_LEVEL 1
|
||||
#define XCHAL_INT16_LEVEL 1
|
||||
#define XCHAL_INT17_LEVEL 1
|
||||
#define XCHAL_INT18_LEVEL 1
|
||||
#define XCHAL_INT19_LEVEL 1
|
||||
#define XCHAL_INT20_LEVEL 1
|
||||
#define XCHAL_INT21_LEVEL 3
|
||||
#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
|
||||
#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
|
||||
#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
|
||||
EXCSAVE/EPS/EPC_n, RFI n) */
|
||||
|
||||
/* Type of each interrupt: */
|
||||
#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
|
||||
#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE
|
||||
#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
|
||||
#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
|
||||
/* Masks of interrupts for each type of interrupt: */
|
||||
#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000
|
||||
#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880
|
||||
#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F8000
|
||||
#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F
|
||||
#define XCHAL_INTTYPE_MASK_TIMER 0x00002440
|
||||
#define XCHAL_INTTYPE_MASK_NMI 0x00004000
|
||||
#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_PROFILING 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_SG_ERR 0x00000000
|
||||
|
||||
/* Interrupt numbers assigned to specific interrupt sources: */
|
||||
#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
|
||||
#define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */
|
||||
#define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */
|
||||
#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
|
||||
#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */
|
||||
|
||||
/* Interrupt numbers for levels at which only one interrupt is configured: */
|
||||
#define XCHAL_INTLEVEL2_NUM 8
|
||||
#define XCHAL_INTLEVEL4_NUM 12
|
||||
#define XCHAL_INTLEVEL5_NUM 13
|
||||
#define XCHAL_INTLEVEL7_NUM 14
|
||||
/* (There are many interrupts each at level(s) 1, 3.) */
|
||||
|
||||
|
||||
/*
|
||||
* External interrupt mapping.
|
||||
* These macros describe how Xtensa processor interrupt numbers
|
||||
* (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
|
||||
* map to external BInterrupt<n> pins, for those interrupts
|
||||
* configured as external (level-triggered, edge-triggered, or NMI).
|
||||
* See the Xtensa processor databook for more details.
|
||||
*/
|
||||
|
||||
/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */
|
||||
#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */
|
||||
#define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */
|
||||
#define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */
|
||||
#define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */
|
||||
#define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */
|
||||
/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */
|
||||
#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */
|
||||
#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */
|
||||
#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */
|
||||
#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */
|
||||
#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */
|
||||
#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */
|
||||
#define XCHAL_INT8_EXTNUM 6 /* (intlevel 2) */
|
||||
#define XCHAL_INT9_EXTNUM 7 /* (intlevel 3) */
|
||||
#define XCHAL_INT12_EXTNUM 8 /* (intlevel 4) */
|
||||
#define XCHAL_INT14_EXTNUM 9 /* (intlevel 7) */
|
||||
#define XCHAL_INT15_EXTNUM 10 /* (intlevel 1) */
|
||||
#define XCHAL_INT16_EXTNUM 11 /* (intlevel 1) */
|
||||
#define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */
|
||||
#define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */
|
||||
#define XCHAL_INT19_EXTNUM 14 /* (intlevel 1) */
|
||||
#define XCHAL_INT20_EXTNUM 15 /* (intlevel 1) */
|
||||
#define XCHAL_INT21_EXTNUM 16 /* (intlevel 3) */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
EXCEPTIONS and VECTORS
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
|
||||
number: 1 == XEA1 (old)
|
||||
2 == XEA2 (new)
|
||||
0 == XEAX (extern) or TX */
|
||||
#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
|
||||
#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
|
||||
#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
|
||||
#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
|
||||
#define XCHAL_HAVE_HALT 0 /* halt architecture option */
|
||||
#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
|
||||
#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
|
||||
#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
|
||||
#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
|
||||
#define XCHAL_VECBASE_RESET_VADDR 0x60000000 /* VECBASE reset value */
|
||||
#define XCHAL_VECBASE_RESET_PADDR 0x60000000
|
||||
#define XCHAL_RESET_VECBASE_OVERLAP 0
|
||||
|
||||
#define XCHAL_RESET_VECTOR0_VADDR 0x50000000
|
||||
#define XCHAL_RESET_VECTOR0_PADDR 0x50000000
|
||||
#define XCHAL_RESET_VECTOR1_VADDR 0x40000400
|
||||
#define XCHAL_RESET_VECTOR1_PADDR 0x40000400
|
||||
#define XCHAL_RESET_VECTOR_VADDR 0x50000000
|
||||
#define XCHAL_RESET_VECTOR_PADDR 0x50000000
|
||||
#define XCHAL_USER_VECOFS 0x00000340
|
||||
#define XCHAL_USER_VECTOR_VADDR 0x60000340
|
||||
#define XCHAL_USER_VECTOR_PADDR 0x60000340
|
||||
#define XCHAL_KERNEL_VECOFS 0x00000300
|
||||
#define XCHAL_KERNEL_VECTOR_VADDR 0x60000300
|
||||
#define XCHAL_KERNEL_VECTOR_PADDR 0x60000300
|
||||
#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x600003C0
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x600003C0
|
||||
#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
|
||||
#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
|
||||
#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
|
||||
#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
|
||||
#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
|
||||
#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
|
||||
#define XCHAL_WINDOW_VECTORS_VADDR 0x60000000
|
||||
#define XCHAL_WINDOW_VECTORS_PADDR 0x60000000
|
||||
#define XCHAL_INTLEVEL2_VECOFS 0x00000180
|
||||
#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x60000180
|
||||
#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x60000180
|
||||
#define XCHAL_INTLEVEL3_VECOFS 0x000001C0
|
||||
#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x600001C0
|
||||
#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x600001C0
|
||||
#define XCHAL_INTLEVEL4_VECOFS 0x00000200
|
||||
#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x60000200
|
||||
#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x60000200
|
||||
#define XCHAL_INTLEVEL5_VECOFS 0x00000240
|
||||
#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x60000240
|
||||
#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x60000240
|
||||
#define XCHAL_INTLEVEL6_VECOFS 0x00000280
|
||||
#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x60000280
|
||||
#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x60000280
|
||||
#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
|
||||
#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
|
||||
#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
|
||||
#define XCHAL_NMI_VECOFS 0x000002C0
|
||||
#define XCHAL_NMI_VECTOR_VADDR 0x600002C0
|
||||
#define XCHAL_NMI_VECTOR_PADDR 0x600002C0
|
||||
#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
|
||||
#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
|
||||
#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
DEBUG MODULE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/* Misc */
|
||||
#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */
|
||||
#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */
|
||||
#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */
|
||||
|
||||
/* On-Chip Debug (OCD) */
|
||||
#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
|
||||
#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
|
||||
#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
|
||||
#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */
|
||||
#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */
|
||||
|
||||
/* TRAX (in core) */
|
||||
#define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */
|
||||
#define XCHAL_TRAX_MEM_SIZE 262144 /* TRAX memory size in bytes */
|
||||
#define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */
|
||||
#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */
|
||||
#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */
|
||||
|
||||
/* Perf counters */
|
||||
#define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MMU
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/* See core-matmap.h header file for more details. */
|
||||
|
||||
#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
|
||||
#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
|
||||
#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */
|
||||
#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */
|
||||
#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
|
||||
#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */
|
||||
#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
|
||||
#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
|
||||
[autorefill] and protection)
|
||||
usable for an MMU-based OS */
|
||||
|
||||
/* If none of the above last 5 are set, it's a custom TLB configuration. */
|
||||
|
||||
#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */
|
||||
#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */
|
||||
#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MPU
|
||||
----------------------------------------------------------------------*/
|
||||
#define XCHAL_HAVE_MPU 0
|
||||
#define XCHAL_MPU_ENTRIES 0
|
||||
|
||||
#define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */
|
||||
#define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in background map */
|
||||
|
||||
#define XCHAL_MPU_ALIGN_BITS 0
|
||||
#define XCHAL_MPU_ALIGN 0
|
||||
|
||||
#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
|
||||
|
||||
|
||||
#endif /* _XTENSA_CORE_CONFIGURATION_H */
|
||||
|
198
target/xtensa/core-de212/gdb-config.c
Normal file
198
target/xtensa/core-de212/gdb-config.c
Normal file
@ -0,0 +1,198 @@
|
||||
/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
|
||||
|
||||
Copyright (c) 2003-2015 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
|
||||
XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
|
||||
XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
|
||||
XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
|
||||
XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
|
||||
XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
|
||||
XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
|
||||
XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
|
||||
XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
|
||||
XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
|
||||
XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0)
|
||||
XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0)
|
||||
XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0)
|
||||
XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0)
|
||||
XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0)
|
||||
XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0)
|
||||
XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0)
|
||||
XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0)
|
||||
XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0)
|
||||
XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0)
|
||||
XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0)
|
||||
XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0)
|
||||
XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0)
|
||||
XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0)
|
||||
XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0)
|
||||
XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0)
|
||||
XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0)
|
||||
XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0)
|
||||
XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0)
|
||||
XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0)
|
||||
XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0)
|
||||
XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0)
|
||||
XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0)
|
||||
XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0)
|
||||
XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0)
|
||||
XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0)
|
||||
XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
|
||||
XTREG( 37,148, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0)
|
||||
XTREG( 38,152, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)
|
||||
XTREG( 39,156,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0)
|
||||
XTREG( 40,160,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0)
|
||||
XTREG( 41,164,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0)
|
||||
XTREG( 42,168,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0)
|
||||
XTREG( 43,172,32, 4, 4,0x0210,0x0006,-1, 2,0x1100,acclo, 0,0,0,0,0,0)
|
||||
XTREG( 44,176, 8, 4, 4,0x0211,0x0006,-1, 2,0x1100,acchi, 0,0,0,0,0,0)
|
||||
XTREG( 45,180,32, 4, 4,0x0220,0x0006,-1, 2,0x1100,m0, 0,0,0,0,0,0)
|
||||
XTREG( 46,184,32, 4, 4,0x0221,0x0006,-1, 2,0x1100,m1, 0,0,0,0,0,0)
|
||||
XTREG( 47,188,32, 4, 4,0x0222,0x0006,-1, 2,0x1100,m2, 0,0,0,0,0,0)
|
||||
XTREG( 48,192,32, 4, 4,0x0223,0x0006,-1, 2,0x1100,m3, 0,0,0,0,0,0)
|
||||
XTREG( 49,196,32, 4, 4,0x03e6,0x000e,-1, 3,0x0110,expstate, 0,0,0,0,0,0)
|
||||
XTREG( 50,200,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0)
|
||||
XTREG( 51,204, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0)
|
||||
XTREG( 52,208, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0)
|
||||
XTREG( 53,212,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0)
|
||||
XTREG( 54,216,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0)
|
||||
XTREG( 55,220,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0)
|
||||
XTREG( 56,224,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0)
|
||||
XTREG( 57,228,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0)
|
||||
XTREG( 58,232,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0)
|
||||
XTREG( 59,236,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0)
|
||||
XTREG( 60,240,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0)
|
||||
XTREG( 61,244,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0)
|
||||
XTREG( 62,248,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0)
|
||||
XTREG( 63,252,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0)
|
||||
XTREG( 64,256,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0)
|
||||
XTREG( 65,260,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0)
|
||||
XTREG( 66,264,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0)
|
||||
XTREG( 67,268,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0)
|
||||
XTREG( 68,272,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0)
|
||||
XTREG( 69,276,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0)
|
||||
XTREG( 70,280,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0)
|
||||
XTREG( 71,284,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0)
|
||||
XTREG( 72,288,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0)
|
||||
XTREG( 73,292,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0)
|
||||
XTREG( 74,296,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0)
|
||||
XTREG( 75,300,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0)
|
||||
XTREG( 76,304,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0)
|
||||
XTREG( 77,308,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0)
|
||||
XTREG( 78,312,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0)
|
||||
XTREG( 79,316,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0)
|
||||
XTREG( 80,320,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0)
|
||||
XTREG( 81,324,22, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0)
|
||||
XTREG( 82,328,22, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0)
|
||||
XTREG( 83,332,22, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0)
|
||||
XTREG( 84,336,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
|
||||
XTREG( 85,340,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
|
||||
XTREG( 86,344, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0)
|
||||
XTREG( 87,348,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0)
|
||||
XTREG( 88,352,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0)
|
||||
XTREG( 89,356,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0)
|
||||
XTREG( 90,360,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0)
|
||||
XTREG( 91,364, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0)
|
||||
XTREG( 92,368,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
|
||||
XTREG( 93,372,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0)
|
||||
XTREG( 94,376,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0)
|
||||
XTREG( 95,380,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0)
|
||||
XTREG( 96,384,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0)
|
||||
XTREG( 97,388,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0)
|
||||
XTREG( 98,392,32, 8, 4,0x2015,0x000f,-2, 4,0x0101,pwrctl,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:20:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:20:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG( 99,400,32, 8, 4,0x2016,0x000f,-2, 4,0x0101,pwrstat,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:24:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:24:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(100,408, 1, 8, 4,0x2017,0x000f,-2, 4,0x0101,eristat,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:28:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:28:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(101,416,32, 8, 4,0x2018,0x000f,-2, 4,0x0101,cs_itctrl,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:d5:03:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:d5:03:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(102,424,16, 8, 4,0x2019,0x000f,-2, 4,0x0101,cs_claimset,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(103,432,16, 8, 4,0x201a,0x000f,-2, 4,0x0101,cs_claimclr,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(104,440,32, 8, 4,0x201b,0x000f,-2, 4,0x0101,cs_lockaccess,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(105,448,32, 8, 4,0x201c,0x000f,-2, 4,0x0101,cs_lockstatus,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(106,456, 1, 8, 4,0x201d,0x000f,-2, 4,0x0101,cs_authstatus,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(107,464,32, 8, 4,0x202c,0x0007,-2, 4,0x0101,trax_id,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(108,472,32, 8, 4,0x202d,0x000f,-2, 4,0x0101,trax_control,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(109,480,32, 8, 4,0x202e,0x000f,-2, 4,0x0101,trax_status,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:08:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:08:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(110,488,32, 8, 4,0x202f,0x000f,-2, 4,0x0101,trax_data,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:0c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:0c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(111,496,32, 8, 4,0x2030,0x000f,-2, 4,0x0101,trax_address,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:10:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:10:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(112,504,32, 8, 4,0x2031,0x000f,-2, 4,0x0101,trax_pctrigger,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:14:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:14:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(113,512,32, 8, 4,0x2032,0x000f,-2, 4,0x0101,trax_pcmatch,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:18:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:18:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(114,520,32, 8, 4,0x2033,0x000f,-2, 4,0x0101,trax_delay,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:1c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:1c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(115,528,32, 8, 4,0x2034,0x000f,-2, 4,0x0101,trax_memstart,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:20:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:20:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(116,536,32, 8, 4,0x2035,0x000f,-2, 4,0x0101,trax_memend,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:24:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:24:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(117,544,32, 8, 4,0x2043,0x0007,-2, 4,0x0101,ocdid,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(118,552,32, 8, 4,0x2044,0x000f,-2, 4,0x0101,ocd_dcrclr,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:08:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:08:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(119,560,32, 8, 4,0x2045,0x000f,-2, 4,0x0101,ocd_dcrset,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:0c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:0c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(120,568,32, 8, 4,0x2046,0x000f,-2, 4,0x0101,ocd_dsr,
|
||||
"03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:10:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:10:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
|
||||
XTREG(121,576,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0)
|
||||
XTREG(122,580,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0)
|
||||
XTREG(123,584,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0)
|
||||
XTREG(124,588,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0)
|
||||
XTREG(125,592,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0)
|
||||
XTREG(126,596,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0)
|
||||
XTREG(127,600,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0)
|
||||
XTREG(128,604,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0)
|
||||
XTREG(129,608,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0)
|
||||
XTREG(130,612,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0)
|
||||
XTREG(131,616,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0)
|
||||
XTREG(132,620,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0)
|
||||
XTREG(133,624,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0)
|
||||
XTREG(134,628,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0)
|
||||
XTREG(135,632,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0)
|
||||
XTREG(136,636,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0)
|
||||
XTREG(137,640, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel,
|
||||
0,0,&xtensa_mask0,0,0,0)
|
||||
XTREG(138,644, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum,
|
||||
0,0,&xtensa_mask1,0,0,0)
|
||||
XTREG(139,648, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe,
|
||||
0,0,&xtensa_mask2,0,0,0)
|
||||
XTREG(140,652, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,psexcm,
|
||||
0,0,&xtensa_mask3,0,0,0)
|
||||
XTREG(141,656, 2, 4, 4,0x200c,0x0006,-2, 6,0x1010,pscallinc,
|
||||
0,0,&xtensa_mask4,0,0,0)
|
||||
XTREG(142,660, 4, 4, 4,0x200d,0x0006,-2, 6,0x1010,psowb,
|
||||
0,0,&xtensa_mask5,0,0,0)
|
||||
XTREG(143,664,40, 8, 4,0x200e,0x0006,-2, 6,0x1010,acc,
|
||||
0,0,&xtensa_mask6,0,0,0)
|
||||
XTREG_END
|
14566
target/xtensa/core-de212/xtensa-modules.c
Normal file
14566
target/xtensa/core-de212/xtensa-modules.c
Normal file
File diff suppressed because it is too large
Load Diff
53
target/xtensa/core-sample_controller.c
Normal file
53
target/xtensa/core-sample_controller.c
Normal file
@ -0,0 +1,53 @@
|
||||
/*
|
||||
* Copyright (c) 2018, Max Filippov, Open Source and Linux Lab.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of the Open Source and Linux Lab nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#include "cpu.h"
|
||||
#include "exec/exec-all.h"
|
||||
#include "exec/gdbstub.h"
|
||||
#include "qemu-common.h"
|
||||
#include "qemu/host-utils.h"
|
||||
|
||||
#include "core-sample_controller/core-isa.h"
|
||||
#include "overlay_tool.h"
|
||||
|
||||
#define xtensa_modules xtensa_modules_sample_controller
|
||||
#include "core-sample_controller/xtensa-modules.c"
|
||||
|
||||
static XtensaConfig sample_controller __attribute__((unused)) = {
|
||||
.name = "sample_controller",
|
||||
.gdb_regmap = {
|
||||
.reg = {
|
||||
#include "core-sample_controller/gdb-config.c"
|
||||
}
|
||||
},
|
||||
.isa_internal = &xtensa_modules,
|
||||
.clock_freq_khz = 10000,
|
||||
DEFAULT_SECTIONS
|
||||
};
|
||||
|
||||
REGISTER_CORE(sample_controller)
|
644
target/xtensa/core-sample_controller/core-isa.h
Normal file
644
target/xtensa/core-sample_controller/core-isa.h
Normal file
@ -0,0 +1,644 @@
|
||||
/*
|
||||
* xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
|
||||
* processor CORE configuration
|
||||
*
|
||||
* See <xtensa/config/core.h>, which includes this file, for more details.
|
||||
*/
|
||||
|
||||
/* Xtensa processor core configuration information.
|
||||
|
||||
Copyright (c) 1999-2016 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
#ifndef _XTENSA_CORE_CONFIGURATION_H
|
||||
#define _XTENSA_CORE_CONFIGURATION_H
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
Parameters Useful for Any Code, USER or PRIVILEGED
|
||||
****************************************************************************/
|
||||
|
||||
/*
|
||||
* Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
|
||||
* configured, and a value of 0 otherwise. These macros are always defined.
|
||||
*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
ISA
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
|
||||
#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
|
||||
#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */
|
||||
#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */
|
||||
#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */
|
||||
#define XCHAL_HAVE_DEBUG 1 /* debug option */
|
||||
#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
|
||||
#define XCHAL_HAVE_LOOPS 0 /* zero-overhead loops */
|
||||
#define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
|
||||
#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
|
||||
#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
|
||||
#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
|
||||
#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */
|
||||
#define XCHAL_HAVE_CLAMPS 0 /* CLAMPS instruction */
|
||||
#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
|
||||
#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
|
||||
#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */
|
||||
#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */
|
||||
#define XCHAL_HAVE_L32R 1 /* L32R instruction */
|
||||
#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
|
||||
#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
|
||||
#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
|
||||
#define XCHAL_HAVE_EXCLUSIVE 0 /* L32EX/S32EX instructions */
|
||||
#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
|
||||
#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
|
||||
#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
|
||||
#define XCHAL_HAVE_ABS 1 /* ABS instruction */
|
||||
/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
|
||||
/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
|
||||
#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
|
||||
#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
|
||||
#define XCHAL_HAVE_SPECULATION 0 /* speculation */
|
||||
#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
|
||||
#define XCHAL_NUM_CONTEXTS 1 /* */
|
||||
#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */
|
||||
#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
|
||||
#define XCHAL_HAVE_PRID 1 /* processor ID register */
|
||||
#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
|
||||
#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */
|
||||
#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
|
||||
#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
|
||||
#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
|
||||
#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */
|
||||
#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */
|
||||
#define XCHAL_HAVE_THREADPTR 0 /* THREADPTR register */
|
||||
#define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */
|
||||
#define XCHAL_HAVE_CP 0 /* CPENABLE reg (coprocessor) */
|
||||
#define XCHAL_CP_MAXCFG 0 /* max allowed cp id plus one */
|
||||
#define XCHAL_HAVE_MAC16 0 /* MAC16 package */
|
||||
|
||||
#define XCHAL_HAVE_FUSION 0 /* Fusion*/
|
||||
#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */
|
||||
#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */
|
||||
#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */
|
||||
#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */
|
||||
#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */
|
||||
#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */
|
||||
#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */
|
||||
#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */
|
||||
#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */
|
||||
#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */
|
||||
#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */
|
||||
#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */
|
||||
#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */
|
||||
#define XCHAL_HAVE_HIFI_MINI 0
|
||||
|
||||
|
||||
|
||||
#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
|
||||
#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */
|
||||
#define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */
|
||||
#define XCHAL_HAVE_FP 0 /* single prec floating point */
|
||||
#define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */
|
||||
#define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */
|
||||
#define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */
|
||||
#define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */
|
||||
#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
|
||||
#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */
|
||||
#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/
|
||||
#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */
|
||||
#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/
|
||||
#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */
|
||||
#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */
|
||||
|
||||
#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */
|
||||
#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */
|
||||
#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
|
||||
#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
|
||||
|
||||
#define XCHAL_HAVE_FUSIONG 0 /* FusionG */
|
||||
#define XCHAL_HAVE_FUSIONG3 0 /* FusionG3 */
|
||||
#define XCHAL_HAVE_FUSIONG_SP_VFPU 0 /* sp_vfpu option on FusionG */
|
||||
#define XCHAL_HAVE_FUSIONG_DP_VFPU 0 /* dp_vfpu option on FusionG */
|
||||
#define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */
|
||||
|
||||
#define XCHAL_HAVE_PDX 0 /* PDX */
|
||||
#define XCHAL_PDX_SIMD32 0 /* simd32 for PDX */
|
||||
#define XCHAL_HAVE_PDX4 0 /* PDX4 */
|
||||
#define XCHAL_HAVE_PDX8 0 /* PDX8 */
|
||||
#define XCHAL_HAVE_PDX16 0 /* PDX16 */
|
||||
|
||||
#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
|
||||
#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */
|
||||
#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
|
||||
#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */
|
||||
#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */
|
||||
#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */
|
||||
#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */
|
||||
#define XCHAL_HAVE_BBENEP_SP_VFPU 0 /* sp_vfpu option on BBE-EP */
|
||||
#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
|
||||
#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */
|
||||
#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
|
||||
#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */
|
||||
#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
|
||||
#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
|
||||
#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
|
||||
#define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */
|
||||
#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
|
||||
|
||||
#define XCHAL_HAVE_VISION 0 /* Vision P5/P6 */
|
||||
#define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */
|
||||
#define XCHAL_VISION_TYPE 0 /* Vision P5, P6, or P3 */
|
||||
#define XCHAL_VISION_QUAD_MAC_TYPE 0 /* quad_mac option on Vision P6 */
|
||||
#define XCHAL_HAVE_VISION_HISTOGRAM 0 /* histogram option on Vision P5/P6 */
|
||||
#define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision P5/P6 */
|
||||
#define XCHAL_HAVE_VISION_HP_VFPU 0 /* hp_vfpu option on Vision P6 */
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MISC
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */
|
||||
#define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* size of write buffer */
|
||||
#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */
|
||||
#define XCHAL_DATA_WIDTH 4 /* data width in bytes */
|
||||
#define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay
|
||||
(1 = 5-stage, 2 = 7-stage) */
|
||||
#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */
|
||||
#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */
|
||||
/* In T1050, applies to selected core load and store instructions (see ISA): */
|
||||
#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
|
||||
#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
|
||||
#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */
|
||||
#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/
|
||||
|
||||
#define XCHAL_SW_VERSION 1200004 /* sw version of this header */
|
||||
|
||||
#define XCHAL_CORE_ID "sample_controller" /* alphanum core name
|
||||
(CoreID) set in the Xtensa
|
||||
Processor Generator */
|
||||
|
||||
#define XCHAL_BUILD_UNIQUE_ID 0x00064D47 /* 22-bit sw build ID */
|
||||
|
||||
/*
|
||||
* These definitions describe the hardware targeted by this software.
|
||||
*/
|
||||
#define XCHAL_HW_CONFIGID0 0xC280DAFE /* ConfigID hi 32 bits*/
|
||||
#define XCHAL_HW_CONFIGID1 0x21064D47 /* ConfigID lo 32 bits*/
|
||||
#define XCHAL_HW_VERSION_NAME "LX7.0.4" /* full version name */
|
||||
#define XCHAL_HW_VERSION_MAJOR 2700 /* major ver# of targeted hw */
|
||||
#define XCHAL_HW_VERSION_MINOR 4 /* minor ver# of targeted hw */
|
||||
#define XCHAL_HW_VERSION 270004 /* major*100+minor */
|
||||
#define XCHAL_HW_REL_LX7 1
|
||||
#define XCHAL_HW_REL_LX7_0 1
|
||||
#define XCHAL_HW_REL_LX7_0_4 1
|
||||
#define XCHAL_HW_CONFIGID_RELIABLE 1
|
||||
/* If software targets a *range* of hardware versions, these are the bounds: */
|
||||
#define XCHAL_HW_MIN_VERSION_MAJOR 2700 /* major v of earliest tgt hw */
|
||||
#define XCHAL_HW_MIN_VERSION_MINOR 4 /* minor v of earliest tgt hw */
|
||||
#define XCHAL_HW_MIN_VERSION 270004 /* earliest targeted hw */
|
||||
#define XCHAL_HW_MAX_VERSION_MAJOR 2700 /* major v of latest tgt hw */
|
||||
#define XCHAL_HW_MAX_VERSION_MINOR 4 /* minor v of latest tgt hw */
|
||||
#define XCHAL_HW_MAX_VERSION 270004 /* latest targeted hw */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
CACHE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_ICACHE_LINESIZE 4 /* I-cache line size in bytes */
|
||||
#define XCHAL_DCACHE_LINESIZE 4 /* D-cache line size in bytes */
|
||||
#define XCHAL_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */
|
||||
#define XCHAL_DCACHE_LINEWIDTH 2 /* log2(D line size in bytes) */
|
||||
|
||||
#define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */
|
||||
#define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */
|
||||
|
||||
#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */
|
||||
#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
|
||||
|
||||
#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */
|
||||
#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */
|
||||
#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */
|
||||
#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */
|
||||
#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */
|
||||
#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */
|
||||
#define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */
|
||||
#define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */
|
||||
#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */
|
||||
#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */
|
||||
|
||||
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
|
||||
****************************************************************************/
|
||||
|
||||
|
||||
#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
CACHE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_PIF 1 /* any outbound bus present */
|
||||
|
||||
#define XCHAL_HAVE_AXI 0 /* AXI bus */
|
||||
#define XCHAL_HAVE_AXI_ECC 0 /* ECC on AXI bus */
|
||||
#define XCHAL_HAVE_ACELITE 0 /* ACELite bus */
|
||||
|
||||
#define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */
|
||||
#define XCHAL_HAVE_PIF_REQ_ATTR 0 /* pif attribute */
|
||||
|
||||
/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
|
||||
|
||||
/* Number of cache sets in log2(lines per way): */
|
||||
#define XCHAL_ICACHE_SETWIDTH 0
|
||||
#define XCHAL_DCACHE_SETWIDTH 0
|
||||
|
||||
/* Cache set associativity (number of ways): */
|
||||
#define XCHAL_ICACHE_WAYS 1
|
||||
#define XCHAL_DCACHE_WAYS 1
|
||||
|
||||
/* Cache features: */
|
||||
#define XCHAL_ICACHE_LINE_LOCKABLE 0
|
||||
#define XCHAL_DCACHE_LINE_LOCKABLE 0
|
||||
#define XCHAL_ICACHE_ECC_PARITY 0
|
||||
#define XCHAL_DCACHE_ECC_PARITY 0
|
||||
|
||||
/* Cache access size in bytes (affects operation of SICW instruction): */
|
||||
#define XCHAL_ICACHE_ACCESS_SIZE 1
|
||||
#define XCHAL_DCACHE_ACCESS_SIZE 1
|
||||
|
||||
#define XCHAL_DCACHE_BANKS 0 /* number of banks */
|
||||
|
||||
/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
|
||||
#define XCHAL_CA_BITS 4
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
INTERNAL I/D RAM/ROMs and XLMI
|
||||
----------------------------------------------------------------------*/
|
||||
#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
|
||||
#define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */
|
||||
#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
|
||||
#define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */
|
||||
#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
|
||||
#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
|
||||
|
||||
/* Instruction RAM 0: */
|
||||
#define XCHAL_INSTRAM0_VADDR 0x40000000 /* virtual address */
|
||||
#define XCHAL_INSTRAM0_PADDR 0x40000000 /* physical address */
|
||||
#define XCHAL_INSTRAM0_SIZE 131072 /* size in bytes */
|
||||
#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
|
||||
#define XCHAL_HAVE_INSTRAM0
|
||||
#define XCHAL_INSTRAM0_HAVE_IDMA 0 /* idma supported by this local memory */
|
||||
|
||||
/* Data RAM 0: */
|
||||
#define XCHAL_DATARAM0_VADDR 0x3FFE0000 /* virtual address */
|
||||
#define XCHAL_DATARAM0_PADDR 0x3FFE0000 /* physical address */
|
||||
#define XCHAL_DATARAM0_SIZE 131072 /* size in bytes */
|
||||
#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
|
||||
#define XCHAL_DATARAM0_BANKS 1 /* number of banks */
|
||||
#define XCHAL_HAVE_DATARAM0
|
||||
#define XCHAL_DATARAM0_HAVE_IDMA 0 /* idma supported by this local memory */
|
||||
|
||||
/* Data RAM 1: */
|
||||
#define XCHAL_DATARAM1_VADDR 0x3FFC0000 /* virtual address */
|
||||
#define XCHAL_DATARAM1_PADDR 0x3FFC0000 /* physical address */
|
||||
#define XCHAL_DATARAM1_SIZE 131072 /* size in bytes */
|
||||
#define XCHAL_DATARAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */
|
||||
#define XCHAL_DATARAM1_BANKS 1 /* number of banks */
|
||||
#define XCHAL_HAVE_DATARAM1
|
||||
#define XCHAL_DATARAM1_HAVE_IDMA 0 /* idma supported by this local memory */
|
||||
|
||||
#define XCHAL_HAVE_IDMA 0
|
||||
#define XCHAL_HAVE_IDMA_TRANSPOSE 0
|
||||
|
||||
#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
INTERRUPTS and TIMERS
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
|
||||
#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
|
||||
#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
|
||||
#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
|
||||
#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
|
||||
#define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */
|
||||
#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
|
||||
#define XCHAL_NUM_EXTINTERRUPTS 17 /* num of external interrupts */
|
||||
#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
|
||||
(not including level zero) */
|
||||
#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */
|
||||
/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
|
||||
|
||||
/* Masks of interrupts at each interrupt level: */
|
||||
#define XCHAL_INTLEVEL1_MASK 0x001F80FF
|
||||
#define XCHAL_INTLEVEL2_MASK 0x00000100
|
||||
#define XCHAL_INTLEVEL3_MASK 0x00200E00
|
||||
#define XCHAL_INTLEVEL4_MASK 0x00001000
|
||||
#define XCHAL_INTLEVEL5_MASK 0x00002000
|
||||
#define XCHAL_INTLEVEL6_MASK 0x00000000
|
||||
#define XCHAL_INTLEVEL7_MASK 0x00004000
|
||||
|
||||
/* Masks of interrupts at each range 1..n of interrupt levels: */
|
||||
#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x001F80FF
|
||||
#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x001F81FF
|
||||
#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x003F8FFF
|
||||
#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x003F9FFF
|
||||
#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x003FBFFF
|
||||
#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x003FBFFF
|
||||
#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF
|
||||
|
||||
/* Level of each interrupt: */
|
||||
#define XCHAL_INT0_LEVEL 1
|
||||
#define XCHAL_INT1_LEVEL 1
|
||||
#define XCHAL_INT2_LEVEL 1
|
||||
#define XCHAL_INT3_LEVEL 1
|
||||
#define XCHAL_INT4_LEVEL 1
|
||||
#define XCHAL_INT5_LEVEL 1
|
||||
#define XCHAL_INT6_LEVEL 1
|
||||
#define XCHAL_INT7_LEVEL 1
|
||||
#define XCHAL_INT8_LEVEL 2
|
||||
#define XCHAL_INT9_LEVEL 3
|
||||
#define XCHAL_INT10_LEVEL 3
|
||||
#define XCHAL_INT11_LEVEL 3
|
||||
#define XCHAL_INT12_LEVEL 4
|
||||
#define XCHAL_INT13_LEVEL 5
|
||||
#define XCHAL_INT14_LEVEL 7
|
||||
#define XCHAL_INT15_LEVEL 1
|
||||
#define XCHAL_INT16_LEVEL 1
|
||||
#define XCHAL_INT17_LEVEL 1
|
||||
#define XCHAL_INT18_LEVEL 1
|
||||
#define XCHAL_INT19_LEVEL 1
|
||||
#define XCHAL_INT20_LEVEL 1
|
||||
#define XCHAL_INT21_LEVEL 3
|
||||
#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
|
||||
#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
|
||||
#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
|
||||
EXCSAVE/EPS/EPC_n, RFI n) */
|
||||
|
||||
/* Type of each interrupt: */
|
||||
#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
|
||||
#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE
|
||||
#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
|
||||
#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
|
||||
/* Masks of interrupts for each type of interrupt: */
|
||||
#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000
|
||||
#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880
|
||||
#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F8000
|
||||
#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F
|
||||
#define XCHAL_INTTYPE_MASK_TIMER 0x00002440
|
||||
#define XCHAL_INTTYPE_MASK_NMI 0x00004000
|
||||
#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_PROFILING 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_GS_ERR 0x00000000
|
||||
|
||||
/* Interrupt numbers assigned to specific interrupt sources: */
|
||||
#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
|
||||
#define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */
|
||||
#define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */
|
||||
#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
|
||||
#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */
|
||||
|
||||
/* Interrupt numbers for levels at which only one interrupt is configured: */
|
||||
#define XCHAL_INTLEVEL2_NUM 8
|
||||
#define XCHAL_INTLEVEL4_NUM 12
|
||||
#define XCHAL_INTLEVEL5_NUM 13
|
||||
#define XCHAL_INTLEVEL7_NUM 14
|
||||
/* (There are many interrupts each at level(s) 1, 3.) */
|
||||
|
||||
|
||||
/*
|
||||
* External interrupt mapping.
|
||||
* These macros describe how Xtensa processor interrupt numbers
|
||||
* (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
|
||||
* map to external BInterrupt<n> pins, for those interrupts
|
||||
* configured as external (level-triggered, edge-triggered, or NMI).
|
||||
* See the Xtensa processor databook for more details.
|
||||
*/
|
||||
|
||||
/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */
|
||||
#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */
|
||||
#define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */
|
||||
#define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */
|
||||
#define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */
|
||||
#define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */
|
||||
/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */
|
||||
#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */
|
||||
#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */
|
||||
#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */
|
||||
#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */
|
||||
#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */
|
||||
#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */
|
||||
#define XCHAL_INT8_EXTNUM 6 /* (intlevel 2) */
|
||||
#define XCHAL_INT9_EXTNUM 7 /* (intlevel 3) */
|
||||
#define XCHAL_INT12_EXTNUM 8 /* (intlevel 4) */
|
||||
#define XCHAL_INT14_EXTNUM 9 /* (intlevel 7) */
|
||||
#define XCHAL_INT15_EXTNUM 10 /* (intlevel 1) */
|
||||
#define XCHAL_INT16_EXTNUM 11 /* (intlevel 1) */
|
||||
#define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */
|
||||
#define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */
|
||||
#define XCHAL_INT19_EXTNUM 14 /* (intlevel 1) */
|
||||
#define XCHAL_INT20_EXTNUM 15 /* (intlevel 1) */
|
||||
#define XCHAL_INT21_EXTNUM 16 /* (intlevel 3) */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
EXCEPTIONS and VECTORS
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
|
||||
number: 1 == XEA1 (old)
|
||||
2 == XEA2 (new)
|
||||
0 == XEAX (extern) or TX */
|
||||
#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
|
||||
#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
|
||||
#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
|
||||
#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
|
||||
#define XCHAL_HAVE_HALT 0 /* halt architecture option */
|
||||
#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
|
||||
#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
|
||||
#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
|
||||
#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
|
||||
#define XCHAL_VECBASE_RESET_VADDR 0x40000000 /* VECBASE reset value */
|
||||
#define XCHAL_VECBASE_RESET_PADDR 0x40000000
|
||||
#define XCHAL_RESET_VECBASE_OVERLAP 0
|
||||
|
||||
#define XCHAL_RESET_VECTOR0_VADDR 0x50000000
|
||||
#define XCHAL_RESET_VECTOR0_PADDR 0x50000000
|
||||
#define XCHAL_RESET_VECTOR1_VADDR 0x40000400
|
||||
#define XCHAL_RESET_VECTOR1_PADDR 0x40000400
|
||||
#define XCHAL_RESET_VECTOR_VADDR 0x50000000
|
||||
#define XCHAL_RESET_VECTOR_PADDR 0x50000000
|
||||
#define XCHAL_USER_VECOFS 0x00000340
|
||||
#define XCHAL_USER_VECTOR_VADDR 0x40000340
|
||||
#define XCHAL_USER_VECTOR_PADDR 0x40000340
|
||||
#define XCHAL_KERNEL_VECOFS 0x00000300
|
||||
#define XCHAL_KERNEL_VECTOR_VADDR 0x40000300
|
||||
#define XCHAL_KERNEL_VECTOR_PADDR 0x40000300
|
||||
#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x400003C0
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x400003C0
|
||||
#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
|
||||
#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
|
||||
#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
|
||||
#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
|
||||
#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
|
||||
#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
|
||||
#define XCHAL_WINDOW_VECTORS_VADDR 0x40000000
|
||||
#define XCHAL_WINDOW_VECTORS_PADDR 0x40000000
|
||||
#define XCHAL_INTLEVEL2_VECOFS 0x00000180
|
||||
#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x40000180
|
||||
#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x40000180
|
||||
#define XCHAL_INTLEVEL3_VECOFS 0x000001C0
|
||||
#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x400001C0
|
||||
#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x400001C0
|
||||
#define XCHAL_INTLEVEL4_VECOFS 0x00000200
|
||||
#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x40000200
|
||||
#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x40000200
|
||||
#define XCHAL_INTLEVEL5_VECOFS 0x00000240
|
||||
#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x40000240
|
||||
#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x40000240
|
||||
#define XCHAL_INTLEVEL6_VECOFS 0x00000280
|
||||
#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x40000280
|
||||
#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x40000280
|
||||
#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
|
||||
#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
|
||||
#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
|
||||
#define XCHAL_NMI_VECOFS 0x000002C0
|
||||
#define XCHAL_NMI_VECTOR_VADDR 0x400002C0
|
||||
#define XCHAL_NMI_VECTOR_PADDR 0x400002C0
|
||||
#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
|
||||
#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
|
||||
#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
DEBUG MODULE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/* Misc */
|
||||
#define XCHAL_HAVE_DEBUG_ERI 0 /* ERI to debug module */
|
||||
#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */
|
||||
#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */
|
||||
|
||||
/* On-Chip Debug (OCD) */
|
||||
#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
|
||||
#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
|
||||
#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
|
||||
#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */
|
||||
#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */
|
||||
|
||||
/* TRAX (in core) */
|
||||
#define XCHAL_HAVE_TRAX 0 /* TRAX in debug module */
|
||||
#define XCHAL_TRAX_MEM_SIZE 0 /* TRAX memory size in bytes */
|
||||
#define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */
|
||||
#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */
|
||||
#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */
|
||||
|
||||
/* Perf counters */
|
||||
#define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MMU
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/* See core-matmap.h header file for more details. */
|
||||
|
||||
#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
|
||||
#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
|
||||
#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */
|
||||
#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */
|
||||
#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
|
||||
#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */
|
||||
#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
|
||||
#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
|
||||
[autorefill] and protection)
|
||||
usable for an MMU-based OS */
|
||||
|
||||
/* If none of the above last 5 are set, it's a custom TLB configuration. */
|
||||
|
||||
#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */
|
||||
#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */
|
||||
#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MPU
|
||||
----------------------------------------------------------------------*/
|
||||
#define XCHAL_HAVE_MPU 0
|
||||
#define XCHAL_MPU_ENTRIES 0
|
||||
|
||||
#define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */
|
||||
#define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in bg map*/
|
||||
#define XCHAL_MPU_BG_CACHEADRDIS 0 /* default CACHEADRDIS for bg */
|
||||
|
||||
#define XCHAL_MPU_ALIGN_BITS 0
|
||||
#define XCHAL_MPU_ALIGN 0
|
||||
|
||||
#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
|
||||
|
||||
|
||||
#endif /* _XTENSA_CORE_CONFIGURATION_H */
|
||||
|
141
target/xtensa/core-sample_controller/gdb-config.c
Normal file
141
target/xtensa/core-sample_controller/gdb-config.c
Normal file
@ -0,0 +1,141 @@
|
||||
/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
|
||||
|
||||
Copyright (c) 2003-2016 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
|
||||
XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
|
||||
XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
|
||||
XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
|
||||
XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
|
||||
XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
|
||||
XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
|
||||
XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
|
||||
XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
|
||||
XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
|
||||
XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0)
|
||||
XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0)
|
||||
XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0)
|
||||
XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0)
|
||||
XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0)
|
||||
XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0)
|
||||
XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0)
|
||||
XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0)
|
||||
XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0)
|
||||
XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0)
|
||||
XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0)
|
||||
XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0)
|
||||
XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0)
|
||||
XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0)
|
||||
XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0)
|
||||
XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0)
|
||||
XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0)
|
||||
XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0)
|
||||
XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0)
|
||||
XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0)
|
||||
XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0)
|
||||
XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0)
|
||||
XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0)
|
||||
XTREG( 33,132, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
|
||||
XTREG( 34,136, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0)
|
||||
XTREG( 35,140, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)
|
||||
XTREG( 36,144,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0)
|
||||
XTREG( 37,148,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0)
|
||||
XTREG( 38,152,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0)
|
||||
XTREG( 39,156,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0)
|
||||
XTREG( 40,160,32, 4, 4,0x03e6,0x000e,-1, 3,0x0110,expstate, 0,0,0,0,0,0)
|
||||
XTREG( 41,164,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0)
|
||||
XTREG( 42,168, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0)
|
||||
XTREG( 43,172, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0)
|
||||
XTREG( 44,176,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0)
|
||||
XTREG( 45,180,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0)
|
||||
XTREG( 46,184,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0)
|
||||
XTREG( 47,188,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0)
|
||||
XTREG( 48,192,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0)
|
||||
XTREG( 49,196,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0)
|
||||
XTREG( 50,200,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0)
|
||||
XTREG( 51,204,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0)
|
||||
XTREG( 52,208,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0)
|
||||
XTREG( 53,212,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0)
|
||||
XTREG( 54,216,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0)
|
||||
XTREG( 55,220,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0)
|
||||
XTREG( 56,224,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0)
|
||||
XTREG( 57,228,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0)
|
||||
XTREG( 58,232,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0)
|
||||
XTREG( 59,236,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0)
|
||||
XTREG( 60,240,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0)
|
||||
XTREG( 61,244,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0)
|
||||
XTREG( 62,248,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0)
|
||||
XTREG( 63,252,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0)
|
||||
XTREG( 64,256,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0)
|
||||
XTREG( 65,260,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0)
|
||||
XTREG( 66,264,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0)
|
||||
XTREG( 67,268,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0)
|
||||
XTREG( 68,272,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0)
|
||||
XTREG( 69,276,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0)
|
||||
XTREG( 70,280,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0)
|
||||
XTREG( 71,284,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0)
|
||||
XTREG( 72,288,22, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0)
|
||||
XTREG( 73,292,22, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0)
|
||||
XTREG( 74,296,22, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0)
|
||||
XTREG( 75,300,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
|
||||
XTREG( 76,304,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
|
||||
XTREG( 77,308, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0)
|
||||
XTREG( 78,312,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0)
|
||||
XTREG( 79,316,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0)
|
||||
XTREG( 80,320,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0)
|
||||
XTREG( 81,324,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0)
|
||||
XTREG( 82,328, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0)
|
||||
XTREG( 83,332,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
|
||||
XTREG( 84,336,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0)
|
||||
XTREG( 85,340,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0)
|
||||
XTREG( 86,344,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0)
|
||||
XTREG( 87,348,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0)
|
||||
XTREG( 88,352,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0)
|
||||
XTREG( 89,356,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0)
|
||||
XTREG( 90,360,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0)
|
||||
XTREG( 91,364,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0)
|
||||
XTREG( 92,368,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0)
|
||||
XTREG( 93,372,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0)
|
||||
XTREG( 94,376,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0)
|
||||
XTREG( 95,380,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0)
|
||||
XTREG( 96,384,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0)
|
||||
XTREG( 97,388,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0)
|
||||
XTREG( 98,392,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0)
|
||||
XTREG( 99,396,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0)
|
||||
XTREG(100,400,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0)
|
||||
XTREG(101,404,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0)
|
||||
XTREG(102,408,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0)
|
||||
XTREG(103,412,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0)
|
||||
XTREG(104,416,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0)
|
||||
XTREG(105,420, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel,
|
||||
0,0,&xtensa_mask0,0,0,0)
|
||||
XTREG(106,424, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum,
|
||||
0,0,&xtensa_mask1,0,0,0)
|
||||
XTREG(107,428, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe,
|
||||
0,0,&xtensa_mask2,0,0,0)
|
||||
XTREG(108,432, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,psexcm,
|
||||
0,0,&xtensa_mask3,0,0,0)
|
||||
XTREG(109,436, 2, 4, 4,0x200c,0x0006,-2, 6,0x1010,pscallinc,
|
||||
0,0,&xtensa_mask4,0,0,0)
|
||||
XTREG(110,440, 4, 4, 4,0x200d,0x0006,-2, 6,0x1010,psowb,
|
||||
0,0,&xtensa_mask5,0,0,0)
|
||||
XTREG_END
|
11377
target/xtensa/core-sample_controller/xtensa-modules.c
Normal file
11377
target/xtensa/core-sample_controller/xtensa-modules.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -503,10 +503,15 @@ void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
|
||||
|
||||
#ifdef TARGET_WORDS_BIGENDIAN
|
||||
#define XTENSA_DEFAULT_CPU_MODEL "fsf"
|
||||
#define XTENSA_DEFAULT_CPU_NOMMU_MODEL "fsf"
|
||||
#else
|
||||
#define XTENSA_DEFAULT_CPU_MODEL "dc232b"
|
||||
#define XTENSA_DEFAULT_CPU_NOMMU_MODEL "de212"
|
||||
#endif
|
||||
#define XTENSA_DEFAULT_CPU_TYPE XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_MODEL)
|
||||
#define XTENSA_DEFAULT_CPU_TYPE \
|
||||
XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_MODEL)
|
||||
#define XTENSA_DEFAULT_CPU_NOMMU_TYPE \
|
||||
XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_NOMMU_MODEL)
|
||||
|
||||
#define cpu_init(cpu_model) cpu_generic_init(TYPE_XTENSA_CPU, cpu_model)
|
||||
|
||||
|
@ -342,24 +342,24 @@
|
||||
.dtlb = TLB_TEMPLATE
|
||||
|
||||
#ifndef XCHAL_SYSROM0_PADDR
|
||||
#define XCHAL_SYSROM0_PADDR 0x60000000
|
||||
#define XCHAL_SYSROM0_PADDR 0x50000000
|
||||
#define XCHAL_SYSROM0_SIZE 0x04000000
|
||||
#endif
|
||||
|
||||
#ifndef XCHAL_SYSRAM0_PADDR
|
||||
#define XCHAL_SYSRAM0_PADDR 0x50000000
|
||||
#define XCHAL_SYSRAM0_PADDR 0x60000000
|
||||
#define XCHAL_SYSRAM0_SIZE 0x04000000
|
||||
#endif
|
||||
|
||||
#else
|
||||
|
||||
#ifndef XCHAL_SYSROM0_PADDR
|
||||
#define XCHAL_SYSROM0_PADDR 0x60000000
|
||||
#define XCHAL_SYSROM0_PADDR 0x50000000
|
||||
#define XCHAL_SYSROM0_SIZE 0x04000000
|
||||
#endif
|
||||
|
||||
#ifndef XCHAL_SYSRAM0_PADDR
|
||||
#define XCHAL_SYSRAM0_PADDR 0x50000000
|
||||
#define XCHAL_SYSRAM0_PADDR 0x60000000
|
||||
#define XCHAL_SYSRAM0_SIZE 0x04000000
|
||||
#endif
|
||||
|
||||
|
@ -942,7 +942,7 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
|
||||
unsigned char b[MAX_INSN_LENGTH] = {cpu_ldub_code(env, dc->pc)};
|
||||
unsigned len = xtensa_op0_insn_len(dc, b[0]);
|
||||
xtensa_format fmt;
|
||||
unsigned slot, slots;
|
||||
int slot, slots;
|
||||
unsigned i;
|
||||
|
||||
if (len == XTENSA_UNDEFINED) {
|
||||
@ -969,7 +969,7 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
|
||||
slots = xtensa_format_num_slots(isa, fmt);
|
||||
for (slot = 0; slot < slots; ++slot) {
|
||||
xtensa_opcode opc;
|
||||
unsigned opnd, vopnd, opnds;
|
||||
int opnd, vopnd, opnds;
|
||||
uint32_t raw_arg[MAX_OPCODE_ARGS];
|
||||
uint32_t arg[MAX_OPCODE_ARGS];
|
||||
XtensaOpcodeOps *ops;
|
||||
|
Loading…
Reference in New Issue
Block a user