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Add definitions for Freescale PowerPC implementations,
ie MPC5xx, MPC8xx, e200, e300, e500 and e600 cores. Make those CPUs and PowerPC 440 available for user-mode emulation, thus providing a way of testing their implementation specific instructions. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3681 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
j_mayer
parent
b4095fed95
commit
80d11f4467
827
target-ppc/cpu.h
827
target-ppc/cpu.h
@ -822,394 +822,447 @@ static inline int cpu_mmu_index (CPUState *env)
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#define xer_bc env->xer[0]
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/* SPR definitions */
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#define SPR_MQ (0x000)
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#define SPR_XER (0x001)
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#define SPR_601_VRTCU (0x004)
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#define SPR_601_VRTCL (0x005)
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#define SPR_601_UDECR (0x006)
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#define SPR_LR (0x008)
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#define SPR_CTR (0x009)
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#define SPR_DSISR (0x012)
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#define SPR_DAR (0x013) /* DAE for PowerPC 601 */
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#define SPR_601_RTCU (0x014)
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#define SPR_601_RTCL (0x015)
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#define SPR_DECR (0x016)
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#define SPR_SDR1 (0x019)
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#define SPR_SRR0 (0x01A)
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#define SPR_SRR1 (0x01B)
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#define SPR_AMR (0x01D)
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#define SPR_BOOKE_PID (0x030)
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#define SPR_BOOKE_DECAR (0x036)
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#define SPR_BOOKE_CSRR0 (0x03A)
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#define SPR_BOOKE_CSRR1 (0x03B)
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#define SPR_BOOKE_DEAR (0x03D)
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#define SPR_BOOKE_ESR (0x03E)
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#define SPR_BOOKE_IVPR (0x03F)
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#define SPR_8xx_EIE (0x050)
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#define SPR_8xx_EID (0x051)
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#define SPR_8xx_NRE (0x052)
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#define SPR_CTRL (0x088)
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#define SPR_58x_CMPA (0x090)
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#define SPR_58x_CMPB (0x091)
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#define SPR_58x_CMPC (0x092)
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#define SPR_58x_CMPD (0x093)
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#define SPR_58x_ICR (0x094)
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#define SPR_58x_DER (0x094)
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#define SPR_58x_COUNTA (0x096)
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#define SPR_58x_COUNTB (0x097)
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#define SPR_UCTRL (0x098)
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#define SPR_58x_CMPE (0x098)
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#define SPR_58x_CMPF (0x099)
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#define SPR_58x_CMPG (0x09A)
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#define SPR_58x_CMPH (0x09B)
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#define SPR_58x_LCTRL1 (0x09C)
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#define SPR_58x_LCTRL2 (0x09D)
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#define SPR_58x_ICTRL (0x09E)
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#define SPR_58x_BAR (0x09F)
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#define SPR_VRSAVE (0x100)
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#define SPR_USPRG0 (0x100)
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#define SPR_USPRG1 (0x101)
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#define SPR_USPRG2 (0x102)
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#define SPR_USPRG3 (0x103)
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#define SPR_USPRG4 (0x104)
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#define SPR_USPRG5 (0x105)
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#define SPR_USPRG6 (0x106)
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#define SPR_USPRG7 (0x107)
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#define SPR_VTBL (0x10C)
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#define SPR_VTBU (0x10D)
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#define SPR_SPRG0 (0x110)
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#define SPR_SPRG1 (0x111)
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#define SPR_SPRG2 (0x112)
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#define SPR_SPRG3 (0x113)
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#define SPR_SPRG4 (0x114)
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#define SPR_SCOMC (0x114)
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#define SPR_SPRG5 (0x115)
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#define SPR_SCOMD (0x115)
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#define SPR_SPRG6 (0x116)
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#define SPR_SPRG7 (0x117)
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#define SPR_ASR (0x118)
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#define SPR_EAR (0x11A)
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#define SPR_TBL (0x11C)
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#define SPR_TBU (0x11D)
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#define SPR_TBU40 (0x11E)
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#define SPR_SVR (0x11E)
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#define SPR_BOOKE_PIR (0x11E)
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#define SPR_PVR (0x11F)
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#define SPR_HSPRG0 (0x130)
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#define SPR_BOOKE_DBSR (0x130)
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#define SPR_HSPRG1 (0x131)
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#define SPR_HDSISR (0x132)
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#define SPR_HDAR (0x133)
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#define SPR_BOOKE_DBCR0 (0x134)
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#define SPR_IBCR (0x135)
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#define SPR_PURR (0x135)
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#define SPR_BOOKE_DBCR1 (0x135)
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#define SPR_DBCR (0x136)
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#define SPR_HDEC (0x136)
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#define SPR_BOOKE_DBCR2 (0x136)
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#define SPR_HIOR (0x137)
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#define SPR_MBAR (0x137)
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#define SPR_RMOR (0x138)
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#define SPR_BOOKE_IAC1 (0x138)
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#define SPR_HRMOR (0x139)
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#define SPR_BOOKE_IAC2 (0x139)
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#define SPR_HSRR0 (0x13A)
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#define SPR_BOOKE_IAC3 (0x13A)
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#define SPR_HSRR1 (0x13B)
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#define SPR_BOOKE_IAC4 (0x13B)
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#define SPR_LPCR (0x13C)
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#define SPR_BOOKE_DAC1 (0x13C)
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#define SPR_LPIDR (0x13D)
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#define SPR_DABR2 (0x13D)
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#define SPR_BOOKE_DAC2 (0x13D)
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#define SPR_BOOKE_DVC1 (0x13E)
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#define SPR_BOOKE_DVC2 (0x13F)
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#define SPR_BOOKE_TSR (0x150)
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#define SPR_BOOKE_TCR (0x154)
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#define SPR_BOOKE_IVOR0 (0x190)
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#define SPR_BOOKE_IVOR1 (0x191)
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#define SPR_BOOKE_IVOR2 (0x192)
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#define SPR_BOOKE_IVOR3 (0x193)
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#define SPR_BOOKE_IVOR4 (0x194)
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#define SPR_BOOKE_IVOR5 (0x195)
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#define SPR_BOOKE_IVOR6 (0x196)
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#define SPR_BOOKE_IVOR7 (0x197)
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#define SPR_BOOKE_IVOR8 (0x198)
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#define SPR_BOOKE_IVOR9 (0x199)
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#define SPR_BOOKE_IVOR10 (0x19A)
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#define SPR_BOOKE_IVOR11 (0x19B)
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#define SPR_BOOKE_IVOR12 (0x19C)
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#define SPR_BOOKE_IVOR13 (0x19D)
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#define SPR_BOOKE_IVOR14 (0x19E)
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#define SPR_BOOKE_IVOR15 (0x19F)
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#define SPR_BOOKE_SPEFSCR (0x200)
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#define SPR_E500_BBEAR (0x201)
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#define SPR_E500_BBTAR (0x202)
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#define SPR_ATBL (0x20E)
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#define SPR_ATBU (0x20F)
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#define SPR_IBAT0U (0x210)
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#define SPR_BOOKE_IVOR32 (0x210)
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#define SPR_IBAT0L (0x211)
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#define SPR_BOOKE_IVOR33 (0x211)
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#define SPR_IBAT1U (0x212)
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#define SPR_BOOKE_IVOR34 (0x212)
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#define SPR_IBAT1L (0x213)
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#define SPR_BOOKE_IVOR35 (0x213)
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#define SPR_IBAT2U (0x214)
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#define SPR_BOOKE_IVOR36 (0x214)
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#define SPR_IBAT2L (0x215)
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#define SPR_E500_L1CFG0 (0x215)
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#define SPR_BOOKE_IVOR37 (0x215)
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#define SPR_IBAT3U (0x216)
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#define SPR_E500_L1CFG1 (0x216)
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#define SPR_IBAT3L (0x217)
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#define SPR_DBAT0U (0x218)
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#define SPR_DBAT0L (0x219)
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#define SPR_DBAT1U (0x21A)
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#define SPR_DBAT1L (0x21B)
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#define SPR_DBAT2U (0x21C)
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#define SPR_DBAT2L (0x21D)
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#define SPR_DBAT3U (0x21E)
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#define SPR_DBAT3L (0x21F)
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#define SPR_IBAT4U (0x230)
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#define SPR_IBAT4L (0x231)
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#define SPR_IBAT5U (0x232)
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#define SPR_IBAT5L (0x233)
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#define SPR_IBAT6U (0x234)
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#define SPR_IBAT6L (0x235)
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#define SPR_IBAT7U (0x236)
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#define SPR_IBAT7L (0x237)
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#define SPR_DBAT4U (0x238)
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#define SPR_DBAT4L (0x239)
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#define SPR_DBAT5U (0x23A)
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#define SPR_BOOKE_MCSRR0 (0x23A)
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#define SPR_DBAT5L (0x23B)
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#define SPR_BOOKE_MCSRR1 (0x23B)
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#define SPR_DBAT6U (0x23C)
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#define SPR_BOOKE_MCSR (0x23C)
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#define SPR_DBAT6L (0x23D)
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#define SPR_E500_MCAR (0x23D)
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#define SPR_DBAT7U (0x23E)
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#define SPR_BOOKE_DSRR0 (0x23E)
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#define SPR_DBAT7L (0x23F)
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#define SPR_BOOKE_DSRR1 (0x23F)
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#define SPR_BOOKE_SPRG8 (0x25C)
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#define SPR_BOOKE_SPRG9 (0x25D)
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#define SPR_BOOKE_MAS0 (0x270)
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#define SPR_BOOKE_MAS1 (0x271)
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#define SPR_BOOKE_MAS2 (0x272)
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#define SPR_BOOKE_MAS3 (0x273)
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#define SPR_BOOKE_MAS4 (0x274)
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#define SPR_BOOKE_MAS6 (0x276)
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#define SPR_BOOKE_PID1 (0x279)
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#define SPR_BOOKE_PID2 (0x27A)
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#define SPR_BOOKE_TLB0CFG (0x2B0)
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#define SPR_BOOKE_TLB1CFG (0x2B1)
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#define SPR_BOOKE_TLB2CFG (0x2B2)
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#define SPR_BOOKE_TLB3CFG (0x2B3)
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#define SPR_BOOKE_EPR (0x2BE)
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#define SPR_PERF0 (0x300)
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#define SPR_PERF1 (0x301)
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#define SPR_PERF2 (0x302)
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#define SPR_PERF3 (0x303)
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#define SPR_PERF4 (0x304)
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#define SPR_PERF5 (0x305)
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#define SPR_PERF6 (0x306)
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#define SPR_PERF7 (0x307)
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#define SPR_PERF8 (0x308)
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#define SPR_PERF9 (0x309)
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#define SPR_PERFA (0x30A)
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#define SPR_PERFB (0x30B)
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#define SPR_PERFC (0x30C)
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#define SPR_PERFD (0x30D)
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#define SPR_PERFE (0x30E)
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#define SPR_PERFF (0x30F)
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#define SPR_UPERF0 (0x310)
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#define SPR_UPERF1 (0x311)
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#define SPR_UPERF2 (0x312)
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#define SPR_UPERF3 (0x313)
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#define SPR_UPERF4 (0x314)
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#define SPR_UPERF5 (0x315)
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#define SPR_UPERF6 (0x316)
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#define SPR_UPERF7 (0x317)
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#define SPR_UPERF8 (0x318)
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#define SPR_UPERF9 (0x319)
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#define SPR_UPERFA (0x31A)
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#define SPR_UPERFB (0x31B)
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#define SPR_UPERFC (0x31C)
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#define SPR_UPERFD (0x31D)
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#define SPR_UPERFE (0x31E)
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#define SPR_UPERFF (0x31F)
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#define SPR_440_INV0 (0x370)
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#define SPR_440_INV1 (0x371)
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#define SPR_440_INV2 (0x372)
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#define SPR_440_INV3 (0x373)
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#define SPR_440_ITV0 (0x374)
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#define SPR_440_ITV1 (0x375)
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#define SPR_440_ITV2 (0x376)
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#define SPR_440_ITV3 (0x377)
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#define SPR_440_CCR1 (0x378)
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#define SPR_DCRIPR (0x37B)
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#define SPR_PPR (0x380)
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#define SPR_440_DNV0 (0x390)
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#define SPR_440_DNV1 (0x391)
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#define SPR_440_DNV2 (0x392)
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#define SPR_440_DNV3 (0x393)
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#define SPR_440_DTV0 (0x394)
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#define SPR_440_DTV1 (0x395)
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#define SPR_440_DTV2 (0x396)
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#define SPR_440_DTV3 (0x397)
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#define SPR_440_DVLIM (0x398)
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#define SPR_440_IVLIM (0x399)
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#define SPR_440_RSTCFG (0x39B)
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#define SPR_BOOKE_DCDBTRL (0x39C)
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#define SPR_BOOKE_DCDBTRH (0x39D)
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#define SPR_BOOKE_ICDBTRL (0x39E)
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#define SPR_BOOKE_ICDBTRH (0x39F)
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#define SPR_UMMCR2 (0x3A0)
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#define SPR_UPMC5 (0x3A1)
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#define SPR_UPMC6 (0x3A2)
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#define SPR_UBAMR (0x3A7)
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#define SPR_UMMCR0 (0x3A8)
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#define SPR_UPMC1 (0x3A9)
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#define SPR_UPMC2 (0x3AA)
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#define SPR_USIAR (0x3AB)
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#define SPR_UMMCR1 (0x3AC)
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#define SPR_UPMC3 (0x3AD)
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#define SPR_UPMC4 (0x3AE)
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#define SPR_USDA (0x3AF)
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#define SPR_40x_ZPR (0x3B0)
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#define SPR_BOOKE_MAS7 (0x3B0)
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#define SPR_620_PMR0 (0x3B0)
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#define SPR_MMCR2 (0x3B0)
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#define SPR_PMC5 (0x3B1)
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#define SPR_40x_PID (0x3B1)
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#define SPR_620_PMR1 (0x3B1)
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#define SPR_PMC6 (0x3B2)
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#define SPR_440_MMUCR (0x3B2)
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#define SPR_620_PMR2 (0x3B2)
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#define SPR_4xx_CCR0 (0x3B3)
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#define SPR_BOOKE_EPLC (0x3B3)
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#define SPR_620_PMR3 (0x3B3)
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#define SPR_405_IAC3 (0x3B4)
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#define SPR_BOOKE_EPSC (0x3B4)
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#define SPR_620_PMR4 (0x3B4)
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#define SPR_405_IAC4 (0x3B5)
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#define SPR_620_PMR5 (0x3B5)
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#define SPR_405_DVC1 (0x3B6)
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#define SPR_620_PMR6 (0x3B6)
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#define SPR_405_DVC2 (0x3B7)
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#define SPR_620_PMR7 (0x3B7)
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#define SPR_BAMR (0x3B7)
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#define SPR_MMCR0 (0x3B8)
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#define SPR_620_PMR8 (0x3B8)
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#define SPR_PMC1 (0x3B9)
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#define SPR_40x_SGR (0x3B9)
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#define SPR_620_PMR9 (0x3B9)
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#define SPR_PMC2 (0x3BA)
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#define SPR_40x_DCWR (0x3BA)
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#define SPR_620_PMRA (0x3BA)
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#define SPR_SIAR (0x3BB)
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#define SPR_405_SLER (0x3BB)
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#define SPR_620_PMRB (0x3BB)
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#define SPR_MMCR1 (0x3BC)
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#define SPR_405_SU0R (0x3BC)
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#define SPR_620_PMRC (0x3BC)
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#define SPR_401_SKR (0x3BC)
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#define SPR_PMC3 (0x3BD)
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#define SPR_405_DBCR1 (0x3BD)
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#define SPR_620_PMRD (0x3BD)
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#define SPR_PMC4 (0x3BE)
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#define SPR_620_PMRE (0x3BE)
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#define SPR_SDA (0x3BF)
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#define SPR_620_PMRF (0x3BF)
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#define SPR_403_VTBL (0x3CC)
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#define SPR_403_VTBU (0x3CD)
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#define SPR_DMISS (0x3D0)
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#define SPR_DCMP (0x3D1)
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#define SPR_HASH1 (0x3D2)
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#define SPR_HASH2 (0x3D3)
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#define SPR_BOOKE_ICDBDR (0x3D3)
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#define SPR_TLBMISS (0x3D4)
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#define SPR_IMISS (0x3D4)
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#define SPR_40x_ESR (0x3D4)
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#define SPR_PTEHI (0x3D5)
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#define SPR_ICMP (0x3D5)
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#define SPR_40x_DEAR (0x3D5)
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#define SPR_PTELO (0x3D6)
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#define SPR_RPA (0x3D6)
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#define SPR_40x_EVPR (0x3D6)
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#define SPR_L3PM (0x3D7)
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#define SPR_403_CDBCR (0x3D7)
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#define SPR_L3OHCR (0x3D8)
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#define SPR_TCR (0x3D8)
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#define SPR_40x_TSR (0x3D8)
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#define SPR_IBR (0x3DA)
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#define SPR_40x_TCR (0x3DA)
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#define SPR_ESASRR (0x3DB)
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#define SPR_40x_PIT (0x3DB)
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#define SPR_403_TBL (0x3DC)
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#define SPR_403_TBU (0x3DD)
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#define SPR_SEBR (0x3DE)
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#define SPR_40x_SRR2 (0x3DE)
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#define SPR_SER (0x3DF)
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#define SPR_40x_SRR3 (0x3DF)
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#define SPR_L3ITCR0 (0x3E8)
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#define SPR_L3ITCR1 (0x3E9)
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#define SPR_L3ITCR2 (0x3EA)
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#define SPR_L3ITCR3 (0x3EB)
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#define SPR_HID0 (0x3F0)
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#define SPR_40x_DBSR (0x3F0)
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#define SPR_HID1 (0x3F1)
|
||||
#define SPR_IABR (0x3F2)
|
||||
#define SPR_40x_DBCR0 (0x3F2)
|
||||
#define SPR_601_HID2 (0x3F2)
|
||||
#define SPR_E500_L1CSR0 (0x3F2)
|
||||
#define SPR_ICTRL (0x3F3)
|
||||
#define SPR_HID2 (0x3F3)
|
||||
#define SPR_E500_L1CSR1 (0x3F3)
|
||||
#define SPR_440_DBDR (0x3F3)
|
||||
#define SPR_LDSTDB (0x3F4)
|
||||
#define SPR_40x_IAC1 (0x3F4)
|
||||
#define SPR_MMUCSR0 (0x3F4)
|
||||
#define SPR_DABR (0x3F5)
|
||||
#define SPR_MQ (0x000)
|
||||
#define SPR_XER (0x001)
|
||||
#define SPR_601_VRTCU (0x004)
|
||||
#define SPR_601_VRTCL (0x005)
|
||||
#define SPR_601_UDECR (0x006)
|
||||
#define SPR_LR (0x008)
|
||||
#define SPR_CTR (0x009)
|
||||
#define SPR_DSISR (0x012)
|
||||
#define SPR_DAR (0x013) /* DAE for PowerPC 601 */
|
||||
#define SPR_601_RTCU (0x014)
|
||||
#define SPR_601_RTCL (0x015)
|
||||
#define SPR_DECR (0x016)
|
||||
#define SPR_SDR1 (0x019)
|
||||
#define SPR_SRR0 (0x01A)
|
||||
#define SPR_SRR1 (0x01B)
|
||||
#define SPR_AMR (0x01D)
|
||||
#define SPR_BOOKE_PID (0x030)
|
||||
#define SPR_BOOKE_DECAR (0x036)
|
||||
#define SPR_BOOKE_CSRR0 (0x03A)
|
||||
#define SPR_BOOKE_CSRR1 (0x03B)
|
||||
#define SPR_BOOKE_DEAR (0x03D)
|
||||
#define SPR_BOOKE_ESR (0x03E)
|
||||
#define SPR_BOOKE_IVPR (0x03F)
|
||||
#define SPR_MPC_EIE (0x050)
|
||||
#define SPR_MPC_EID (0x051)
|
||||
#define SPR_MPC_NRI (0x052)
|
||||
#define SPR_CTRL (0x088)
|
||||
#define SPR_MPC_CMPA (0x090)
|
||||
#define SPR_MPC_CMPB (0x091)
|
||||
#define SPR_MPC_CMPC (0x092)
|
||||
#define SPR_MPC_CMPD (0x093)
|
||||
#define SPR_MPC_ECR (0x094)
|
||||
#define SPR_MPC_DER (0x095)
|
||||
#define SPR_MPC_COUNTA (0x096)
|
||||
#define SPR_MPC_COUNTB (0x097)
|
||||
#define SPR_UCTRL (0x098)
|
||||
#define SPR_MPC_CMPE (0x098)
|
||||
#define SPR_MPC_CMPF (0x099)
|
||||
#define SPR_MPC_CMPG (0x09A)
|
||||
#define SPR_MPC_CMPH (0x09B)
|
||||
#define SPR_MPC_LCTRL1 (0x09C)
|
||||
#define SPR_MPC_LCTRL2 (0x09D)
|
||||
#define SPR_MPC_ICTRL (0x09E)
|
||||
#define SPR_MPC_BAR (0x09F)
|
||||
#define SPR_VRSAVE (0x100)
|
||||
#define SPR_USPRG0 (0x100)
|
||||
#define SPR_USPRG1 (0x101)
|
||||
#define SPR_USPRG2 (0x102)
|
||||
#define SPR_USPRG3 (0x103)
|
||||
#define SPR_USPRG4 (0x104)
|
||||
#define SPR_USPRG5 (0x105)
|
||||
#define SPR_USPRG6 (0x106)
|
||||
#define SPR_USPRG7 (0x107)
|
||||
#define SPR_VTBL (0x10C)
|
||||
#define SPR_VTBU (0x10D)
|
||||
#define SPR_SPRG0 (0x110)
|
||||
#define SPR_SPRG1 (0x111)
|
||||
#define SPR_SPRG2 (0x112)
|
||||
#define SPR_SPRG3 (0x113)
|
||||
#define SPR_SPRG4 (0x114)
|
||||
#define SPR_SCOMC (0x114)
|
||||
#define SPR_SPRG5 (0x115)
|
||||
#define SPR_SCOMD (0x115)
|
||||
#define SPR_SPRG6 (0x116)
|
||||
#define SPR_SPRG7 (0x117)
|
||||
#define SPR_ASR (0x118)
|
||||
#define SPR_EAR (0x11A)
|
||||
#define SPR_TBL (0x11C)
|
||||
#define SPR_TBU (0x11D)
|
||||
#define SPR_TBU40 (0x11E)
|
||||
#define SPR_SVR (0x11E)
|
||||
#define SPR_BOOKE_PIR (0x11E)
|
||||
#define SPR_PVR (0x11F)
|
||||
#define SPR_HSPRG0 (0x130)
|
||||
#define SPR_BOOKE_DBSR (0x130)
|
||||
#define SPR_HSPRG1 (0x131)
|
||||
#define SPR_HDSISR (0x132)
|
||||
#define SPR_HDAR (0x133)
|
||||
#define SPR_BOOKE_DBCR0 (0x134)
|
||||
#define SPR_IBCR (0x135)
|
||||
#define SPR_PURR (0x135)
|
||||
#define SPR_BOOKE_DBCR1 (0x135)
|
||||
#define SPR_DBCR (0x136)
|
||||
#define SPR_HDEC (0x136)
|
||||
#define SPR_BOOKE_DBCR2 (0x136)
|
||||
#define SPR_HIOR (0x137)
|
||||
#define SPR_MBAR (0x137)
|
||||
#define SPR_RMOR (0x138)
|
||||
#define SPR_BOOKE_IAC1 (0x138)
|
||||
#define SPR_HRMOR (0x139)
|
||||
#define SPR_BOOKE_IAC2 (0x139)
|
||||
#define SPR_HSRR0 (0x13A)
|
||||
#define SPR_BOOKE_IAC3 (0x13A)
|
||||
#define SPR_HSRR1 (0x13B)
|
||||
#define SPR_BOOKE_IAC4 (0x13B)
|
||||
#define SPR_LPCR (0x13C)
|
||||
#define SPR_BOOKE_DAC1 (0x13C)
|
||||
#define SPR_LPIDR (0x13D)
|
||||
#define SPR_DABR2 (0x13D)
|
||||
#define SPR_BOOKE_DAC2 (0x13D)
|
||||
#define SPR_BOOKE_DVC1 (0x13E)
|
||||
#define SPR_BOOKE_DVC2 (0x13F)
|
||||
#define SPR_BOOKE_TSR (0x150)
|
||||
#define SPR_BOOKE_TCR (0x154)
|
||||
#define SPR_BOOKE_IVOR0 (0x190)
|
||||
#define SPR_BOOKE_IVOR1 (0x191)
|
||||
#define SPR_BOOKE_IVOR2 (0x192)
|
||||
#define SPR_BOOKE_IVOR3 (0x193)
|
||||
#define SPR_BOOKE_IVOR4 (0x194)
|
||||
#define SPR_BOOKE_IVOR5 (0x195)
|
||||
#define SPR_BOOKE_IVOR6 (0x196)
|
||||
#define SPR_BOOKE_IVOR7 (0x197)
|
||||
#define SPR_BOOKE_IVOR8 (0x198)
|
||||
#define SPR_BOOKE_IVOR9 (0x199)
|
||||
#define SPR_BOOKE_IVOR10 (0x19A)
|
||||
#define SPR_BOOKE_IVOR11 (0x19B)
|
||||
#define SPR_BOOKE_IVOR12 (0x19C)
|
||||
#define SPR_BOOKE_IVOR13 (0x19D)
|
||||
#define SPR_BOOKE_IVOR14 (0x19E)
|
||||
#define SPR_BOOKE_IVOR15 (0x19F)
|
||||
#define SPR_BOOKE_SPEFSCR (0x200)
|
||||
#define SPR_Exxx_BBEAR (0x201)
|
||||
#define SPR_Exxx_BBTAR (0x202)
|
||||
#define SPR_Exxx_L1CFG0 (0x203)
|
||||
#define SPR_Exxx_NPIDR (0x205)
|
||||
#define SPR_ATBL (0x20E)
|
||||
#define SPR_ATBU (0x20F)
|
||||
#define SPR_IBAT0U (0x210)
|
||||
#define SPR_BOOKE_IVOR32 (0x210)
|
||||
#define SPR_RCPU_MI_GRA (0x210)
|
||||
#define SPR_IBAT0L (0x211)
|
||||
#define SPR_BOOKE_IVOR33 (0x211)
|
||||
#define SPR_IBAT1U (0x212)
|
||||
#define SPR_BOOKE_IVOR34 (0x212)
|
||||
#define SPR_IBAT1L (0x213)
|
||||
#define SPR_BOOKE_IVOR35 (0x213)
|
||||
#define SPR_IBAT2U (0x214)
|
||||
#define SPR_BOOKE_IVOR36 (0x214)
|
||||
#define SPR_IBAT2L (0x215)
|
||||
#define SPR_BOOKE_IVOR37 (0x215)
|
||||
#define SPR_IBAT3U (0x216)
|
||||
#define SPR_IBAT3L (0x217)
|
||||
#define SPR_DBAT0U (0x218)
|
||||
#define SPR_RCPU_L2U_GRA (0x218)
|
||||
#define SPR_DBAT0L (0x219)
|
||||
#define SPR_DBAT1U (0x21A)
|
||||
#define SPR_DBAT1L (0x21B)
|
||||
#define SPR_DBAT2U (0x21C)
|
||||
#define SPR_DBAT2L (0x21D)
|
||||
#define SPR_DBAT3U (0x21E)
|
||||
#define SPR_DBAT3L (0x21F)
|
||||
#define SPR_IBAT4U (0x230)
|
||||
#define SPR_RPCU_BBCMCR (0x230)
|
||||
#define SPR_MPC_IC_CST (0x230)
|
||||
#define SPR_Exxx_CTXCR (0x230)
|
||||
#define SPR_IBAT4L (0x231)
|
||||
#define SPR_MPC_IC_ADR (0x231)
|
||||
#define SPR_Exxx_DBCR3 (0x231)
|
||||
#define SPR_IBAT5U (0x232)
|
||||
#define SPR_MPC_IC_DAT (0x232)
|
||||
#define SPR_Exxx_DBCNT (0x232)
|
||||
#define SPR_IBAT5L (0x233)
|
||||
#define SPR_IBAT6U (0x234)
|
||||
#define SPR_IBAT6L (0x235)
|
||||
#define SPR_IBAT7U (0x236)
|
||||
#define SPR_IBAT7L (0x237)
|
||||
#define SPR_DBAT4U (0x238)
|
||||
#define SPR_RCPU_L2U_MCR (0x238)
|
||||
#define SPR_MPC_DC_CST (0x238)
|
||||
#define SPR_Exxx_ALTCTXCR (0x238)
|
||||
#define SPR_DBAT4L (0x239)
|
||||
#define SPR_MPC_DC_ADR (0x239)
|
||||
#define SPR_DBAT5U (0x23A)
|
||||
#define SPR_BOOKE_MCSRR0 (0x23A)
|
||||
#define SPR_MPC_DC_DAT (0x23A)
|
||||
#define SPR_DBAT5L (0x23B)
|
||||
#define SPR_BOOKE_MCSRR1 (0x23B)
|
||||
#define SPR_DBAT6U (0x23C)
|
||||
#define SPR_BOOKE_MCSR (0x23C)
|
||||
#define SPR_DBAT6L (0x23D)
|
||||
#define SPR_Exxx_MCAR (0x23D)
|
||||
#define SPR_DBAT7U (0x23E)
|
||||
#define SPR_BOOKE_DSRR0 (0x23E)
|
||||
#define SPR_DBAT7L (0x23F)
|
||||
#define SPR_BOOKE_DSRR1 (0x23F)
|
||||
#define SPR_BOOKE_SPRG8 (0x25C)
|
||||
#define SPR_BOOKE_SPRG9 (0x25D)
|
||||
#define SPR_BOOKE_MAS0 (0x270)
|
||||
#define SPR_BOOKE_MAS1 (0x271)
|
||||
#define SPR_BOOKE_MAS2 (0x272)
|
||||
#define SPR_BOOKE_MAS3 (0x273)
|
||||
#define SPR_BOOKE_MAS4 (0x274)
|
||||
#define SPR_BOOKE_MAS5 (0x275)
|
||||
#define SPR_BOOKE_MAS6 (0x276)
|
||||
#define SPR_BOOKE_PID1 (0x279)
|
||||
#define SPR_BOOKE_PID2 (0x27A)
|
||||
#define SPR_MPC_DPDR (0x280)
|
||||
#define SPR_MPC_IMMR (0x288)
|
||||
#define SPR_BOOKE_TLB0CFG (0x2B0)
|
||||
#define SPR_BOOKE_TLB1CFG (0x2B1)
|
||||
#define SPR_BOOKE_TLB2CFG (0x2B2)
|
||||
#define SPR_BOOKE_TLB3CFG (0x2B3)
|
||||
#define SPR_BOOKE_EPR (0x2BE)
|
||||
#define SPR_PERF0 (0x300)
|
||||
#define SPR_RCPU_MI_RBA0 (0x300)
|
||||
#define SPR_MPC_MI_CTR (0x300)
|
||||
#define SPR_PERF1 (0x301)
|
||||
#define SPR_RCPU_MI_RBA1 (0x301)
|
||||
#define SPR_PERF2 (0x302)
|
||||
#define SPR_RCPU_MI_RBA2 (0x302)
|
||||
#define SPR_MPC_MI_AP (0x302)
|
||||
#define SPR_PERF3 (0x303)
|
||||
#define SPR_RCPU_MI_RBA3 (0x303)
|
||||
#define SPR_MPC_MI_EPN (0x303)
|
||||
#define SPR_PERF4 (0x304)
|
||||
#define SPR_PERF5 (0x305)
|
||||
#define SPR_MPC_MI_TWC (0x305)
|
||||
#define SPR_PERF6 (0x306)
|
||||
#define SPR_MPC_MI_RPN (0x306)
|
||||
#define SPR_PERF7 (0x307)
|
||||
#define SPR_PERF8 (0x308)
|
||||
#define SPR_RCPU_L2U_RBA0 (0x308)
|
||||
#define SPR_MPC_MD_CTR (0x308)
|
||||
#define SPR_PERF9 (0x309)
|
||||
#define SPR_RCPU_L2U_RBA1 (0x309)
|
||||
#define SPR_MPC_MD_CASID (0x309)
|
||||
#define SPR_PERFA (0x30A)
|
||||
#define SPR_RCPU_L2U_RBA2 (0x30A)
|
||||
#define SPR_MPC_MD_AP (0x30A)
|
||||
#define SPR_PERFB (0x30B)
|
||||
#define SPR_RCPU_L2U_RBA3 (0x30B)
|
||||
#define SPR_MPC_MD_EPN (0x30B)
|
||||
#define SPR_PERFC (0x30C)
|
||||
#define SPR_MPC_MD_TWB (0x30C)
|
||||
#define SPR_PERFD (0x30D)
|
||||
#define SPR_MPC_MD_TWC (0x30D)
|
||||
#define SPR_PERFE (0x30E)
|
||||
#define SPR_MPC_MD_RPN (0x30E)
|
||||
#define SPR_PERFF (0x30F)
|
||||
#define SPR_MPC_MD_TW (0x30F)
|
||||
#define SPR_UPERF0 (0x310)
|
||||
#define SPR_UPERF1 (0x311)
|
||||
#define SPR_UPERF2 (0x312)
|
||||
#define SPR_UPERF3 (0x313)
|
||||
#define SPR_UPERF4 (0x314)
|
||||
#define SPR_UPERF5 (0x315)
|
||||
#define SPR_UPERF6 (0x316)
|
||||
#define SPR_UPERF7 (0x317)
|
||||
#define SPR_UPERF8 (0x318)
|
||||
#define SPR_UPERF9 (0x319)
|
||||
#define SPR_UPERFA (0x31A)
|
||||
#define SPR_UPERFB (0x31B)
|
||||
#define SPR_UPERFC (0x31C)
|
||||
#define SPR_UPERFD (0x31D)
|
||||
#define SPR_UPERFE (0x31E)
|
||||
#define SPR_UPERFF (0x31F)
|
||||
#define SPR_RCPU_MI_RA0 (0x320)
|
||||
#define SPR_MPC_MI_DBCAM (0x320)
|
||||
#define SPR_RCPU_MI_RA1 (0x321)
|
||||
#define SPR_MPC_MI_DBRAM0 (0x321)
|
||||
#define SPR_RCPU_MI_RA2 (0x322)
|
||||
#define SPR_MPC_MI_DBRAM1 (0x322)
|
||||
#define SPR_RCPU_MI_RA3 (0x323)
|
||||
#define SPR_RCPU_L2U_RA0 (0x328)
|
||||
#define SPR_MPC_MD_DBCAM (0x328)
|
||||
#define SPR_RCPU_L2U_RA1 (0x329)
|
||||
#define SPR_MPC_MD_DBRAM0 (0x329)
|
||||
#define SPR_RCPU_L2U_RA2 (0x32A)
|
||||
#define SPR_MPC_MD_DBRAM1 (0x32A)
|
||||
#define SPR_RCPU_L2U_RA3 (0x32B)
|
||||
#define SPR_440_INV0 (0x370)
|
||||
#define SPR_440_INV1 (0x371)
|
||||
#define SPR_440_INV2 (0x372)
|
||||
#define SPR_440_INV3 (0x373)
|
||||
#define SPR_440_ITV0 (0x374)
|
||||
#define SPR_440_ITV1 (0x375)
|
||||
#define SPR_440_ITV2 (0x376)
|
||||
#define SPR_440_ITV3 (0x377)
|
||||
#define SPR_440_CCR1 (0x378)
|
||||
#define SPR_DCRIPR (0x37B)
|
||||
#define SPR_PPR (0x380)
|
||||
#define SPR_440_DNV0 (0x390)
|
||||
#define SPR_440_DNV1 (0x391)
|
||||
#define SPR_440_DNV2 (0x392)
|
||||
#define SPR_440_DNV3 (0x393)
|
||||
#define SPR_440_DTV0 (0x394)
|
||||
#define SPR_440_DTV1 (0x395)
|
||||
#define SPR_440_DTV2 (0x396)
|
||||
#define SPR_440_DTV3 (0x397)
|
||||
#define SPR_440_DVLIM (0x398)
|
||||
#define SPR_440_IVLIM (0x399)
|
||||
#define SPR_440_RSTCFG (0x39B)
|
||||
#define SPR_BOOKE_DCDBTRL (0x39C)
|
||||
#define SPR_BOOKE_DCDBTRH (0x39D)
|
||||
#define SPR_BOOKE_ICDBTRL (0x39E)
|
||||
#define SPR_BOOKE_ICDBTRH (0x39F)
|
||||
#define SPR_UMMCR2 (0x3A0)
|
||||
#define SPR_UPMC5 (0x3A1)
|
||||
#define SPR_UPMC6 (0x3A2)
|
||||
#define SPR_UBAMR (0x3A7)
|
||||
#define SPR_UMMCR0 (0x3A8)
|
||||
#define SPR_UPMC1 (0x3A9)
|
||||
#define SPR_UPMC2 (0x3AA)
|
||||
#define SPR_USIAR (0x3AB)
|
||||
#define SPR_UMMCR1 (0x3AC)
|
||||
#define SPR_UPMC3 (0x3AD)
|
||||
#define SPR_UPMC4 (0x3AE)
|
||||
#define SPR_USDA (0x3AF)
|
||||
#define SPR_40x_ZPR (0x3B0)
|
||||
#define SPR_BOOKE_MAS7 (0x3B0)
|
||||
#define SPR_620_PMR0 (0x3B0)
|
||||
#define SPR_MMCR2 (0x3B0)
|
||||
#define SPR_PMC5 (0x3B1)
|
||||
#define SPR_40x_PID (0x3B1)
|
||||
#define SPR_620_PMR1 (0x3B1)
|
||||
#define SPR_PMC6 (0x3B2)
|
||||
#define SPR_440_MMUCR (0x3B2)
|
||||
#define SPR_620_PMR2 (0x3B2)
|
||||
#define SPR_4xx_CCR0 (0x3B3)
|
||||
#define SPR_BOOKE_EPLC (0x3B3)
|
||||
#define SPR_620_PMR3 (0x3B3)
|
||||
#define SPR_405_IAC3 (0x3B4)
|
||||
#define SPR_BOOKE_EPSC (0x3B4)
|
||||
#define SPR_620_PMR4 (0x3B4)
|
||||
#define SPR_405_IAC4 (0x3B5)
|
||||
#define SPR_620_PMR5 (0x3B5)
|
||||
#define SPR_405_DVC1 (0x3B6)
|
||||
#define SPR_620_PMR6 (0x3B6)
|
||||
#define SPR_405_DVC2 (0x3B7)
|
||||
#define SPR_620_PMR7 (0x3B7)
|
||||
#define SPR_BAMR (0x3B7)
|
||||
#define SPR_MMCR0 (0x3B8)
|
||||
#define SPR_620_PMR8 (0x3B8)
|
||||
#define SPR_PMC1 (0x3B9)
|
||||
#define SPR_40x_SGR (0x3B9)
|
||||
#define SPR_620_PMR9 (0x3B9)
|
||||
#define SPR_PMC2 (0x3BA)
|
||||
#define SPR_40x_DCWR (0x3BA)
|
||||
#define SPR_620_PMRA (0x3BA)
|
||||
#define SPR_SIAR (0x3BB)
|
||||
#define SPR_405_SLER (0x3BB)
|
||||
#define SPR_620_PMRB (0x3BB)
|
||||
#define SPR_MMCR1 (0x3BC)
|
||||
#define SPR_405_SU0R (0x3BC)
|
||||
#define SPR_620_PMRC (0x3BC)
|
||||
#define SPR_401_SKR (0x3BC)
|
||||
#define SPR_PMC3 (0x3BD)
|
||||
#define SPR_405_DBCR1 (0x3BD)
|
||||
#define SPR_620_PMRD (0x3BD)
|
||||
#define SPR_PMC4 (0x3BE)
|
||||
#define SPR_620_PMRE (0x3BE)
|
||||
#define SPR_SDA (0x3BF)
|
||||
#define SPR_620_PMRF (0x3BF)
|
||||
#define SPR_403_VTBL (0x3CC)
|
||||
#define SPR_403_VTBU (0x3CD)
|
||||
#define SPR_DMISS (0x3D0)
|
||||
#define SPR_DCMP (0x3D1)
|
||||
#define SPR_HASH1 (0x3D2)
|
||||
#define SPR_HASH2 (0x3D3)
|
||||
#define SPR_BOOKE_ICDBDR (0x3D3)
|
||||
#define SPR_TLBMISS (0x3D4)
|
||||
#define SPR_IMISS (0x3D4)
|
||||
#define SPR_40x_ESR (0x3D4)
|
||||
#define SPR_PTEHI (0x3D5)
|
||||
#define SPR_ICMP (0x3D5)
|
||||
#define SPR_40x_DEAR (0x3D5)
|
||||
#define SPR_PTELO (0x3D6)
|
||||
#define SPR_RPA (0x3D6)
|
||||
#define SPR_40x_EVPR (0x3D6)
|
||||
#define SPR_L3PM (0x3D7)
|
||||
#define SPR_403_CDBCR (0x3D7)
|
||||
#define SPR_L3OHCR (0x3D8)
|
||||
#define SPR_TCR (0x3D8)
|
||||
#define SPR_40x_TSR (0x3D8)
|
||||
#define SPR_IBR (0x3DA)
|
||||
#define SPR_40x_TCR (0x3DA)
|
||||
#define SPR_ESASRR (0x3DB)
|
||||
#define SPR_40x_PIT (0x3DB)
|
||||
#define SPR_403_TBL (0x3DC)
|
||||
#define SPR_403_TBU (0x3DD)
|
||||
#define SPR_SEBR (0x3DE)
|
||||
#define SPR_40x_SRR2 (0x3DE)
|
||||
#define SPR_SER (0x3DF)
|
||||
#define SPR_40x_SRR3 (0x3DF)
|
||||
#define SPR_L3ITCR0 (0x3E8)
|
||||
#define SPR_L3ITCR1 (0x3E9)
|
||||
#define SPR_L3ITCR2 (0x3EA)
|
||||
#define SPR_L3ITCR3 (0x3EB)
|
||||
#define SPR_HID0 (0x3F0)
|
||||
#define SPR_40x_DBSR (0x3F0)
|
||||
#define SPR_HID1 (0x3F1)
|
||||
#define SPR_IABR (0x3F2)
|
||||
#define SPR_40x_DBCR0 (0x3F2)
|
||||
#define SPR_601_HID2 (0x3F2)
|
||||
#define SPR_Exxx_L1CSR0 (0x3F2)
|
||||
#define SPR_ICTRL (0x3F3)
|
||||
#define SPR_HID2 (0x3F3)
|
||||
#define SPR_Exxx_L1CSR1 (0x3F3)
|
||||
#define SPR_440_DBDR (0x3F3)
|
||||
#define SPR_LDSTDB (0x3F4)
|
||||
#define SPR_40x_IAC1 (0x3F4)
|
||||
#define SPR_MMUCSR0 (0x3F4)
|
||||
#define SPR_DABR (0x3F5)
|
||||
#define DABR_MASK (~(target_ulong)0x7)
|
||||
#define SPR_E500_BUCSR (0x3F5)
|
||||
#define SPR_40x_IAC2 (0x3F5)
|
||||
#define SPR_601_HID5 (0x3F5)
|
||||
#define SPR_40x_DAC1 (0x3F6)
|
||||
#define SPR_MSSCR0 (0x3F6)
|
||||
#define SPR_970_HID5 (0x3F6)
|
||||
#define SPR_MSSSR0 (0x3F7)
|
||||
#define SPR_DABRX (0x3F7)
|
||||
#define SPR_40x_DAC2 (0x3F7)
|
||||
#define SPR_MMUCFG (0x3F7)
|
||||
#define SPR_LDSTCR (0x3F8)
|
||||
#define SPR_L2PMCR (0x3F8)
|
||||
#define SPR_750_HID2 (0x3F8)
|
||||
#define SPR_620_HID8 (0x3F8)
|
||||
#define SPR_L2CR (0x3F9)
|
||||
#define SPR_620_HID9 (0x3F9)
|
||||
#define SPR_L3CR (0x3FA)
|
||||
#define SPR_IABR2 (0x3FA)
|
||||
#define SPR_40x_DCCR (0x3FA)
|
||||
#define SPR_ICTC (0x3FB)
|
||||
#define SPR_40x_ICCR (0x3FB)
|
||||
#define SPR_THRM1 (0x3FC)
|
||||
#define SPR_403_PBL1 (0x3FC)
|
||||
#define SPR_SP (0x3FD)
|
||||
#define SPR_THRM2 (0x3FD)
|
||||
#define SPR_403_PBU1 (0x3FD)
|
||||
#define SPR_604_HID13 (0x3FD)
|
||||
#define SPR_LT (0x3FE)
|
||||
#define SPR_THRM3 (0x3FE)
|
||||
#define SPR_FPECR (0x3FE)
|
||||
#define SPR_403_PBL2 (0x3FE)
|
||||
#define SPR_PIR (0x3FF)
|
||||
#define SPR_403_PBU2 (0x3FF)
|
||||
#define SPR_601_HID15 (0x3FF)
|
||||
#define SPR_604_HID15 (0x3FF)
|
||||
#define SPR_E500_SVR (0x3FF)
|
||||
#define SPR_Exxx_BUCSR (0x3F5)
|
||||
#define SPR_40x_IAC2 (0x3F5)
|
||||
#define SPR_601_HID5 (0x3F5)
|
||||
#define SPR_40x_DAC1 (0x3F6)
|
||||
#define SPR_MSSCR0 (0x3F6)
|
||||
#define SPR_970_HID5 (0x3F6)
|
||||
#define SPR_MSSSR0 (0x3F7)
|
||||
#define SPR_DABRX (0x3F7)
|
||||
#define SPR_40x_DAC2 (0x3F7)
|
||||
#define SPR_MMUCFG (0x3F7)
|
||||
#define SPR_LDSTCR (0x3F8)
|
||||
#define SPR_L2PMCR (0x3F8)
|
||||
#define SPR_750_HID2 (0x3F8)
|
||||
#define SPR_620_HID8 (0x3F8)
|
||||
#define SPR_Exxx_L1FINV0 (0x3F8)
|
||||
#define SPR_L2CR (0x3F9)
|
||||
#define SPR_620_HID9 (0x3F9)
|
||||
#define SPR_L3CR (0x3FA)
|
||||
#define SPR_IABR2 (0x3FA)
|
||||
#define SPR_40x_DCCR (0x3FA)
|
||||
#define SPR_ICTC (0x3FB)
|
||||
#define SPR_40x_ICCR (0x3FB)
|
||||
#define SPR_THRM1 (0x3FC)
|
||||
#define SPR_403_PBL1 (0x3FC)
|
||||
#define SPR_SP (0x3FD)
|
||||
#define SPR_THRM2 (0x3FD)
|
||||
#define SPR_403_PBU1 (0x3FD)
|
||||
#define SPR_604_HID13 (0x3FD)
|
||||
#define SPR_LT (0x3FE)
|
||||
#define SPR_THRM3 (0x3FE)
|
||||
#define SPR_RCPU_FPECR (0x3FE)
|
||||
#define SPR_403_PBL2 (0x3FE)
|
||||
#define SPR_PIR (0x3FF)
|
||||
#define SPR_403_PBU2 (0x3FF)
|
||||
#define SPR_601_HID15 (0x3FF)
|
||||
#define SPR_604_HID15 (0x3FF)
|
||||
#define SPR_E500_SVR (0x3FF)
|
||||
|
||||
/*****************************************************************************/
|
||||
/* Memory access type :
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user