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target/ppc: Implement the rest of gen_st_atomic
The store twin case was stubbed out. For now, implement it only within a serial context, forcing parallel execution to synchronize. It would be possible to implement with a cmpxchg loop, if we care, but the loose alignment requirements (simply no crossing 32-byte boundary) might send us back to the serial context anyway. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -3254,7 +3254,31 @@ static void gen_st_atomic(DisasContext *ctx, TCGMemOp memop)
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tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
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break;
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case 24: /* Store twin */
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gen_invalid(ctx);
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if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
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/* Restart with exclusive lock. */
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gen_helper_exit_atomic(cpu_env);
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ctx->base.is_jmp = DISAS_NORETURN;
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} else {
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TCGv t = tcg_temp_new();
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TCGv t2 = tcg_temp_new();
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TCGv s = tcg_temp_new();
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TCGv s2 = tcg_temp_new();
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TCGv ea_plus_s = tcg_temp_new();
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tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
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tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop));
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tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop);
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tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t);
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tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2);
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tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop);
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tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop);
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tcg_temp_free(ea_plus_s);
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tcg_temp_free(s2);
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tcg_temp_free(s);
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tcg_temp_free(t2);
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tcg_temp_free(t);
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}
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break;
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default:
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/* invoke data storage error handler */
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