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target/ppc: Implement the rest of gen_st_atomic

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The store twin case was stubbed out.  For now, implement it only within
a serial context, forcing parallel execution to synchronize.  It would
be possible to implement with a cmpxchg loop, if we care, but the loose
alignment requirements (simply no crossing 32-byte boundary) might send
us back to the serial context anyway.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Richard Henderson 2018-06-26 09:19:21 -07:00 committed by David Gibson
parent 20923c1d02
commit 7fbc2b20d2
1 changed files with 25 additions and 1 deletions
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26
target/ppc/translate.c
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@ -3254,7 +3254,31 @@ static void gen_st_atomic(DisasContext *ctx, TCGMemOp memop)
tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
break;
case 24: /* Store twin */
gen_invalid(ctx);
if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
/* Restart with exclusive lock. */
gen_helper_exit_atomic(cpu_env);
ctx->base.is_jmp = DISAS_NORETURN;
} else {
TCGv t = tcg_temp_new();
TCGv t2 = tcg_temp_new();
TCGv s = tcg_temp_new();
TCGv s2 = tcg_temp_new();
TCGv ea_plus_s = tcg_temp_new();
tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop));
tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop);
tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t);
tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2);
tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop);
tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop);
tcg_temp_free(ea_plus_s);
tcg_temp_free(s2);
tcg_temp_free(s);
tcg_temp_free(t2);
tcg_temp_free(t);
}
break;
default:
/* invoke data storage error handler */