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vmstate: port cirrus_vga device
Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Juan Quintela
Anthony Liguori
parent
747791f11a
commit
7e72abc382
152
hw/cirrus_vga.c
152
hw/cirrus_vga.c
@ -2955,85 +2955,12 @@ static CPUWriteMemoryFunc * const cirrus_mmio_write[3] = {
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/* load/save state */
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static void cirrus_vga_save(QEMUFile *f, void *opaque)
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static int cirrus_post_load(void *opaque)
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{
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CirrusVGAState *s = opaque;
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qemu_put_be32s(f, &s->vga.latch);
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qemu_put_8s(f, &s->vga.sr_index);
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qemu_put_buffer(f, s->vga.sr, 256);
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qemu_put_8s(f, &s->vga.gr_index);
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qemu_put_8s(f, &s->cirrus_shadow_gr0);
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qemu_put_8s(f, &s->cirrus_shadow_gr1);
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qemu_put_buffer(f, s->vga.gr + 2, 254);
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qemu_put_8s(f, &s->vga.ar_index);
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qemu_put_buffer(f, s->vga.ar, 21);
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qemu_put_be32(f, s->vga.ar_flip_flop);
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qemu_put_8s(f, &s->vga.cr_index);
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qemu_put_buffer(f, s->vga.cr, 256);
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qemu_put_8s(f, &s->vga.msr);
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qemu_put_8s(f, &s->vga.fcr);
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qemu_put_8s(f, &s->vga.st00);
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qemu_put_8s(f, &s->vga.st01);
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qemu_put_8s(f, &s->vga.dac_state);
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qemu_put_8s(f, &s->vga.dac_sub_index);
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qemu_put_8s(f, &s->vga.dac_read_index);
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qemu_put_8s(f, &s->vga.dac_write_index);
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qemu_put_buffer(f, s->vga.dac_cache, 3);
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qemu_put_buffer(f, s->vga.palette, 768);
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qemu_put_be32(f, s->vga.bank_offset);
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qemu_put_8s(f, &s->cirrus_hidden_dac_lockindex);
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qemu_put_8s(f, &s->cirrus_hidden_dac_data);
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qemu_put_be32s(f, &s->hw_cursor_x);
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qemu_put_be32s(f, &s->hw_cursor_y);
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/* XXX: we do not save the bitblt state - we assume we do not save
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the state when the blitter is active */
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}
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static int cirrus_vga_load(QEMUFile *f, void *opaque, int version_id)
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{
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CirrusVGAState *s = opaque;
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if (version_id > 2)
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return -EINVAL;
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qemu_get_be32s(f, &s->vga.latch);
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qemu_get_8s(f, &s->vga.sr_index);
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qemu_get_buffer(f, s->vga.sr, 256);
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qemu_get_8s(f, &s->vga.gr_index);
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qemu_get_8s(f, &s->cirrus_shadow_gr0);
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qemu_get_8s(f, &s->cirrus_shadow_gr1);
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s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
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s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
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qemu_get_buffer(f, s->vga.gr + 2, 254);
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qemu_get_8s(f, &s->vga.ar_index);
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qemu_get_buffer(f, s->vga.ar, 21);
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s->vga.ar_flip_flop=qemu_get_be32(f);
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qemu_get_8s(f, &s->vga.cr_index);
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qemu_get_buffer(f, s->vga.cr, 256);
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qemu_get_8s(f, &s->vga.msr);
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qemu_get_8s(f, &s->vga.fcr);
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qemu_get_8s(f, &s->vga.st00);
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qemu_get_8s(f, &s->vga.st01);
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qemu_get_8s(f, &s->vga.dac_state);
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qemu_get_8s(f, &s->vga.dac_sub_index);
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qemu_get_8s(f, &s->vga.dac_read_index);
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qemu_get_8s(f, &s->vga.dac_write_index);
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qemu_get_buffer(f, s->vga.dac_cache, 3);
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qemu_get_buffer(f, s->vga.palette, 768);
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s->vga.bank_offset = qemu_get_be32(f);
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qemu_get_8s(f, &s->cirrus_hidden_dac_lockindex);
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qemu_get_8s(f, &s->cirrus_hidden_dac_data);
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qemu_get_be32s(f, &s->hw_cursor_x);
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qemu_get_be32s(f, &s->hw_cursor_y);
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cirrus_update_memory_access(s);
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/* force refresh */
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@ -3043,30 +2970,59 @@ static int cirrus_vga_load(QEMUFile *f, void *opaque, int version_id)
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return 0;
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}
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static void pci_cirrus_vga_save(QEMUFile *f, void *opaque)
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{
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PCICirrusVGAState *s = opaque;
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pci_device_save(&s->dev, f);
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cirrus_vga_save(f, &s->cirrus_vga);
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}
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static int pci_cirrus_vga_load(QEMUFile *f, void *opaque, int version_id)
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{
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PCICirrusVGAState *s = opaque;
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int ret;
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if (version_id > 2)
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return -EINVAL;
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if (version_id >= 2) {
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ret = pci_device_load(&s->dev, f);
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if (ret < 0)
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return ret;
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static const VMStateDescription vmstate_cirrus_vga = {
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.name = "cirrus_vga",
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.version_id = 2,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.post_load = cirrus_post_load,
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.fields = (VMStateField []) {
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VMSTATE_UINT32(vga.latch, CirrusVGAState),
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VMSTATE_UINT8(vga.sr_index, CirrusVGAState),
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VMSTATE_BUFFER(vga.sr, CirrusVGAState),
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VMSTATE_UINT8(vga.gr_index, CirrusVGAState),
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VMSTATE_UINT8(cirrus_shadow_gr0, CirrusVGAState),
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VMSTATE_UINT8(cirrus_shadow_gr1, CirrusVGAState),
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VMSTATE_BUFFER_START_MIDDLE(vga.gr, CirrusVGAState, 2),
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VMSTATE_UINT8(vga.ar_index, CirrusVGAState),
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VMSTATE_BUFFER(vga.ar, CirrusVGAState),
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VMSTATE_INT32(vga.ar_flip_flop, CirrusVGAState),
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VMSTATE_UINT8(vga.cr_index, CirrusVGAState),
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VMSTATE_BUFFER(vga.cr, CirrusVGAState),
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VMSTATE_UINT8(vga.msr, CirrusVGAState),
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VMSTATE_UINT8(vga.fcr, CirrusVGAState),
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VMSTATE_UINT8(vga.st00, CirrusVGAState),
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VMSTATE_UINT8(vga.st01, CirrusVGAState),
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VMSTATE_UINT8(vga.dac_state, CirrusVGAState),
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VMSTATE_UINT8(vga.dac_sub_index, CirrusVGAState),
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VMSTATE_UINT8(vga.dac_read_index, CirrusVGAState),
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VMSTATE_UINT8(vga.dac_write_index, CirrusVGAState),
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VMSTATE_BUFFER(vga.dac_cache, CirrusVGAState),
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VMSTATE_BUFFER(vga.palette, CirrusVGAState),
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VMSTATE_INT32(vga.bank_offset, CirrusVGAState),
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VMSTATE_UINT8(cirrus_hidden_dac_lockindex, CirrusVGAState),
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VMSTATE_UINT8(cirrus_hidden_dac_data, CirrusVGAState),
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VMSTATE_UINT32(hw_cursor_x, CirrusVGAState),
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VMSTATE_UINT32(hw_cursor_y, CirrusVGAState),
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/* XXX: we do not save the bitblt state - we assume we do not save
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the state when the blitter is active */
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VMSTATE_END_OF_LIST()
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}
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};
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return cirrus_vga_load(f, &s->cirrus_vga, version_id);
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}
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static const VMStateDescription vmstate_pci_cirrus_vga = {
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.name = "cirrus_vga",
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.version_id = 2,
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.minimum_version_id = 2,
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.minimum_version_id_old = 2,
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.post_load = cirrus_post_load,
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.fields = (VMStateField []) {
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VMSTATE_PCI_DEVICE(dev, PCICirrusVGAState),
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VMSTATE_STRUCT(cirrus_vga, PCICirrusVGAState, 0,
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vmstate_cirrus_vga, CirrusVGAState),
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VMSTATE_END_OF_LIST()
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}
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};
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/***************************************
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*
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@ -3203,7 +3159,7 @@ void isa_cirrus_vga_init(void)
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s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
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s->vga.screen_dump, s->vga.text_update,
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&s->vga);
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register_savevm("cirrus_vga", 0, 2, cirrus_vga_save, cirrus_vga_load, s);
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vmstate_register(0, &vmstate_cirrus_vga, s);
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/* XXX ISA-LFB support */
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}
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@ -3286,7 +3242,7 @@ static int pci_cirrus_vga_initfn(PCIDevice *dev)
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pci_register_bar((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
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PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map);
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}
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register_savevm("cirrus_vga", 0, 2, pci_cirrus_vga_save, pci_cirrus_vga_load, d);
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vmstate_register(0, &vmstate_pci_cirrus_vga, d);
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/* XXX: ROM BIOS */
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return 0;
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}
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9
hw/hw.h
9
hw/hw.h
@ -408,6 +408,15 @@ extern const VMStateInfo vmstate_info_buffer;
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+ type_check_array(uint8_t,typeof_field(_state, _field),sizeof(typeof_field(_state,_field))) \
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}
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#define VMSTATE_BUFFER_START_MIDDLE(_field, _state, start) { \
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.name = (stringify(_field)), \
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.size = sizeof(typeof_field(_state,_field)) - start, \
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.info = &vmstate_info_buffer, \
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.flags = VMS_BUFFER, \
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.offset = offsetof(_state, _field) + start \
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+ type_check_array(uint8_t,typeof_field(_state, _field),sizeof(typeof_field(_state,_field))) \
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}
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extern const VMStateDescription vmstate_pci_device;
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#define VMSTATE_PCI_DEVICE(_field, _state) { \
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