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target/arm: Fix sve predicate store, 8 <= VQ <= 15

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Brown bag time: store instead of load results in uninitialized temp.


Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1704
Reported-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230620134659.817559-1-richard.henderson@linaro.org
Fixes: e6dd5e782b ("target/arm: Use tcg_gen_qemu_{ld, st}_i128 in gen_sve_{ld, st}r")
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2023-06-20 15:46:59 +02:00 committed by Peter Maydell
parent 9fe2b4a289
commit 7c347c7333
1 changed files with 1 additions and 1 deletions
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2
target/arm/tcg/translate-sve.c
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@ -4329,7 +4329,7 @@ void gen_sve_str(DisasContext *s, TCGv_ptr base, int vofs,
/* Predicate register stores can be any multiple of 2. */ /* Predicate register stores can be any multiple of 2. */
if (len_remain >= 8) { if (len_remain >= 8) {
t0 = tcg_temp_new_i64(); t0 = tcg_temp_new_i64();
tcg_gen_st_i64(t0, base, vofs + len_align); tcg_gen_ld_i64(t0, base, vofs + len_align);
tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUQ | MO_ATOM_NONE); tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUQ | MO_ATOM_NONE);
len_remain -= 8; len_remain -= 8;
len_align += 8; len_align += 8;