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target-m68k: update move to/from ccr/sr

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Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Laurent Vivier 2016-01-17 18:55:13 +01:00
parent 20a8856eba
commit 7c0eb318bd
1 changed files with 24 additions and 33 deletions
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57
target-m68k/translate.c
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@ -1368,12 +1368,10 @@ static TCGv gen_get_ccr(DisasContext *s)
DISAS_INSN(move_from_ccr) DISAS_INSN(move_from_ccr)
{ {
TCGv reg;
TCGv ccr; TCGv ccr;
ccr = gen_get_ccr(s); ccr = gen_get_ccr(s);
reg = DREG(insn, 0); DEST_EA(env, insn, OS_WORD, ccr, NULL);
gen_partset_reg(OS_WORD, reg, ccr);
} }
DISAS_INSN(neg) DISAS_INSN(neg)
@ -1400,37 +1398,31 @@ static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
} }
} }
static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn, static void gen_set_sr(DisasContext *s, TCGv val, int ccr_only)
int ccr_only)
{ {
TCGv tmp; TCGv tmp;
TCGv reg; tmp = tcg_temp_new();
tcg_gen_andi_i32(QREG_CC_DEST, val, 0xf);
s->cc_op = CC_OP_FLAGS; tcg_gen_shri_i32(tmp, val, 4);
if ((insn & 0x38) == 0) tcg_gen_andi_i32(QREG_CC_X, tmp, 1);
{ if (!ccr_only) {
tmp = tcg_temp_new(); gen_helper_set_sr(cpu_env, val);
reg = DREG(insn, 0); }
tcg_gen_andi_i32(QREG_CC_DEST, reg, 0xf);
tcg_gen_shri_i32(tmp, reg, 4);
tcg_gen_andi_i32(QREG_CC_X, tmp, 1);
if (!ccr_only) {
gen_helper_set_sr(cpu_env, reg);
}
}
else if ((insn & 0x3f) == 0x3c)
{
uint16_t val;
val = read_im16(env, s);
gen_set_sr_im(s, val, ccr_only);
}
else
disas_undef(env, s, insn);
} }
static void gen_move_to_sr(CPUM68KState *env, DisasContext *s, uint16_t insn,
int ccr_only)
{
TCGv src;
s->cc_op = CC_OP_FLAGS;
SRC_EA(env, src, OS_WORD, 0, NULL);
gen_set_sr(s, src, ccr_only);
}
DISAS_INSN(move_to_ccr) DISAS_INSN(move_to_ccr)
{ {
gen_set_sr(env, s, insn, 1); gen_move_to_sr(env, s, insn, 1);
} }
DISAS_INSN(not) DISAS_INSN(not)
@ -1957,16 +1949,14 @@ DISAS_INSN(strldsr)
DISAS_INSN(move_from_sr) DISAS_INSN(move_from_sr)
{ {
TCGv reg;
TCGv sr; TCGv sr;
if (IS_USER(s)) { if (IS_USER(s) && !m68k_feature(env, M68K_FEATURE_M68000)) {
gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
return; return;
} }
sr = gen_get_sr(s); sr = gen_get_sr(s);
reg = DREG(insn, 0); DEST_EA(env, insn, OS_WORD, sr, NULL);
gen_partset_reg(OS_WORD, reg, sr);
} }
DISAS_INSN(move_to_sr) DISAS_INSN(move_to_sr)
@ -1975,7 +1965,7 @@ DISAS_INSN(move_to_sr)
gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
return; return;
} }
gen_set_sr(env, s, insn, 0); gen_move_to_sr(env, s, insn, 0);
gen_lookup_tb(s); gen_lookup_tb(s);
} }
@ -2872,6 +2862,7 @@ void register_m68k_insns (CPUM68KState *env)
BASE(clr, 4200, ff00); BASE(clr, 4200, ff00);
BASE(undef, 42c0, ffc0); BASE(undef, 42c0, ffc0);
INSN(move_from_ccr, 42c0, fff8, CF_ISA_A); INSN(move_from_ccr, 42c0, fff8, CF_ISA_A);
INSN(move_from_ccr, 42c0, ffc0, M68000);
INSN(neg, 4480, fff8, CF_ISA_A); INSN(neg, 4480, fff8, CF_ISA_A);
INSN(neg, 4400, ff00, M68000); INSN(neg, 4400, ff00, M68000);
INSN(undef, 44c0, ffc0, M68000); INSN(undef, 44c0, ffc0, M68000);