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target/loongarch: Implement xvssrlrn xvssrarn
This patch includes:
- XVSSRLRN.{B.H/H.W/W.D};
- XVSSRARN.{B.H/H.W/W.D};
- XVSSRLRN.{BU.H/HU.W/WU.D};
- XVSSRARN.{BU.H/HU.W/WU.D};
- XVSSRLRNI.{B.H/H.W/W.D/D.Q};
- XVSSRARNI.{B.H/H.W/W.D/D.Q};
- XVSSRLRNI.{BU.H/HU.W/WU.D/DU.Q};
- XVSSRARNI.{BU.H/HU.W/WU.D/DU.Q}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230914022645.1151356-42-gaosong@loongson.cn>
This commit is contained in:
Song Gao
parent
6256c8caeb
commit
77fca79428
@ -2166,6 +2166,36 @@ INSN_LASX(xvssrani_hu_w, vv_i)
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INSN_LASX(xvssrani_wu_d, vv_i)
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INSN_LASX(xvssrani_du_q, vv_i)
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INSN_LASX(xvssrlrn_b_h, vvv)
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INSN_LASX(xvssrlrn_h_w, vvv)
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INSN_LASX(xvssrlrn_w_d, vvv)
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INSN_LASX(xvssrarn_b_h, vvv)
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INSN_LASX(xvssrarn_h_w, vvv)
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INSN_LASX(xvssrarn_w_d, vvv)
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INSN_LASX(xvssrlrn_bu_h, vvv)
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INSN_LASX(xvssrlrn_hu_w, vvv)
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INSN_LASX(xvssrlrn_wu_d, vvv)
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INSN_LASX(xvssrarn_bu_h, vvv)
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INSN_LASX(xvssrarn_hu_w, vvv)
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INSN_LASX(xvssrarn_wu_d, vvv)
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INSN_LASX(xvssrlrni_b_h, vv_i)
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INSN_LASX(xvssrlrni_h_w, vv_i)
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INSN_LASX(xvssrlrni_w_d, vv_i)
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INSN_LASX(xvssrlrni_d_q, vv_i)
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INSN_LASX(xvssrlrni_bu_h, vv_i)
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INSN_LASX(xvssrlrni_hu_w, vv_i)
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INSN_LASX(xvssrlrni_wu_d, vv_i)
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INSN_LASX(xvssrlrni_du_q, vv_i)
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INSN_LASX(xvssrarni_b_h, vv_i)
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INSN_LASX(xvssrarni_h_w, vv_i)
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INSN_LASX(xvssrarni_w_d, vv_i)
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INSN_LASX(xvssrarni_d_q, vv_i)
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INSN_LASX(xvssrarni_bu_h, vv_i)
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INSN_LASX(xvssrarni_hu_w, vv_i)
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INSN_LASX(xvssrarni_wu_d, vv_i)
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INSN_LASX(xvssrarni_du_q, vv_i)
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INSN_LASX(xvreplgr2vr_b, vr)
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INSN_LASX(xvreplgr2vr_h, vr)
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INSN_LASX(xvreplgr2vr_w, vr)
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@ -3895,6 +3895,18 @@ TRANS(vssrlrn_wu_d, LSX, gen_vvv, gen_helper_vssrlrn_wu_d)
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TRANS(vssrarn_bu_h, LSX, gen_vvv, gen_helper_vssrarn_bu_h)
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TRANS(vssrarn_hu_w, LSX, gen_vvv, gen_helper_vssrarn_hu_w)
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TRANS(vssrarn_wu_d, LSX, gen_vvv, gen_helper_vssrarn_wu_d)
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TRANS(xvssrlrn_b_h, LASX, gen_xxx, gen_helper_vssrlrn_b_h)
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TRANS(xvssrlrn_h_w, LASX, gen_xxx, gen_helper_vssrlrn_h_w)
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TRANS(xvssrlrn_w_d, LASX, gen_xxx, gen_helper_vssrlrn_w_d)
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TRANS(xvssrarn_b_h, LASX, gen_xxx, gen_helper_vssrarn_b_h)
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TRANS(xvssrarn_h_w, LASX, gen_xxx, gen_helper_vssrarn_h_w)
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TRANS(xvssrarn_w_d, LASX, gen_xxx, gen_helper_vssrarn_w_d)
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TRANS(xvssrlrn_bu_h, LASX, gen_xxx, gen_helper_vssrlrn_bu_h)
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TRANS(xvssrlrn_hu_w, LASX, gen_xxx, gen_helper_vssrlrn_hu_w)
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TRANS(xvssrlrn_wu_d, LASX, gen_xxx, gen_helper_vssrlrn_wu_d)
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TRANS(xvssrarn_bu_h, LASX, gen_xxx, gen_helper_vssrarn_bu_h)
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TRANS(xvssrarn_hu_w, LASX, gen_xxx, gen_helper_vssrarn_hu_w)
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TRANS(xvssrarn_wu_d, LASX, gen_xxx, gen_helper_vssrarn_wu_d)
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TRANS(vssrlrni_b_h, LSX, gen_vv_i, gen_helper_vssrlrni_b_h)
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TRANS(vssrlrni_h_w, LSX, gen_vv_i, gen_helper_vssrlrni_h_w)
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@ -3912,6 +3924,22 @@ TRANS(vssrarni_bu_h, LSX, gen_vv_i, gen_helper_vssrarni_bu_h)
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TRANS(vssrarni_hu_w, LSX, gen_vv_i, gen_helper_vssrarni_hu_w)
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TRANS(vssrarni_wu_d, LSX, gen_vv_i, gen_helper_vssrarni_wu_d)
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TRANS(vssrarni_du_q, LSX, gen_vv_i, gen_helper_vssrarni_du_q)
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TRANS(xvssrlrni_b_h, LASX, gen_xx_i, gen_helper_vssrlrni_b_h)
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TRANS(xvssrlrni_h_w, LASX, gen_xx_i, gen_helper_vssrlrni_h_w)
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TRANS(xvssrlrni_w_d, LASX, gen_xx_i, gen_helper_vssrlrni_w_d)
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TRANS(xvssrlrni_d_q, LASX, gen_xx_i, gen_helper_vssrlrni_d_q)
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TRANS(xvssrarni_b_h, LASX, gen_xx_i, gen_helper_vssrarni_b_h)
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TRANS(xvssrarni_h_w, LASX, gen_xx_i, gen_helper_vssrarni_h_w)
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TRANS(xvssrarni_w_d, LASX, gen_xx_i, gen_helper_vssrarni_w_d)
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TRANS(xvssrarni_d_q, LASX, gen_xx_i, gen_helper_vssrarni_d_q)
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TRANS(xvssrlrni_bu_h, LASX, gen_xx_i, gen_helper_vssrlrni_bu_h)
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TRANS(xvssrlrni_hu_w, LASX, gen_xx_i, gen_helper_vssrlrni_hu_w)
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TRANS(xvssrlrni_wu_d, LASX, gen_xx_i, gen_helper_vssrlrni_wu_d)
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TRANS(xvssrlrni_du_q, LASX, gen_xx_i, gen_helper_vssrlrni_du_q)
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TRANS(xvssrarni_bu_h, LASX, gen_xx_i, gen_helper_vssrarni_bu_h)
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TRANS(xvssrarni_hu_w, LASX, gen_xx_i, gen_helper_vssrarni_hu_w)
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TRANS(xvssrarni_wu_d, LASX, gen_xx_i, gen_helper_vssrarni_wu_d)
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TRANS(xvssrarni_du_q, LASX, gen_xx_i, gen_helper_vssrarni_du_q)
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TRANS(vclo_b, LSX, gen_vv, gen_helper_vclo_b)
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TRANS(vclo_h, LSX, gen_vv, gen_helper_vclo_h)
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@ -1740,6 +1740,36 @@ xvssrani_hu_w 0111 01110110 01001 ..... ..... ..... @vv_ui5
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xvssrani_wu_d 0111 01110110 0101 ...... ..... ..... @vv_ui6
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xvssrani_du_q 0111 01110110 011 ....... ..... ..... @vv_ui7
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xvssrlrn_b_h 0111 01010000 00001 ..... ..... ..... @vvv
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xvssrlrn_h_w 0111 01010000 00010 ..... ..... ..... @vvv
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xvssrlrn_w_d 0111 01010000 00011 ..... ..... ..... @vvv
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xvssrarn_b_h 0111 01010000 00101 ..... ..... ..... @vvv
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xvssrarn_h_w 0111 01010000 00110 ..... ..... ..... @vvv
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xvssrarn_w_d 0111 01010000 00111 ..... ..... ..... @vvv
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xvssrlrn_bu_h 0111 01010000 10001 ..... ..... ..... @vvv
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xvssrlrn_hu_w 0111 01010000 10010 ..... ..... ..... @vvv
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xvssrlrn_wu_d 0111 01010000 10011 ..... ..... ..... @vvv
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xvssrarn_bu_h 0111 01010000 10101 ..... ..... ..... @vvv
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xvssrarn_hu_w 0111 01010000 10110 ..... ..... ..... @vvv
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xvssrarn_wu_d 0111 01010000 10111 ..... ..... ..... @vvv
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xvssrlrni_b_h 0111 01110101 00000 1 .... ..... ..... @vv_ui4
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xvssrlrni_h_w 0111 01110101 00001 ..... ..... ..... @vv_ui5
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xvssrlrni_w_d 0111 01110101 0001 ...... ..... ..... @vv_ui6
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xvssrlrni_d_q 0111 01110101 001 ....... ..... ..... @vv_ui7
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xvssrarni_b_h 0111 01110110 10000 1 .... ..... ..... @vv_ui4
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xvssrarni_h_w 0111 01110110 10001 ..... ..... ..... @vv_ui5
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xvssrarni_w_d 0111 01110110 1001 ...... ..... ..... @vv_ui6
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xvssrarni_d_q 0111 01110110 101 ....... ..... ..... @vv_ui7
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xvssrlrni_bu_h 0111 01110101 01000 1 .... ..... ..... @vv_ui4
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xvssrlrni_hu_w 0111 01110101 01001 ..... ..... ..... @vv_ui5
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xvssrlrni_wu_d 0111 01110101 0101 ...... ..... ..... @vv_ui6
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xvssrlrni_du_q 0111 01110101 011 ....... ..... ..... @vv_ui7
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xvssrarni_bu_h 0111 01110110 11000 1 .... ..... ..... @vv_ui4
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xvssrarni_hu_w 0111 01110110 11001 ..... ..... ..... @vv_ui5
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xvssrarni_wu_d 0111 01110110 1101 ...... ..... ..... @vv_ui6
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xvssrarni_du_q 0111 01110110 111 ....... ..... ..... @vv_ui7
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xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr
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xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr
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xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr
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@ -1827,7 +1827,7 @@ static T1 do_ssrlrns_ ## E1(T2 e2, int sa, int sh) \
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\
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shft_res = do_vsrlr_ ## E2(e2, sa); \
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T1 mask; \
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mask = (1ull << sh) -1; \
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mask = (1ull << sh) - 1; \
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if (shft_res > mask) { \
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return mask; \
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} else { \
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@ -1839,23 +1839,29 @@ SSRLRNS(B, H, uint16_t, int16_t, uint8_t)
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SSRLRNS(H, W, uint32_t, int32_t, uint16_t)
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SSRLRNS(W, D, uint64_t, int64_t, uint32_t)
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#define VSSRLRN(NAME, BIT, T, E1, E2) \
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void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
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{ \
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int i; \
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VReg *Vd = (VReg *)vd; \
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VReg *Vj = (VReg *)vj; \
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VReg *Vk = (VReg *)vk; \
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\
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for (i = 0; i < LSX_LEN/BIT; i++) { \
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Vd->E1(i) = do_ssrlrns_ ## E1(Vj->E2(i), (T)Vk->E2(i)%BIT, BIT/2 -1); \
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} \
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Vd->D(1) = 0; \
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#define VSSRLRN(NAME, BIT, E1, E2, E3) \
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void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
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{ \
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int i, j, ofs; \
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VReg *Vd = (VReg *)vd; \
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VReg *Vj = (VReg *)vj; \
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VReg *Vk = (VReg *)vk; \
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int oprsz = simd_oprsz(desc); \
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\
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ofs = LSX_LEN / BIT; \
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for (i = 0; i < oprsz / 16; i++) { \
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for (j = 0; j < ofs; j++) { \
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Vd->E1(j + ofs * 2 * i) = do_ssrlrns_ ## E1(Vj->E2(j + ofs * i), \
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Vk->E3(j + ofs * i) % BIT, \
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BIT / 2 - 1); \
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} \
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Vd->D(2 * i + 1) = 0; \
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} \
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}
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VSSRLRN(vssrlrn_b_h, 16, uint16_t, B, H)
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VSSRLRN(vssrlrn_h_w, 32, uint32_t, H, W)
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VSSRLRN(vssrlrn_w_d, 64, uint64_t, W, D)
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VSSRLRN(vssrlrn_b_h, 16, B, H, UH)
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VSSRLRN(vssrlrn_h_w, 32, H, W, UW)
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VSSRLRN(vssrlrn_w_d, 64, W, D, UD)
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#define SSRARNS(E1, E2, T1, T2) \
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static T1 do_ssrarns_ ## E1(T1 e2, int sa, int sh) \
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@ -1864,7 +1870,7 @@ static T1 do_ssrarns_ ## E1(T1 e2, int sa, int sh) \
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\
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shft_res = do_vsrar_ ## E2(e2, sa); \
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T2 mask; \
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mask = (1ll << sh) -1; \
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mask = (1ll << sh) - 1; \
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if (shft_res > mask) { \
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return mask; \
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} else if (shft_res < -(mask +1)) { \
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@ -1878,23 +1884,29 @@ SSRARNS(B, H, int16_t, int8_t)
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SSRARNS(H, W, int32_t, int16_t)
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SSRARNS(W, D, int64_t, int32_t)
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#define VSSRARN(NAME, BIT, T, E1, E2) \
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void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
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{ \
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int i; \
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VReg *Vd = (VReg *)vd; \
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VReg *Vj = (VReg *)vj; \
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VReg *Vk = (VReg *)vk; \
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\
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for (i = 0; i < LSX_LEN/BIT; i++) { \
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Vd->E1(i) = do_ssrarns_ ## E1(Vj->E2(i), (T)Vk->E2(i)%BIT, BIT/2 -1); \
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} \
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Vd->D(1) = 0; \
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#define VSSRARN(NAME, BIT, E1, E2, E3) \
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void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
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{ \
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int i, j, ofs; \
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VReg *Vd = (VReg *)vd; \
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VReg *Vj = (VReg *)vj; \
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VReg *Vk = (VReg *)vk; \
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int oprsz = simd_oprsz(desc); \
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\
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ofs = LSX_LEN / BIT; \
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for (i = 0; i < oprsz / 16; i++) { \
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for (j = 0; j < ofs; j++) { \
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Vd->E1(j + ofs * 2 * i) = do_ssrarns_ ## E1(Vj->E2(j + ofs * i), \
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Vk->E3(j + ofs * i) % BIT, \
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BIT/ 2 - 1); \
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} \
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Vd->D(2 * i + 1) = 0; \
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} \
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}
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VSSRARN(vssrarn_b_h, 16, uint16_t, B, H)
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VSSRARN(vssrarn_h_w, 32, uint32_t, H, W)
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VSSRARN(vssrarn_w_d, 64, uint64_t, W, D)
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VSSRARN(vssrarn_b_h, 16, B, H, UH)
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VSSRARN(vssrarn_h_w, 32, H, W, UW)
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VSSRARN(vssrarn_w_d, 64, W, D, UD)
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#define SSRLRNU(E1, E2, T1, T2, T3) \
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static T1 do_ssrlrnu_ ## E1(T3 e2, int sa, int sh) \
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@ -1904,7 +1916,7 @@ static T1 do_ssrlrnu_ ## E1(T3 e2, int sa, int sh) \
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shft_res = do_vsrlr_ ## E2(e2, sa); \
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\
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T2 mask; \
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mask = (1ull << sh) -1; \
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mask = (1ull << sh) - 1; \
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if (shft_res > mask) { \
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return mask; \
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} else { \
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@ -1916,23 +1928,29 @@ SSRLRNU(B, H, uint16_t, uint8_t, int16_t)
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SSRLRNU(H, W, uint32_t, uint16_t, int32_t)
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SSRLRNU(W, D, uint64_t, uint32_t, int64_t)
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#define VSSRLRNU(NAME, BIT, T, E1, E2) \
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void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
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{ \
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int i; \
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VReg *Vd = (VReg *)vd; \
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VReg *Vj = (VReg *)vj; \
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VReg *Vk = (VReg *)vk; \
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\
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for (i = 0; i < LSX_LEN/BIT; i++) { \
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Vd->E1(i) = do_ssrlrnu_ ## E1(Vj->E2(i), (T)Vk->E2(i)%BIT, BIT/2); \
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} \
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Vd->D(1) = 0; \
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#define VSSRLRNU(NAME, BIT, E1, E2, E3) \
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void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
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{ \
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int i, j, ofs; \
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VReg *Vd = (VReg *)vd; \
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VReg *Vj = (VReg *)vj; \
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VReg *Vk = (VReg *)vk; \
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int oprsz = simd_oprsz(desc); \
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\
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ofs = LSX_LEN / BIT; \
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for (i = 0; i < oprsz / 16; i++) { \
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for (j = 0; j < ofs; j++) { \
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Vd->E1(j + ofs * 2 * i) = do_ssrlrnu_ ## E1(Vj->E2(j + ofs * i), \
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Vk->E3(j + ofs * i) % BIT, \
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BIT / 2); \
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} \
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Vd->D(2 * i + 1) = 0; \
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} \
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}
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VSSRLRNU(vssrlrn_bu_h, 16, uint16_t, B, H)
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VSSRLRNU(vssrlrn_hu_w, 32, uint32_t, H, W)
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VSSRLRNU(vssrlrn_wu_d, 64, uint64_t, W, D)
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VSSRLRNU(vssrlrn_bu_h, 16, B, H, UH)
|
||||
VSSRLRNU(vssrlrn_hu_w, 32, H, W, UW)
|
||||
VSSRLRNU(vssrlrn_wu_d, 64, W, D, UD)
|
||||
|
||||
#define SSRARNU(E1, E2, T1, T2, T3) \
|
||||
static T1 do_ssrarnu_ ## E1(T3 e2, int sa, int sh) \
|
||||
@ -1945,7 +1963,7 @@ static T1 do_ssrarnu_ ## E1(T3 e2, int sa, int sh) \
|
||||
shft_res = do_vsrar_ ## E2(e2, sa); \
|
||||
} \
|
||||
T2 mask; \
|
||||
mask = (1ull << sh) -1; \
|
||||
mask = (1ull << sh) - 1; \
|
||||
if (shft_res > mask) { \
|
||||
return mask; \
|
||||
} else { \
|
||||
@ -1957,126 +1975,162 @@ SSRARNU(B, H, uint16_t, uint8_t, int16_t)
|
||||
SSRARNU(H, W, uint32_t, uint16_t, int32_t)
|
||||
SSRARNU(W, D, uint64_t, uint32_t, int64_t)
|
||||
|
||||
#define VSSRARNU(NAME, BIT, T, E1, E2) \
|
||||
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
|
||||
{ \
|
||||
int i; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
VReg *Vk = (VReg *)vk; \
|
||||
\
|
||||
for (i = 0; i < LSX_LEN/BIT; i++) { \
|
||||
Vd->E1(i) = do_ssrarnu_ ## E1(Vj->E2(i), (T)Vk->E2(i)%BIT, BIT/2); \
|
||||
} \
|
||||
Vd->D(1) = 0; \
|
||||
#define VSSRARNU(NAME, BIT, E1, E2, E3) \
|
||||
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
|
||||
{ \
|
||||
int i, j, ofs; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
VReg *Vk = (VReg *)vk; \
|
||||
int oprsz = simd_oprsz(desc); \
|
||||
\
|
||||
ofs = LSX_LEN / BIT; \
|
||||
for (i = 0; i < oprsz / 16; i++) { \
|
||||
for (j = 0; j < ofs; j++) { \
|
||||
Vd->E1(j + ofs * 2 * i) = do_ssrarnu_ ## E1(Vj->E2(j + ofs * i), \
|
||||
Vk->E3(j + ofs * i) % BIT, \
|
||||
BIT / 2); \
|
||||
} \
|
||||
Vd->D(2 * i + 1) = 0; \
|
||||
} \
|
||||
}
|
||||
|
||||
VSSRARNU(vssrarn_bu_h, 16, uint16_t, B, H)
|
||||
VSSRARNU(vssrarn_hu_w, 32, uint32_t, H, W)
|
||||
VSSRARNU(vssrarn_wu_d, 64, uint64_t, W, D)
|
||||
VSSRARNU(vssrarn_bu_h, 16, B, H, UH)
|
||||
VSSRARNU(vssrarn_hu_w, 32, H, W, UW)
|
||||
VSSRARNU(vssrarn_wu_d, 64, W, D, UD)
|
||||
|
||||
#define VSSRLRNI(NAME, BIT, E1, E2) \
|
||||
void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
|
||||
{ \
|
||||
int i; \
|
||||
VReg temp; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
\
|
||||
for (i = 0; i < LSX_LEN/BIT; i++) { \
|
||||
temp.E1(i) = do_ssrlrns_ ## E1(Vj->E2(i), imm, BIT/2 -1); \
|
||||
temp.E1(i + LSX_LEN/BIT) = do_ssrlrns_ ## E1(Vd->E2(i), imm, BIT/2 -1);\
|
||||
} \
|
||||
*Vd = temp; \
|
||||
#define VSSRLRNI(NAME, BIT, E1, E2) \
|
||||
void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
|
||||
{ \
|
||||
int i, j, ofs; \
|
||||
VReg temp = {}; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
int oprsz = simd_oprsz(desc); \
|
||||
\
|
||||
ofs = LSX_LEN / BIT; \
|
||||
for (i = 0; i < oprsz / 16; i++) { \
|
||||
for (j = 0; j < ofs; j++) { \
|
||||
temp.E1(j + ofs * 2 * i) = do_ssrlrns_ ## E1(Vj->E2(j + ofs * i), \
|
||||
imm, BIT / 2 - 1); \
|
||||
temp.E1(j + ofs * (2 * i + 1)) = do_ssrlrns_ ## E1(Vd->E2(j + ofs * i), \
|
||||
imm, BIT / 2 - 1); \
|
||||
} \
|
||||
} \
|
||||
*Vd = temp; \
|
||||
}
|
||||
|
||||
#define VSSRLRNI_Q(NAME, sh) \
|
||||
void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
|
||||
{ \
|
||||
Int128 shft_res1, shft_res2, mask, r1, r2; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
\
|
||||
if (imm == 0) { \
|
||||
shft_res1 = Vj->Q(0); \
|
||||
shft_res2 = Vd->Q(0); \
|
||||
} else { \
|
||||
r1 = int128_and(int128_urshift(Vj->Q(0), (imm -1)), int128_one()); \
|
||||
r2 = int128_and(int128_urshift(Vd->Q(0), (imm -1)), int128_one()); \
|
||||
\
|
||||
shft_res1 = (int128_add(int128_urshift(Vj->Q(0), imm), r1)); \
|
||||
shft_res2 = (int128_add(int128_urshift(Vd->Q(0), imm), r2)); \
|
||||
} \
|
||||
\
|
||||
mask = int128_sub(int128_lshift(int128_one(), sh), int128_one()); \
|
||||
\
|
||||
if (int128_ult(mask, shft_res1)) { \
|
||||
Vd->D(0) = int128_getlo(mask); \
|
||||
}else { \
|
||||
Vd->D(0) = int128_getlo(shft_res1); \
|
||||
} \
|
||||
\
|
||||
if (int128_ult(mask, shft_res2)) { \
|
||||
Vd->D(1) = int128_getlo(mask); \
|
||||
}else { \
|
||||
Vd->D(1) = int128_getlo(shft_res2); \
|
||||
} \
|
||||
static void do_vssrlrni_q(VReg *Vd, VReg * Vj,
|
||||
uint64_t imm, int idx, Int128 mask)
|
||||
{
|
||||
Int128 shft_res1, shft_res2, r1, r2;
|
||||
if (imm == 0) {
|
||||
shft_res1 = Vj->Q(idx);
|
||||
shft_res2 = Vd->Q(idx);
|
||||
} else {
|
||||
r1 = int128_and(int128_urshift(Vj->Q(idx), (imm - 1)), int128_one());
|
||||
r2 = int128_and(int128_urshift(Vd->Q(idx), (imm - 1)), int128_one());
|
||||
shft_res1 = (int128_add(int128_urshift(Vj->Q(idx), imm), r1));
|
||||
shft_res2 = (int128_add(int128_urshift(Vd->Q(idx), imm), r2));
|
||||
}
|
||||
|
||||
if (int128_ult(mask, shft_res1)) {
|
||||
Vd->D(idx * 2) = int128_getlo(mask);
|
||||
}else {
|
||||
Vd->D(idx * 2) = int128_getlo(shft_res1);
|
||||
}
|
||||
|
||||
if (int128_ult(mask, shft_res2)) {
|
||||
Vd->D(idx * 2 + 1) = int128_getlo(mask);
|
||||
}else {
|
||||
Vd->D(idx * 2 + 1) = int128_getlo(shft_res2);
|
||||
}
|
||||
}
|
||||
|
||||
void HELPER(vssrlrni_d_q)(void *vd, void *vj, uint64_t imm, uint32_t desc)
|
||||
{
|
||||
int i;
|
||||
Int128 mask;
|
||||
VReg *Vd = (VReg *)vd;
|
||||
VReg *Vj = (VReg *)vj;
|
||||
int oprsz = simd_oprsz(desc);
|
||||
|
||||
mask = int128_sub(int128_lshift(int128_one(), 63), int128_one());
|
||||
|
||||
for (i = 0; i < oprsz / 16; i++) {
|
||||
do_vssrlrni_q(Vd, Vj, imm, i, mask);
|
||||
}
|
||||
}
|
||||
|
||||
VSSRLRNI(vssrlrni_b_h, 16, B, H)
|
||||
VSSRLRNI(vssrlrni_h_w, 32, H, W)
|
||||
VSSRLRNI(vssrlrni_w_d, 64, W, D)
|
||||
VSSRLRNI_Q(vssrlrni_d_q, 63)
|
||||
|
||||
#define VSSRARNI(NAME, BIT, E1, E2) \
|
||||
void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
|
||||
{ \
|
||||
int i; \
|
||||
VReg temp; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
\
|
||||
for (i = 0; i < LSX_LEN/BIT; i++) { \
|
||||
temp.E1(i) = do_ssrarns_ ## E1(Vj->E2(i), imm, BIT/2 -1); \
|
||||
temp.E1(i + LSX_LEN/BIT) = do_ssrarns_ ## E1(Vd->E2(i), imm, BIT/2 -1); \
|
||||
} \
|
||||
*Vd = temp; \
|
||||
#define VSSRARNI(NAME, BIT, E1, E2) \
|
||||
void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
|
||||
{ \
|
||||
int i, j, ofs; \
|
||||
VReg temp = {}; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
int oprsz = simd_oprsz(desc); \
|
||||
\
|
||||
ofs = LSX_LEN / BIT; \
|
||||
for (i = 0; i < oprsz / 16; i++) { \
|
||||
for (j = 0; j < ofs; j++) { \
|
||||
temp.E1(j + ofs * 2 * i) = do_ssrarns_ ## E1(Vj->E2(j + ofs * i), \
|
||||
imm, BIT / 2 - 1); \
|
||||
temp.E1(j + ofs * (2 * i + 1)) = do_ssrarns_ ## E1(Vd->E2(j + ofs * i), \
|
||||
imm, BIT / 2 - 1); \
|
||||
} \
|
||||
} \
|
||||
*Vd = temp; \
|
||||
}
|
||||
|
||||
static void do_vssrarni_d_q(VReg *Vd, VReg *Vj,
|
||||
uint64_t imm, int idx, Int128 mask1, Int128 mask2)
|
||||
{
|
||||
Int128 shft_res1, shft_res2, r1, r2;
|
||||
|
||||
if (imm == 0) {
|
||||
shft_res1 = Vj->Q(idx);
|
||||
shft_res2 = Vd->Q(idx);
|
||||
} else {
|
||||
r1 = int128_and(int128_rshift(Vj->Q(idx), (imm - 1)), int128_one());
|
||||
r2 = int128_and(int128_rshift(Vd->Q(idx), (imm - 1)), int128_one());
|
||||
shft_res1 = int128_add(int128_rshift(Vj->Q(idx), imm), r1);
|
||||
shft_res2 = int128_add(int128_rshift(Vd->Q(idx), imm), r2);
|
||||
}
|
||||
if (int128_gt(shft_res1, mask1)) {
|
||||
Vd->D(idx * 2) = int128_getlo(mask1);
|
||||
} else if (int128_lt(shft_res1, int128_neg(mask2))) {
|
||||
Vd->D(idx * 2) = int128_getlo(mask2);
|
||||
} else {
|
||||
Vd->D(idx * 2) = int128_getlo(shft_res1);
|
||||
}
|
||||
|
||||
if (int128_gt(shft_res2, mask1)) {
|
||||
Vd->D(idx * 2 + 1) = int128_getlo(mask1);
|
||||
} else if (int128_lt(shft_res2, int128_neg(mask2))) {
|
||||
Vd->D(idx * 2 + 1) = int128_getlo(mask2);
|
||||
} else {
|
||||
Vd->D(idx * 2 + 1) = int128_getlo(shft_res2);
|
||||
}
|
||||
}
|
||||
|
||||
void HELPER(vssrarni_d_q)(void *vd, void *vj, uint64_t imm, uint32_t desc)
|
||||
{
|
||||
Int128 shft_res1, shft_res2, mask1, mask2, r1, r2;
|
||||
int i;
|
||||
Int128 mask1, mask2;
|
||||
VReg *Vd = (VReg *)vd;
|
||||
VReg *Vj = (VReg *)vj;
|
||||
|
||||
if (imm == 0) {
|
||||
shft_res1 = Vj->Q(0);
|
||||
shft_res2 = Vd->Q(0);
|
||||
} else {
|
||||
r1 = int128_and(int128_rshift(Vj->Q(0), (imm -1)), int128_one());
|
||||
r2 = int128_and(int128_rshift(Vd->Q(0), (imm -1)), int128_one());
|
||||
|
||||
shft_res1 = int128_add(int128_rshift(Vj->Q(0), imm), r1);
|
||||
shft_res2 = int128_add(int128_rshift(Vd->Q(0), imm), r2);
|
||||
}
|
||||
int oprsz = simd_oprsz(desc);
|
||||
|
||||
mask1 = int128_sub(int128_lshift(int128_one(), 63), int128_one());
|
||||
mask2 = int128_lshift(int128_one(), 63);
|
||||
|
||||
if (int128_gt(shft_res1, mask1)) {
|
||||
Vd->D(0) = int128_getlo(mask1);
|
||||
} else if (int128_lt(shft_res1, int128_neg(mask2))) {
|
||||
Vd->D(0) = int128_getlo(mask2);
|
||||
} else {
|
||||
Vd->D(0) = int128_getlo(shft_res1);
|
||||
}
|
||||
|
||||
if (int128_gt(shft_res2, mask1)) {
|
||||
Vd->D(1) = int128_getlo(mask1);
|
||||
} else if (int128_lt(shft_res2, int128_neg(mask2))) {
|
||||
Vd->D(1) = int128_getlo(mask2);
|
||||
} else {
|
||||
Vd->D(1) = int128_getlo(shft_res2);
|
||||
for (i = 0; i < oprsz / 16; i++) {
|
||||
do_vssrarni_d_q(Vd, Vj, imm, i, mask1, mask2);
|
||||
}
|
||||
}
|
||||
|
||||
@ -2084,82 +2138,119 @@ VSSRARNI(vssrarni_b_h, 16, B, H)
|
||||
VSSRARNI(vssrarni_h_w, 32, H, W)
|
||||
VSSRARNI(vssrarni_w_d, 64, W, D)
|
||||
|
||||
#define VSSRLRNUI(NAME, BIT, E1, E2) \
|
||||
void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
|
||||
{ \
|
||||
int i; \
|
||||
VReg temp; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
\
|
||||
for (i = 0; i < LSX_LEN/BIT; i++) { \
|
||||
temp.E1(i) = do_ssrlrnu_ ## E1(Vj->E2(i), imm, BIT/2); \
|
||||
temp.E1(i + LSX_LEN/BIT) = do_ssrlrnu_ ## E1(Vd->E2(i), imm, BIT/2); \
|
||||
} \
|
||||
*Vd = temp; \
|
||||
#define VSSRLRNUI(NAME, BIT, E1, E2) \
|
||||
void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
|
||||
{ \
|
||||
int i, j, ofs; \
|
||||
VReg temp = {}; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
int oprsz = simd_oprsz(desc); \
|
||||
\
|
||||
ofs = LSX_LEN / BIT; \
|
||||
for (i = 0; i < oprsz / 16; i++) { \
|
||||
for (j = 0; j < ofs; j++) { \
|
||||
temp.E1(j + ofs * 2 * i) = do_ssrlrnu_ ## E1(Vj->E2(j + ofs * i), \
|
||||
imm, BIT / 2); \
|
||||
temp.E1(j + ofs * (2 * i + 1)) = do_ssrlrnu_ ## E1(Vd->E2(j + ofs * i), \
|
||||
imm, BIT / 2); \
|
||||
} \
|
||||
} \
|
||||
*Vd = temp; \
|
||||
}
|
||||
|
||||
void HELPER(vssrlrni_du_q)(void *vd, void *vj, uint64_t imm, uint32_t desc)
|
||||
{
|
||||
int i;
|
||||
Int128 mask;
|
||||
VReg *Vd = (VReg *)vd;
|
||||
VReg *Vj = (VReg *)vj;
|
||||
int oprsz = simd_oprsz(desc);
|
||||
|
||||
mask = int128_sub(int128_lshift(int128_one(), 64), int128_one());
|
||||
|
||||
for (i = 0; i < oprsz / 16; i++) {
|
||||
do_vssrlrni_q(Vd, Vj, imm, i, mask);
|
||||
}
|
||||
}
|
||||
|
||||
VSSRLRNUI(vssrlrni_bu_h, 16, B, H)
|
||||
VSSRLRNUI(vssrlrni_hu_w, 32, H, W)
|
||||
VSSRLRNUI(vssrlrni_wu_d, 64, W, D)
|
||||
VSSRLRNI_Q(vssrlrni_du_q, 64)
|
||||
|
||||
#define VSSRARNUI(NAME, BIT, E1, E2) \
|
||||
void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
|
||||
{ \
|
||||
int i; \
|
||||
VReg temp; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
\
|
||||
for (i = 0; i < LSX_LEN/BIT; i++) { \
|
||||
temp.E1(i) = do_ssrarnu_ ## E1(Vj->E2(i), imm, BIT/2); \
|
||||
temp.E1(i + LSX_LEN/BIT) = do_ssrarnu_ ## E1(Vd->E2(i), imm, BIT/2); \
|
||||
} \
|
||||
*Vd = temp; \
|
||||
#define VSSRARNUI(NAME, BIT, E1, E2) \
|
||||
void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
|
||||
{ \
|
||||
int i, j, ofs; \
|
||||
VReg temp = {}; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
int oprsz = simd_oprsz(desc); \
|
||||
\
|
||||
ofs = LSX_LEN / BIT; \
|
||||
for (i = 0; i < oprsz / 16; i++) { \
|
||||
for (j = 0; j < ofs; j++) { \
|
||||
temp.E1(j + ofs * 2 * i) = do_ssrarnu_ ## E1(Vj->E2(j + ofs * i), \
|
||||
imm, BIT / 2); \
|
||||
temp.E1(j + ofs * (2 * i + 1)) = do_ssrarnu_ ## E1(Vd->E2(j + ofs * i), \
|
||||
imm, BIT / 2); \
|
||||
} \
|
||||
} \
|
||||
*Vd = temp; \
|
||||
}
|
||||
|
||||
static void do_vssrarni_du_q(VReg *Vd, VReg *Vj,
|
||||
uint64_t imm, int idx, Int128 mask1, Int128 mask2)
|
||||
{
|
||||
Int128 shft_res1, shft_res2, r1, r2;
|
||||
|
||||
if (imm == 0) {
|
||||
shft_res1 = Vj->Q(idx);
|
||||
shft_res2 = Vd->Q(idx);
|
||||
} else {
|
||||
r1 = int128_and(int128_rshift(Vj->Q(idx), (imm - 1)), int128_one());
|
||||
r2 = int128_and(int128_rshift(Vd->Q(idx), (imm - 1)), int128_one());
|
||||
shft_res1 = int128_add(int128_rshift(Vj->Q(idx), imm), r1);
|
||||
shft_res2 = int128_add(int128_rshift(Vd->Q(idx), imm), r2);
|
||||
}
|
||||
|
||||
if (int128_lt(Vj->Q(idx), int128_zero())) {
|
||||
shft_res1 = int128_zero();
|
||||
}
|
||||
if (int128_lt(Vd->Q(idx), int128_zero())) {
|
||||
shft_res2 = int128_zero();
|
||||
}
|
||||
|
||||
if (int128_gt(shft_res1, mask1)) {
|
||||
Vd->D(idx * 2) = int128_getlo(mask1);
|
||||
} else if (int128_lt(shft_res1, int128_neg(mask2))) {
|
||||
Vd->D(idx * 2) = int128_getlo(mask2);
|
||||
} else {
|
||||
Vd->D(idx * 2) = int128_getlo(shft_res1);
|
||||
}
|
||||
|
||||
if (int128_gt(shft_res2, mask1)) {
|
||||
Vd->D(idx * 2 + 1) = int128_getlo(mask1);
|
||||
} else if (int128_lt(shft_res2, int128_neg(mask2))) {
|
||||
Vd->D(idx * 2 + 1) = int128_getlo(mask2);
|
||||
} else {
|
||||
Vd->D(idx * 2 + 1) = int128_getlo(shft_res2);
|
||||
}
|
||||
}
|
||||
|
||||
void HELPER(vssrarni_du_q)(void *vd, void *vj, uint64_t imm, uint32_t desc)
|
||||
{
|
||||
Int128 shft_res1, shft_res2, mask1, mask2, r1, r2;
|
||||
int i;
|
||||
Int128 mask1, mask2;
|
||||
VReg *Vd = (VReg *)vd;
|
||||
VReg *Vj = (VReg *)vj;
|
||||
|
||||
if (imm == 0) {
|
||||
shft_res1 = Vj->Q(0);
|
||||
shft_res2 = Vd->Q(0);
|
||||
} else {
|
||||
r1 = int128_and(int128_rshift(Vj->Q(0), (imm -1)), int128_one());
|
||||
r2 = int128_and(int128_rshift(Vd->Q(0), (imm -1)), int128_one());
|
||||
|
||||
shft_res1 = int128_add(int128_rshift(Vj->Q(0), imm), r1);
|
||||
shft_res2 = int128_add(int128_rshift(Vd->Q(0), imm), r2);
|
||||
}
|
||||
|
||||
if (int128_lt(Vj->Q(0), int128_zero())) {
|
||||
shft_res1 = int128_zero();
|
||||
}
|
||||
if (int128_lt(Vd->Q(0), int128_zero())) {
|
||||
shft_res2 = int128_zero();
|
||||
}
|
||||
int oprsz = simd_oprsz(desc);
|
||||
|
||||
mask1 = int128_sub(int128_lshift(int128_one(), 64), int128_one());
|
||||
mask2 = int128_lshift(int128_one(), 64);
|
||||
|
||||
if (int128_gt(shft_res1, mask1)) {
|
||||
Vd->D(0) = int128_getlo(mask1);
|
||||
} else if (int128_lt(shft_res1, int128_neg(mask2))) {
|
||||
Vd->D(0) = int128_getlo(mask2);
|
||||
} else {
|
||||
Vd->D(0) = int128_getlo(shft_res1);
|
||||
}
|
||||
|
||||
if (int128_gt(shft_res2, mask1)) {
|
||||
Vd->D(1) = int128_getlo(mask1);
|
||||
} else if (int128_lt(shft_res2, int128_neg(mask2))) {
|
||||
Vd->D(1) = int128_getlo(mask2);
|
||||
} else {
|
||||
Vd->D(1) = int128_getlo(shft_res2);
|
||||
for (i = 0; i < oprsz / 16; i++) {
|
||||
do_vssrarni_du_q(Vd, Vj, imm, i, mask1, mask2);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user