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target/sparc: Prefer fast cpu_env() over slower CPU QOM cast macro
Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240129164514.73104-27-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
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@ -32,9 +32,8 @@
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static void sparc_cpu_reset_hold(Object *obj)
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static void sparc_cpu_reset_hold(Object *obj)
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{
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{
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CPUState *cs = CPU(obj);
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CPUState *cs = CPU(obj);
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SPARCCPU *cpu = SPARC_CPU(cs);
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SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj);
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SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj);
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CPUSPARCState *env = &cpu->env;
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CPUSPARCState *env = cpu_env(cs);
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if (scc->parent_phases.hold) {
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if (scc->parent_phases.hold) {
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scc->parent_phases.hold(obj);
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scc->parent_phases.hold(obj);
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@ -83,8 +82,7 @@ static void sparc_cpu_reset_hold(Object *obj)
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static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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{
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if (interrupt_request & CPU_INTERRUPT_HARD) {
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if (interrupt_request & CPU_INTERRUPT_HARD) {
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SPARCCPU *cpu = SPARC_CPU(cs);
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CPUSPARCState *env = cpu_env(cs);
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CPUSPARCState *env = &cpu->env;
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if (cpu_interrupts_enabled(env) && env->interrupt_index > 0) {
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if (cpu_interrupts_enabled(env) && env->interrupt_index > 0) {
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int pil = env->interrupt_index & 0xf;
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int pil = env->interrupt_index & 0xf;
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@ -613,8 +611,7 @@ static void cpu_print_cc(FILE *f, uint32_t cc)
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static void sparc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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static void sparc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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{
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{
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SPARCCPU *cpu = SPARC_CPU(cs);
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CPUSPARCState *env = cpu_env(cs);
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CPUSPARCState *env = &cpu->env;
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int i, x;
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int i, x;
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qemu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc,
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qemu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc,
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@ -711,11 +708,8 @@ static void sparc_cpu_synchronize_from_tb(CPUState *cs,
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static bool sparc_cpu_has_work(CPUState *cs)
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static bool sparc_cpu_has_work(CPUState *cs)
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{
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{
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SPARCCPU *cpu = SPARC_CPU(cs);
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CPUSPARCState *env = &cpu->env;
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return (cs->interrupt_request & CPU_INTERRUPT_HARD) &&
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return (cs->interrupt_request & CPU_INTERRUPT_HARD) &&
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cpu_interrupts_enabled(env);
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cpu_interrupts_enabled(cpu_env(cs));
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}
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}
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static int sparc_cpu_mmu_index(CPUState *cs, bool ifetch)
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static int sparc_cpu_mmu_index(CPUState *cs, bool ifetch)
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@ -777,8 +771,7 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
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CPUState *cs = CPU(dev);
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CPUState *cs = CPU(dev);
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SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev);
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SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev);
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Error *local_err = NULL;
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Error *local_err = NULL;
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SPARCCPU *cpu = SPARC_CPU(dev);
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CPUSPARCState *env = cpu_env(cs);
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CPUSPARCState *env = &cpu->env;
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#if defined(CONFIG_USER_ONLY)
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#if defined(CONFIG_USER_ONLY)
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/* We are emulating the kernel, which will trap and emulate float128. */
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/* We are emulating the kernel, which will trap and emulate float128. */
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@ -29,8 +29,7 @@
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int sparc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
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int sparc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
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{
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{
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SPARCCPU *cpu = SPARC_CPU(cs);
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CPUSPARCState *env = cpu_env(cs);
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CPUSPARCState *env = &cpu->env;
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if (n < 8) {
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if (n < 8) {
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/* g0..g7 */
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/* g0..g7 */
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@ -99,8 +99,7 @@ void cpu_check_irqs(CPUSPARCState *env)
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void sparc_cpu_do_interrupt(CPUState *cs)
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void sparc_cpu_do_interrupt(CPUState *cs)
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{
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{
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SPARCCPU *cpu = SPARC_CPU(cs);
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CPUSPARCState *env = cpu_env(cs);
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CPUSPARCState *env = &cpu->env;
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int cwp, intno = cs->exception_index;
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int cwp, intno = cs->exception_index;
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if (qemu_loglevel_mask(CPU_LOG_INT)) {
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if (qemu_loglevel_mask(CPU_LOG_INT)) {
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@ -130,8 +130,7 @@ void cpu_check_irqs(CPUSPARCState *env)
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void sparc_cpu_do_interrupt(CPUState *cs)
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void sparc_cpu_do_interrupt(CPUState *cs)
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{
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{
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SPARCCPU *cpu = SPARC_CPU(cs);
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CPUSPARCState *env = cpu_env(cs);
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CPUSPARCState *env = &cpu->env;
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int intno = cs->exception_index;
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int intno = cs->exception_index;
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trap_state *tsptr;
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trap_state *tsptr;
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@ -418,8 +418,7 @@ static void sparc_raise_mmu_fault(CPUState *cs, hwaddr addr,
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bool is_write, bool is_exec, int is_asi,
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bool is_write, bool is_exec, int is_asi,
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unsigned size, uintptr_t retaddr)
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unsigned size, uintptr_t retaddr)
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{
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{
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SPARCCPU *cpu = SPARC_CPU(cs);
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CPUSPARCState *env = cpu_env(cs);
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CPUSPARCState *env = &cpu->env;
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int fault_type;
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int fault_type;
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#ifdef DEBUG_UNASSIGNED
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#ifdef DEBUG_UNASSIGNED
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@ -480,8 +479,7 @@ static void sparc_raise_mmu_fault(CPUState *cs, hwaddr addr,
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bool is_write, bool is_exec, int is_asi,
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bool is_write, bool is_exec, int is_asi,
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unsigned size, uintptr_t retaddr)
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unsigned size, uintptr_t retaddr)
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{
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{
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SPARCCPU *cpu = SPARC_CPU(cs);
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CPUSPARCState *env = cpu_env(cs);
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CPUSPARCState *env = &cpu->env;
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#ifdef DEBUG_UNASSIGNED
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#ifdef DEBUG_UNASSIGNED
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printf("Unassigned mem access to " HWADDR_FMT_plx " from " TARGET_FMT_lx
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printf("Unassigned mem access to " HWADDR_FMT_plx " from " TARGET_FMT_lx
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@ -206,8 +206,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr)
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bool probe, uintptr_t retaddr)
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{
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{
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SPARCCPU *cpu = SPARC_CPU(cs);
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CPUSPARCState *env = cpu_env(cs);
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CPUSPARCState *env = &cpu->env;
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CPUTLBEntryFull full = {};
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CPUTLBEntryFull full = {};
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target_ulong vaddr;
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target_ulong vaddr;
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int error_code = 0, access_index;
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int error_code = 0, access_index;
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@ -391,8 +390,7 @@ void dump_mmu(CPUSPARCState *env)
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int sparc_cpu_memory_rw_debug(CPUState *cs, vaddr address,
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int sparc_cpu_memory_rw_debug(CPUState *cs, vaddr address,
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uint8_t *buf, int len, bool is_write)
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uint8_t *buf, int len, bool is_write)
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{
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{
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SPARCCPU *cpu = SPARC_CPU(cs);
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CPUSPARCState *env = cpu_env(cs);
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CPUSPARCState *env = &cpu->env;
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target_ulong addr = address;
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target_ulong addr = address;
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int i;
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int i;
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int len1;
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int len1;
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@ -759,8 +757,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr)
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bool probe, uintptr_t retaddr)
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{
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{
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SPARCCPU *cpu = SPARC_CPU(cs);
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CPUSPARCState *env = cpu_env(cs);
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CPUSPARCState *env = &cpu->env;
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CPUTLBEntryFull full = {};
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CPUTLBEntryFull full = {};
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int error_code = 0, access_index;
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int error_code = 0, access_index;
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@ -898,8 +895,7 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
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hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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{
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{
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SPARCCPU *cpu = SPARC_CPU(cs);
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CPUSPARCState *env = cpu_env(cs);
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CPUSPARCState *env = &cpu->env;
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hwaddr phys_addr;
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hwaddr phys_addr;
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int mmu_idx = cpu_mmu_index(cs, false);
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int mmu_idx = cpu_mmu_index(cs, false);
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@ -916,8 +912,7 @@ G_NORETURN void sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
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int mmu_idx,
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int mmu_idx,
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uintptr_t retaddr)
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uintptr_t retaddr)
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{
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{
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SPARCCPU *cpu = SPARC_CPU(cs);
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CPUSPARCState *env = cpu_env(cs);
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CPUSPARCState *env = &cpu->env;
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#ifdef TARGET_SPARC64
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#ifdef TARGET_SPARC64
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env->dmmu.sfsr = build_sfsr(env, mmu_idx, access_type);
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env->dmmu.sfsr = build_sfsr(env, mmu_idx, access_type);
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@ -4844,13 +4844,12 @@ TRANS(FCMPEq, ALL, do_fcmpq, a, true)
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static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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{
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{
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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CPUSPARCState *env = cpu_env(cs);
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int bound;
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int bound;
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dc->pc = dc->base.pc_first;
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dc->pc = dc->base.pc_first;
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dc->npc = (target_ulong)dc->base.tb->cs_base;
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dc->npc = (target_ulong)dc->base.tb->cs_base;
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dc->mem_idx = dc->base.tb->flags & TB_FLAG_MMU_MASK;
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dc->mem_idx = dc->base.tb->flags & TB_FLAG_MMU_MASK;
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dc->def = &env->def;
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dc->def = &cpu_env(cs)->def;
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dc->fpu_enabled = tb_fpu_enabled(dc->base.tb->flags);
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dc->fpu_enabled = tb_fpu_enabled(dc->base.tb->flags);
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dc->address_mask_32bit = tb_am_enabled(dc->base.tb->flags);
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dc->address_mask_32bit = tb_am_enabled(dc->base.tb->flags);
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#ifndef CONFIG_USER_ONLY
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#ifndef CONFIG_USER_ONLY
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@ -4900,10 +4899,9 @@ static void sparc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
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static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
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static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
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{
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{
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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CPUSPARCState *env = cpu_env(cs);
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unsigned int insn;
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unsigned int insn;
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insn = translator_ldl(env, &dc->base, dc->pc);
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insn = translator_ldl(cpu_env(cs), &dc->base, dc->pc);
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dc->base.pc_next += 4;
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dc->base.pc_next += 4;
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if (!decode(dc, insn)) {
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if (!decode(dc, insn)) {
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@ -5106,8 +5104,7 @@ void sparc_restore_state_to_opc(CPUState *cs,
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const TranslationBlock *tb,
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const TranslationBlock *tb,
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const uint64_t *data)
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const uint64_t *data)
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{
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{
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SPARCCPU *cpu = SPARC_CPU(cs);
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CPUSPARCState *env = cpu_env(cs);
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CPUSPARCState *env = &cpu->env;
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target_ulong pc = data[0];
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target_ulong pc = data[0];
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target_ulong npc = data[1];
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target_ulong npc = data[1];
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