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fixed dirty bit support for 4M pages (L4 Pistachio fix)

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@549 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard 2004-01-18 21:39:51 +00:00
parent 69e5bc9068
commit 777aca2fd3
1 changed files with 2 additions and 2 deletions
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2
target-i386/helper2.c
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@ -304,7 +304,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, uint32_t addr,
/* if PSE bit is set, then we use a 4MB page */
if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
is_dirty = is_write && !(pde & PG_DIRTY_MASK);
if (!(pde & PG_ACCESSED_MASK)) {
if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
pde |= PG_ACCESSED_MASK;
if (is_dirty)
pde |= PG_DIRTY_MASK;