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target/arm: Implement SVE2 SPLICE, EXT

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-48-richard.henderson@linaro.org
Message-Id: <20200423180347.9403-1-steplong@quicinc.com>
[rth: Rename the trans_* functions to *_sve2.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Stephen Long 2021-05-24 18:03:13 -07:00 committed by Peter Maydell
parent 4f26756b87
commit 751147928e
2 changed files with 39 additions and 7 deletions
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11
target/arm/sve.decode
View File

@ -494,10 +494,14 @@ CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s
### SVE Permute - Extract Group ### SVE Permute - Extract Group
# SVE extract vector (immediate offset) # SVE extract vector (destructive)
EXT 00000101 001 ..... 000 ... rm:5 rd:5 \ EXT 00000101 001 ..... 000 ... rm:5 rd:5 \
&rrri rn=%reg_movprfx imm=%imm8_16_10 &rrri rn=%reg_movprfx imm=%imm8_16_10
# SVE2 extract vector (constructive)
EXT_sve2 00000101 011 ..... 000 ... rn:5 rd:5 \
&rri imm=%imm8_16_10
### SVE Permute - Unpredicated Group ### SVE Permute - Unpredicated Group
# SVE broadcast general register # SVE broadcast general register
@ -588,9 +592,12 @@ REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn
REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn
RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn
# SVE vector splice (predicated) # SVE vector splice (predicated, destructive)
SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm
# SVE2 vector splice (predicated, constructive)
SPLICE_sve2 00000101 .. 101 101 100 ... ..... ..... @rd_pg_rn
### SVE Select Vectors Group ### SVE Select Vectors Group
# SVE select vector elements (predicated) # SVE select vector elements (predicated)

35
target/arm/translate-sve.c
View File

@ -2266,18 +2266,18 @@ static bool trans_CPY_z_i(DisasContext *s, arg_CPY_z_i *a)
*** SVE Permute Extract Group *** SVE Permute Extract Group
*/ */
static bool trans_EXT(DisasContext *s, arg_EXT *a) static bool do_EXT(DisasContext *s, int rd, int rn, int rm, int imm)
{ {
if (!sve_access_check(s)) { if (!sve_access_check(s)) {
return true; return true;
} }
unsigned vsz = vec_full_reg_size(s); unsigned vsz = vec_full_reg_size(s);
unsigned n_ofs = a->imm >= vsz ? 0 : a->imm; unsigned n_ofs = imm >= vsz ? 0 : imm;
unsigned n_siz = vsz - n_ofs; unsigned n_siz = vsz - n_ofs;
unsigned d = vec_full_reg_offset(s, a->rd); unsigned d = vec_full_reg_offset(s, rd);
unsigned n = vec_full_reg_offset(s, a->rn); unsigned n = vec_full_reg_offset(s, rn);
unsigned m = vec_full_reg_offset(s, a->rm); unsigned m = vec_full_reg_offset(s, rm);
/* Use host vector move insns if we have appropriate sizes /* Use host vector move insns if we have appropriate sizes
* and no unfortunate overlap. * and no unfortunate overlap.
@ -2296,6 +2296,19 @@ static bool trans_EXT(DisasContext *s, arg_EXT *a)
return true; return true;
} }
static bool trans_EXT(DisasContext *s, arg_EXT *a)
{
return do_EXT(s, a->rd, a->rn, a->rm, a->imm);
}
static bool trans_EXT_sve2(DisasContext *s, arg_rri *a)
{
if (!dc_isar_feature(aa64_sve2, s)) {
return false;
}
return do_EXT(s, a->rd, a->rn, (a->rn + 1) % 32, a->imm);
}
/* /*
*** SVE Permute - Unpredicated Group *** SVE Permute - Unpredicated Group
*/ */
@ -3013,6 +3026,18 @@ static bool trans_SPLICE(DisasContext *s, arg_rprr_esz *a)
return true; return true;
} }
static bool trans_SPLICE_sve2(DisasContext *s, arg_rpr_esz *a)
{
if (!dc_isar_feature(aa64_sve2, s)) {
return false;
}
if (sve_access_check(s)) {
gen_gvec_ool_zzzp(s, gen_helper_sve_splice,
a->rd, a->rn, (a->rn + 1) % 32, a->pg, a->esz);
}
return true;
}
/* /*
*** SVE Integer Compare - Vectors Group *** SVE Integer Compare - Vectors Group
*/ */