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target/cpu: Restrict cpu_get_phys_page_debug() handlers to sysemu
The 'hwaddr' type is only available / meaningful on system emulation. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221216215519.5522-5-philmd@linaro.org>
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@ -276,9 +276,9 @@ extern const VMStateDescription vmstate_alpha_cpu;
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void alpha_cpu_do_interrupt(CPUState *cpu);
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bool alpha_cpu_exec_interrupt(CPUState *cpu, int int_req);
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hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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#endif /* !CONFIG_USER_ONLY */
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void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags);
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hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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int alpha_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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@ -1104,10 +1104,10 @@ extern const VMStateDescription vmstate_arm_cpu;
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void arm_cpu_do_interrupt(CPUState *cpu);
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void arm_v7m_cpu_do_interrupt(CPUState *cpu);
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#endif /* !CONFIG_USER_ONLY */
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hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
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MemTxAttrs *attrs);
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#endif /* !CONFIG_USER_ONLY */
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int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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@ -193,12 +193,11 @@ bool cris_cpu_exec_interrupt(CPUState *cpu, int int_req);
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bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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hwaddr cris_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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#endif
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void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags);
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hwaddr cris_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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int crisv10_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int cris_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int cris_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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@ -322,11 +322,11 @@ static inline void cpu_hppa_change_prot_id(CPUHPPAState *env) { }
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void cpu_hppa_change_prot_id(CPUHPPAState *env);
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#endif
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hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr);
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int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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void hppa_cpu_dump_state(CPUState *cs, FILE *f, int);
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#ifndef CONFIG_USER_ONLY
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hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr);
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bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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@ -1987,9 +1987,6 @@ void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
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void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags);
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hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
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MemTxAttrs *attrs);
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int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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@ -1997,6 +1994,8 @@ void x86_cpu_list(void);
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int cpu_x86_support_mca_broadcast(CPUX86State *env);
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#ifndef CONFIG_USER_ONLY
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hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
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MemTxAttrs *attrs);
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int cpu_get_pic_interrupt(CPUX86State *s);
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/* MSDOS compatibility mode FPU exception support */
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@ -176,9 +176,9 @@ struct ArchCPU {
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#ifndef CONFIG_USER_ONLY
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void m68k_cpu_do_interrupt(CPUState *cpu);
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bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req);
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hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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#endif /* !CONFIG_USER_ONLY */
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void m68k_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
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hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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int m68k_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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@ -358,13 +358,13 @@ struct ArchCPU {
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#ifndef CONFIG_USER_ONLY
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void mb_cpu_do_interrupt(CPUState *cs);
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bool mb_cpu_exec_interrupt(CPUState *cs, int int_req);
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hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
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MemTxAttrs *attrs);
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#endif /* !CONFIG_USER_ONLY */
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G_NORETURN void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
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MMUAccessType access_type,
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int mmu_idx, uintptr_t retaddr);
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void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
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hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
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MemTxAttrs *attrs);
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int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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int mb_cpu_gdb_read_stack_protect(CPUArchState *cpu, GByteArray *buf, int reg);
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@ -262,7 +262,6 @@ void nios2_tcg_init(void);
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void nios2_cpu_do_interrupt(CPUState *cs);
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void dump_mmu(CPUNios2State *env);
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void nios2_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
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hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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G_NORETURN void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
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MMUAccessType access_type, int mmu_idx,
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uintptr_t retaddr);
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@ -288,6 +287,7 @@ static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch)
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}
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#ifndef CONFIG_USER_ONLY
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hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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@ -312,7 +312,6 @@ struct ArchCPU {
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void cpu_openrisc_list(void);
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void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
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hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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void openrisc_translate_init(void);
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@ -321,6 +320,8 @@ int print_insn_or1k(bfd_vma addr, disassemble_info *info);
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#define cpu_list cpu_openrisc_list
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#ifndef CONFIG_USER_ONLY
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hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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@ -1361,12 +1361,12 @@ static inline bool vhyp_cpu_in_nested(PowerPCCPU *cpu)
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#endif /* CONFIG_USER_ONLY */
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void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
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hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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int ppc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int ppc_cpu_gdb_read_register_apple(CPUState *cpu, GByteArray *buf, int reg);
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int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
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#ifndef CONFIG_USER_ONLY
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hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu);
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const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name);
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#endif
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@ -573,7 +573,6 @@ bool riscv_cpu_virt_enabled(CPURISCVState *env);
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void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
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bool riscv_cpu_two_stage_lookup(int mmu_idx);
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int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
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hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
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MMUAccessType access_type, int mmu_idx,
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uintptr_t retaddr);
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@ -592,6 +591,7 @@ void riscv_cpu_list(void);
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#define cpu_mmu_index riscv_cpu_mmu_index
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#ifndef CONFIG_USER_ONLY
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hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
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void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
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int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts);
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@ -123,11 +123,11 @@ const char *rx_crname(uint8_t cr);
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#ifndef CONFIG_USER_ONLY
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void rx_cpu_do_interrupt(CPUState *cpu);
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bool rx_cpu_exec_interrupt(CPUState *cpu, int int_req);
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hwaddr rx_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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#endif /* !CONFIG_USER_ONLY */
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void rx_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
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int rx_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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hwaddr rx_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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void rx_translate_init(void);
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void rx_cpu_list(void);
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@ -144,9 +144,9 @@ bool rx_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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return false;
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}
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#endif /* !CONFIG_USER_ONLY */
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hwaddr rx_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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{
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return addr;
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}
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#endif /* !CONFIG_USER_ONLY */
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@ -214,7 +214,6 @@ struct ArchCPU {
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void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
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hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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G_NORETURN void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
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@ -225,6 +224,7 @@ void sh4_translate_init(void);
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void sh4_cpu_list(void);
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#if !defined(CONFIG_USER_ONLY)
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hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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@ -569,10 +569,11 @@ struct ArchCPU {
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#ifndef CONFIG_USER_ONLY
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extern const VMStateDescription vmstate_sparc_cpu;
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hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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#endif
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void sparc_cpu_do_interrupt(CPUState *cpu);
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hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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int sparc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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G_NORETURN void sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
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@ -576,9 +576,9 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
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unsigned size, MMUAccessType access_type,
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int mmu_idx, MemTxAttrs attrs,
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MemTxResult response, uintptr_t retaddr);
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hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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#endif
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void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
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hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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void xtensa_count_regs(const XtensaConfig *config,
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unsigned *n_regs, unsigned *n_core_regs);
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int xtensa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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