mirror of
https://github.com/qemu/qemu.git
synced 2024-11-26 12:23:36 +08:00
pci: fix bridge IO/BASE
commit 5caef97a16010f818ea8b950e2ee24ba876643ad introduced a regression: we do not make IO base/limit upper 16 bit registers writeable, so we should report a 16 bit IO range type, not a 32 bit one. Note that PCI_PREF_RANGE_TYPE_32 is 0x0, but PCI_IO_RANGE_TYPE_32 is 0x1. In particular, this broke sparc64. Note: this just reverts to behaviour prior to the commit above. Making PCI_IO_BASE_UPPER16 and PCI_IO_LIMIT_UPPER16 registers writeable should, and seems to, work just as well, but as no system seems to actually be interested in 32 bit IO, let's not make unnecessary changes. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
parent
633442ff56
commit
6891710274
4
hw/pci.c
4
hw/pci.c
@ -633,8 +633,8 @@ static void pci_init_mask_bridge(PCIDevice *d)
|
||||
memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
|
||||
|
||||
/* Supported memory and i/o types */
|
||||
d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_32;
|
||||
d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_32;
|
||||
d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16;
|
||||
d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16;
|
||||
pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE,
|
||||
PCI_PREF_RANGE_TYPE_64);
|
||||
pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT,
|
||||
|
Loading…
Reference in New Issue
Block a user