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target-ppc: Add SPE register read/write using XML
Don't read/write SPEFSCR until we figure out what to do about exceptions. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6425 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -9345,6 +9345,51 @@ static int gdb_set_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
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return 0;
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}
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static int gdb_get_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
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{
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if (n < 32) {
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#if defined(TARGET_PPC64)
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stl_p(mem_buf, env->gpr[n] >> 32);
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#else
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stl_p(mem_buf, env->gprh[n]);
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#endif
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return 4;
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}
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if (n == 33) {
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stq_p(mem_buf, env->spe_acc);
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return 8;
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}
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if (n == 34) {
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/* SPEFSCR not implemented */
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memset(mem_buf, 0, 4);
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return 4;
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}
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return 0;
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}
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static int gdb_set_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
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{
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if (n < 32) {
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#if defined(TARGET_PPC64)
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target_ulong lo = (uint32_t)env->gpr[n];
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target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
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env->gpr[n] = lo | hi;
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#else
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env->gprh[n] = ldl_p(mem_buf);
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#endif
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return 4;
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}
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if (n == 33) {
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env->spe_acc = ldq_p(mem_buf);
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return 8;
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}
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if (n == 34) {
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/* SPEFSCR not implemented */
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return 4;
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}
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return 0;
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}
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int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
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{
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env->msr_mask = def->msr_mask;
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@ -9366,6 +9411,11 @@ int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
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gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
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34, "power-altivec.xml", 0);
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}
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if ((def->insns_flags & PPC_SPE) | (def->insns_flags & PPC_SPEFPU)) {
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gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
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34, "power-spe.xml", 0);
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}
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#if defined(PPC_DUMP_CPU)
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{
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const char *mmu_model, *excp_model, *bus_model;
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