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target/riscv: Adjust trans_rev8_32 for riscv64

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When target_long is 64-bit, we still want a 32-bit bswap for rev8.
Since this opcode is specific to RV32, we need not conditionalize.

Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-12-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Richard Henderson 2021-10-19 20:17:05 -07:00 committed by Alistair Francis
parent 80347ae9f2
commit 673be37163
1 changed files with 6 additions and 1 deletions
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7
target/riscv/insn_trans/trans_rvb.c.inc
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@ -232,11 +232,16 @@ static bool trans_rol(DisasContext *ctx, arg_rol *a)
return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
}
static void gen_rev8_32(TCGv ret, TCGv src1)
{
tcg_gen_bswap32_tl(ret, src1, TCG_BSWAP_OS);
}
static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
{
REQUIRE_32BIT(ctx);
REQUIRE_ZBB(ctx);
return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
return gen_unary(ctx, a, EXT_NONE, gen_rev8_32);
}
static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)