mirror of
https://github.com/qemu/qemu.git
synced 2024-11-25 20:03:37 +08:00
i8254: convert to qdev
Convert to qdev. Don't expose PITState. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
parent
c74b88dffc
commit
64d7e9a421
61
hw/i8254.c
61
hw/i8254.c
@ -53,9 +53,12 @@ typedef struct PITChannelState {
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qemu_irq irq;
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} PITChannelState;
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struct PITState {
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typedef struct PITState {
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ISADevice dev;
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uint32_t irq;
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uint32_t iobase;
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PITChannelState channels[3];
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};
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} PITState;
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static PITState pit_state;
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@ -119,8 +122,9 @@ static int pit_get_out1(PITChannelState *s, int64_t current_time)
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return out;
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}
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int pit_get_out(PITState *pit, int channel, int64_t current_time)
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int pit_get_out(ISADevice *dev, int channel, int64_t current_time)
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{
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PITState *pit = DO_UPCAST(PITState, dev, dev);
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PITChannelState *s = &pit->channels[channel];
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return pit_get_out1(s, current_time);
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}
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@ -179,8 +183,9 @@ static int64_t pit_get_next_transition_time(PITChannelState *s,
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}
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/* val must be 0 or 1 */
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void pit_set_gate(PITState *pit, int channel, int val)
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void pit_set_gate(ISADevice *dev, int channel, int val)
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{
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PITState *pit = DO_UPCAST(PITState, dev, dev);
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PITChannelState *s = &pit->channels[channel];
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switch(s->mode) {
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@ -210,20 +215,23 @@ void pit_set_gate(PITState *pit, int channel, int val)
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s->gate = val;
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}
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int pit_get_gate(PITState *pit, int channel)
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int pit_get_gate(ISADevice *dev, int channel)
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{
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PITState *pit = DO_UPCAST(PITState, dev, dev);
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PITChannelState *s = &pit->channels[channel];
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return s->gate;
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}
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int pit_get_initial_count(PITState *pit, int channel)
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int pit_get_initial_count(ISADevice *dev, int channel)
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{
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PITState *pit = DO_UPCAST(PITState, dev, dev);
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PITChannelState *s = &pit->channels[channel];
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return s->count;
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}
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int pit_get_mode(PITState *pit, int channel)
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int pit_get_mode(ISADevice *dev, int channel)
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{
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PITState *pit = DO_UPCAST(PITState, dev, dev);
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PITChannelState *s = &pit->channels[channel];
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return s->mode;
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}
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@ -462,9 +470,9 @@ static const VMStateDescription vmstate_pit = {
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}
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};
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static void pit_reset(void *opaque)
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static void pit_reset(DeviceState *dev)
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{
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PITState *pit = opaque;
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PITState *pit = container_of(dev, PITState, dev.qdev);
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PITChannelState *s;
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int i;
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@ -498,20 +506,39 @@ void hpet_pit_enable(void)
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pit_load_count(s, 0);
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}
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PITState *pit_init(int base, qemu_irq irq)
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static int pit_initfn(ISADevice *dev)
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{
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PITState *pit = &pit_state;
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PITState *pit = DO_UPCAST(PITState, dev, dev);
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PITChannelState *s;
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s = &pit->channels[0];
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/* the timer 0 is connected to an IRQ */
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s->irq_timer = qemu_new_timer(vm_clock, pit_irq_timer, s);
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s->irq = irq;
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s->irq = isa_reserve_irq(pit->irq);
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vmstate_register(NULL, base, &vmstate_pit, pit);
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qemu_register_reset(pit_reset, pit);
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register_ioport_write(base, 4, 1, pit_ioport_write, pit);
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register_ioport_read(base, 3, 1, pit_ioport_read, pit);
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register_ioport_write(pit->iobase, 4, 1, pit_ioport_write, pit);
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register_ioport_read(pit->iobase, 3, 1, pit_ioport_read, pit);
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isa_init_ioport(dev, pit->iobase);
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return pit;
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return 0;
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}
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static ISADeviceInfo pit_info = {
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.qdev.name = "isa-pit",
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.qdev.size = sizeof(PITState),
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.qdev.vmsd = &vmstate_pit,
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.qdev.reset = pit_reset,
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.qdev.no_user = 1,
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.init = pit_initfn,
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.qdev.props = (Property[]) {
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DEFINE_PROP_UINT32("irq", PITState, irq, -1),
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DEFINE_PROP_HEX32("iobase", PITState, iobase, -1),
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DEFINE_PROP_END_OF_LIST(),
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},
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};
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static void pit_register(void)
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{
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isa_qdev_register(&pit_info);
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}
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device_init(pit_register)
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@ -67,7 +67,7 @@
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#define FULONG2E_ATI_SLOT 6
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#define FULONG2E_RTL8139_SLOT 7
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static PITState *pit;
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static ISADevice *pit;
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static struct _loaderparams {
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int ram_size;
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@ -369,7 +369,7 @@ static void mips_fulong2e_init(ram_addr_t ram_size, const char *boot_device,
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qdev_init_nofail(eeprom);
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/* init other devices */
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pit = pit_init(0x40, isa_reserve_irq(0));
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pit = pit_init(0x40, 0);
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cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
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DMA_init(0, cpu_exit_irq);
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@ -115,7 +115,7 @@ void mips_jazz_init (ram_addr_t ram_size,
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void* rc4030_opaque;
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int s_rtc, s_dma_dummy;
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NICInfo *nd;
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PITState *pit;
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ISADevice *pit;
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DriveInfo *fds[MAX_FD];
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qemu_irq esp_reset, dma_enable;
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qemu_irq *cpu_exit_irq;
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@ -181,7 +181,7 @@ void mips_jazz_init (ram_addr_t ram_size,
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isa_bus_irqs(i8259);
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cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
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DMA_init(0, cpu_exit_irq);
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pit = pit_init(0x40, i8259[0]);
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pit = pit_init(0x40, 0);
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pcspk_init(pit);
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/* ISA IO space at 0x90000000 */
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@ -68,7 +68,7 @@ typedef struct {
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SerialState *uart;
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} MaltaFPGAState;
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static PITState *pit;
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static ISADevice *pit;
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static struct _loaderparams {
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int ram_size;
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@ -930,7 +930,7 @@ void mips_malta_init (ram_addr_t ram_size,
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qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256));
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qdev_init_nofail(eeprom);
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}
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pit = pit_init(0x40, isa_reserve_irq(0));
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pit = pit_init(0x40, 0);
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cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
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DMA_init(0, cpu_exit_irq);
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@ -30,7 +30,7 @@ static const int ide_iobase[2] = { 0x1f0, 0x170 };
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static const int ide_iobase2[2] = { 0x3f6, 0x376 };
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static const int ide_irq[2] = { 14, 15 };
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static PITState *pit; /* PIT i8254 */
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static ISADevice *pit; /* PIT i8254 */
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/* i8254 PIT is attached to the IRQ0 at PIC i8259 */
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@ -274,7 +274,7 @@ void mips_r4k_init (ram_addr_t ram_size,
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isa_mmio_init(0x14000000, 0x00010000);
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isa_mem_base = 0x10000000;
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pit = pit_init(0x40, i8259[0]);
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pit = pit_init(0x40, 0);
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for(i = 0; i < MAX_SERIAL_PORTS; i++) {
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if (serial_hds[i]) {
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5
hw/pc.c
5
hw/pc.c
@ -1104,10 +1104,9 @@ void pc_basic_device_init(qemu_irq *isa_irq,
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{
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int i;
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DriveInfo *fd[MAX_FD];
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PITState *pit;
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qemu_irq rtc_irq = NULL;
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qemu_irq *a20_line;
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ISADevice *i8042, *port92, *vmmouse;
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ISADevice *i8042, *port92, *vmmouse, *pit;
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qemu_irq *cpu_exit_irq;
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register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
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@ -1128,7 +1127,7 @@ void pc_basic_device_init(qemu_irq *isa_irq,
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qemu_register_boot_set(pc_boot_set, *rtc_state);
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pit = pit_init(0x40, isa_reserve_irq(0));
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pit = pit_init(0x40, 0);
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pcspk_init(pit);
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for(i = 0; i < MAX_SERIAL_PORTS; i++) {
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25
hw/pc.h
25
hw/pc.h
@ -82,14 +82,23 @@ void isa_irq_handler(void *opaque, int n, int level);
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#define PIT_FREQ 1193182
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typedef struct PITState PITState;
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static inline ISADevice *pit_init(int base, int irq)
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{
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ISADevice *dev;
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PITState *pit_init(int base, qemu_irq irq);
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void pit_set_gate(PITState *pit, int channel, int val);
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int pit_get_gate(PITState *pit, int channel);
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int pit_get_initial_count(PITState *pit, int channel);
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int pit_get_mode(PITState *pit, int channel);
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int pit_get_out(PITState *pit, int channel, int64_t current_time);
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dev = isa_create("isa-pit");
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qdev_prop_set_uint32(&dev->qdev, "iobase", base);
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qdev_prop_set_uint32(&dev->qdev, "irq", irq);
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qdev_init_nofail(&dev->qdev);
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return dev;
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}
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void pit_set_gate(ISADevice *dev, int channel, int val);
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int pit_get_gate(ISADevice *dev, int channel);
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int pit_get_initial_count(ISADevice *dev, int channel);
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int pit_get_mode(ISADevice *dev, int channel);
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int pit_get_out(ISADevice *dev, int channel, int64_t current_time);
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void hpet_pit_disable(void);
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void hpet_pit_enable(void);
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@ -159,7 +168,7 @@ void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
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extern int no_hpet;
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/* pcspk.c */
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void pcspk_init(PITState *);
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void pcspk_init(ISADevice *pit);
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int pcspk_audio_init(qemu_irq *pic);
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/* piix_pci.c */
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@ -37,7 +37,7 @@ typedef struct {
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uint8_t sample_buf[PCSPK_BUF_LEN];
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QEMUSoundCard card;
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SWVoiceOut *voice;
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PITState *pit;
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ISADevice *pit;
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unsigned int pit_count;
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unsigned int samples;
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unsigned int play_pos;
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@ -137,7 +137,7 @@ static void pcspk_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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}
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}
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void pcspk_init(PITState *pit)
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void pcspk_init(ISADevice *pit)
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{
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PCSpkState *s = &pcspk_state;
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@ -82,7 +82,7 @@ static const int ide_irq[2] = { 13, 13 };
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static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
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static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
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//static PITState *pit;
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//static ISADevice *pit;
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/* ISA IO ports bridge */
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#define PPC_IO_BASE 0x80000000
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@ -662,7 +662,7 @@ static void ppc_prep_init (ram_addr_t ram_size,
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/* init basic PC hardware */
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pci_vga_init(pci_bus);
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// openpic = openpic_init(0x00000000, 0xF0000000, 1);
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// pit = pit_init(0x40, i8259[0]);
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// pit = pit_init(0x40, 0);
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rtc_init(2000, NULL);
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if (serial_hds[0])
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