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pcie: Add support for PCIe CAP v1
Added support for PCIe CAP v1, while reusing some of the existing v2 infrastructure. Signed-off-by: Dmitry Fleytman <dmitry.fleytman@ravellosystems.com> Signed-off-by: Leonid Bloch <leonid.bloch@ravellosystems.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
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@ -43,26 +43,15 @@
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/***************************************************************************
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* pci express capability helper functions
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*/
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int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port)
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static void
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pcie_cap_v1_fill(uint8_t *exp_cap, uint8_t port, uint8_t type, uint8_t version)
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{
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int pos;
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uint8_t *exp_cap;
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assert(pci_is_express(dev));
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pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset,
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PCI_EXP_VER2_SIZEOF);
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if (pos < 0) {
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return pos;
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}
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dev->exp.exp_cap = pos;
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exp_cap = dev->config + pos;
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/* capability register
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interrupt message number defaults to 0 */
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interrupt message number defaults to 0 */
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pci_set_word(exp_cap + PCI_EXP_FLAGS,
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((type << PCI_EXP_FLAGS_TYPE_SHIFT) & PCI_EXP_FLAGS_TYPE) |
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PCI_EXP_FLAGS_VER2);
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version);
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/* device capability register
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* table 7-12:
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@ -81,7 +70,27 @@ int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port)
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pci_set_word(exp_cap + PCI_EXP_LNKSTA,
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PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25 |PCI_EXP_LNKSTA_DLLLA);
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}
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int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port)
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{
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/* PCIe cap v2 init */
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int pos;
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uint8_t *exp_cap;
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assert(pci_is_express(dev));
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pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, PCI_EXP_VER2_SIZEOF);
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if (pos < 0) {
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return pos;
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}
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dev->exp.exp_cap = pos;
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exp_cap = dev->config + pos;
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/* Filling values common with v1 */
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pcie_cap_v1_fill(exp_cap, port, type, PCI_EXP_FLAGS_VER2);
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/* Filling v2 specific values */
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pci_set_long(exp_cap + PCI_EXP_DEVCAP2,
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PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP);
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@ -89,7 +98,29 @@ int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port)
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return pos;
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}
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int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset)
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int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, uint8_t type,
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uint8_t port)
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{
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/* PCIe cap v1 init */
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int pos;
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uint8_t *exp_cap;
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assert(pci_is_express(dev));
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pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, PCI_EXP_VER1_SIZEOF);
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if (pos < 0) {
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return pos;
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}
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dev->exp.exp_cap = pos;
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exp_cap = dev->config + pos;
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pcie_cap_v1_fill(exp_cap, port, type, PCI_EXP_FLAGS_VER1);
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return pos;
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}
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static int
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pcie_endpoint_cap_common_init(PCIDevice *dev, uint8_t offset, uint8_t cap_size)
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{
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uint8_t type = PCI_EXP_TYPE_ENDPOINT;
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@ -102,7 +133,19 @@ int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset)
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type = PCI_EXP_TYPE_RC_END;
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}
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return pcie_cap_init(dev, offset, type, 0);
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return (cap_size == PCI_EXP_VER1_SIZEOF)
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? pcie_cap_v1_init(dev, offset, type, 0)
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: pcie_cap_init(dev, offset, type, 0);
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}
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int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset)
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{
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return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER2_SIZEOF);
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}
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int pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset)
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{
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return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER1_SIZEOF);
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}
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void pcie_cap_exit(PCIDevice *dev)
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@ -110,6 +153,11 @@ void pcie_cap_exit(PCIDevice *dev)
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pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER2_SIZEOF);
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}
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void pcie_cap_v1_exit(PCIDevice *dev)
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{
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pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER1_SIZEOF);
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}
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uint8_t pcie_cap_get_type(const PCIDevice *dev)
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{
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uint32_t pos = dev->exp.exp_cap;
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@ -80,8 +80,12 @@ struct PCIExpressDevice {
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/* PCI express capability helper functions */
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int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port);
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int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset,
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uint8_t type, uint8_t port);
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int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset);
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void pcie_cap_exit(PCIDevice *dev);
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int pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset);
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void pcie_cap_v1_exit(PCIDevice *dev);
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uint8_t pcie_cap_get_type(const PCIDevice *dev);
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void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector);
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uint8_t pcie_cap_flags_get_vector(PCIDevice *dev);
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@ -11,6 +11,7 @@
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/* express capability */
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#define PCI_EXP_VER1_SIZEOF 0x14 /* express capability of ver. 1 */
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#define PCI_EXP_VER2_SIZEOF 0x3c /* express capability of ver. 2 */
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#define PCI_EXT_CAP_VER_SHIFT 16
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#define PCI_EXT_CAP_NEXT_SHIFT 20
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@ -26,11 +27,11 @@
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(((x) + PCI_EXT_CAP_ALIGN - 1) & ~(PCI_EXT_CAP_ALIGN - 1))
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/* PCI_EXP_FLAGS */
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#define PCI_EXP_FLAGS_VER2 2 /* for now, supports only ver. 2 */
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#define PCI_EXP_FLAGS_VER1 1
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#define PCI_EXP_FLAGS_VER2 2
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#define PCI_EXP_FLAGS_IRQ_SHIFT ctz32(PCI_EXP_FLAGS_IRQ)
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#define PCI_EXP_FLAGS_TYPE_SHIFT ctz32(PCI_EXP_FLAGS_TYPE)
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/* PCI_EXP_LINK{CAP, STA} */
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/* link speed */
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#define PCI_EXP_LNK_LS_25 1
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