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Embedded PowerPC timers support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2555 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
j_mayer
parent
a8dea12f45
commit
636aaad7b5
212
hw/ppc.c
212
hw/ppc.c
@ -267,26 +267,224 @@ uint32_t cpu_ppc601_load_rtcl (CPUState *env)
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return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
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}
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/*****************************************************************************/
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/* Embedded PowerPC timers */
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target_ulong load_40x_pit (CPUState *env)
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/* PIT, FIT & WDT */
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typedef struct ppcemb_timer_t ppcemb_timer_t;
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struct ppcemb_timer_t {
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uint64_t pit_reload; /* PIT auto-reload value */
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uint64_t fit_next; /* Tick for next FIT interrupt */
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struct QEMUTimer *fit_timer;
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uint64_t wdt_next; /* Tick for next WDT interrupt */
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struct QEMUTimer *wdt_timer;
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};
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/* Fixed interval timer */
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static void cpu_4xx_fit_cb (void *opaque)
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{
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/* XXX: TODO */
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return 0;
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CPUState *env;
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ppc_tb_t *tb_env;
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ppcemb_timer_t *ppcemb_timer;
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uint64_t now, next;
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env = opaque;
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tb_env = env->tb_env;
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ppcemb_timer = tb_env->opaque;
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now = qemu_get_clock(vm_clock);
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switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) {
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case 0:
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next = 1 << 9;
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break;
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case 1:
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next = 1 << 13;
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break;
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case 2:
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next = 1 << 17;
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break;
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case 3:
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next = 1 << 21;
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break;
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default:
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/* Cannot occur, but makes gcc happy */
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return;
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}
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next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq);
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if (next == now)
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next++;
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qemu_mod_timer(ppcemb_timer->fit_timer, next);
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tb_env->decr_next = next;
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env->spr[SPR_40x_TSR] |= 1 << 26;
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if ((env->spr[SPR_40x_TCR] >> 23) & 0x1)
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ppc_set_irq(env, PPC_INTERRUPT_FIT, 1);
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if (loglevel) {
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fprintf(logfile, "%s: ir %d TCR %08x TSR %08x\n", __func__,
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(env->spr[SPR_40x_TCR] >> 23) & 0x1,
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env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
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}
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}
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/* Programmable interval timer */
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static void cpu_4xx_pit_cb (void *opaque)
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{
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CPUState *env;
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ppc_tb_t *tb_env;
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ppcemb_timer_t *ppcemb_timer;
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uint64_t now, next;
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env = opaque;
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tb_env = env->tb_env;
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ppcemb_timer = tb_env->opaque;
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now = qemu_get_clock(vm_clock);
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if ((env->spr[SPR_40x_TCR] >> 22) & 0x1) {
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/* Auto reload */
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next = now + muldiv64(ppcemb_timer->pit_reload,
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ticks_per_sec, tb_env->tb_freq);
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if (next == now)
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next++;
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qemu_mod_timer(tb_env->decr_timer, next);
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tb_env->decr_next = next;
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}
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env->spr[SPR_40x_TSR] |= 1 << 27;
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if ((env->spr[SPR_40x_TCR] >> 26) & 0x1)
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ppc_set_irq(env, PPC_INTERRUPT_PIT, 1);
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if (loglevel) {
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fprintf(logfile, "%s: ar %d ir %d TCR %08x TSR %08x %08lx\n", __func__,
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(env->spr[SPR_40x_TCR] >> 22) & 0x1,
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(env->spr[SPR_40x_TCR] >> 26) & 0x1,
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env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
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ppcemb_timer->pit_reload);
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}
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}
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/* Watchdog timer */
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static void cpu_4xx_wdt_cb (void *opaque)
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{
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CPUState *env;
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ppc_tb_t *tb_env;
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ppcemb_timer_t *ppcemb_timer;
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uint64_t now, next;
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env = opaque;
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tb_env = env->tb_env;
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ppcemb_timer = tb_env->opaque;
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now = qemu_get_clock(vm_clock);
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switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) {
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case 0:
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next = 1 << 17;
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break;
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case 1:
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next = 1 << 21;
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break;
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case 2:
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next = 1 << 25;
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break;
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case 3:
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next = 1 << 29;
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break;
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default:
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/* Cannot occur, but makes gcc happy */
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return;
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}
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next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq);
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if (next == now)
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next++;
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if (loglevel) {
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fprintf(logfile, "%s: TCR %08x TSR %08x\n", __func__,
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env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
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}
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switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {
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case 0x0:
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case 0x1:
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qemu_mod_timer(ppcemb_timer->wdt_timer, next);
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ppcemb_timer->wdt_next = next;
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env->spr[SPR_40x_TSR] |= 1 << 31;
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break;
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case 0x2:
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qemu_mod_timer(ppcemb_timer->wdt_timer, next);
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ppcemb_timer->wdt_next = next;
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env->spr[SPR_40x_TSR] |= 1 << 30;
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if ((env->spr[SPR_40x_TCR] >> 27) & 0x1)
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ppc_set_irq(env, PPC_INTERRUPT_WDT, 1);
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break;
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case 0x3:
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env->spr[SPR_40x_TSR] &= ~0x30000000;
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env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000;
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switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) {
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case 0x0:
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/* No reset */
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break;
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case 0x1: /* Core reset */
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case 0x2: /* Chip reset */
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case 0x3: /* System reset */
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qemu_system_reset_request();
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return;
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}
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}
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}
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void store_40x_pit (CPUState *env, target_ulong val)
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{
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/* XXX: TODO */
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ppc_tb_t *tb_env;
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ppcemb_timer_t *ppcemb_timer;
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uint64_t now, next;
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tb_env = env->tb_env;
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ppcemb_timer = tb_env->opaque;
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if (loglevel)
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fprintf(logfile, "%s %p %p\n", __func__, tb_env, ppcemb_timer);
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ppcemb_timer->pit_reload = val;
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if (val == 0) {
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/* Stop PIT */
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if (loglevel)
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fprintf(logfile, "%s: stop PIT\n", __func__);
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qemu_del_timer(tb_env->decr_timer);
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} else {
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if (loglevel)
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fprintf(logfile, "%s: start PIT 0x%08x\n", __func__, val);
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now = qemu_get_clock(vm_clock);
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next = now + muldiv64(val, ticks_per_sec, tb_env->tb_freq);
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if (next == now)
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next++;
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qemu_mod_timer(tb_env->decr_timer, next);
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tb_env->decr_next = next;
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}
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}
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void store_booke_tcr (CPUState *env, target_ulong val)
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target_ulong load_40x_pit (CPUState *env)
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{
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/* XXX: TODO */
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return cpu_ppc_load_decr(env);
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}
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void store_booke_tsr (CPUState *env, target_ulong val)
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{
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/* XXX: TODO */
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env->spr[SPR_40x_TSR] = val & 0xFC000000;
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}
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void store_booke_tcr (CPUState *env, target_ulong val)
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{
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/* We don't update timers now. Maybe we should... */
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env->spr[SPR_40x_TCR] = val & 0xFF800000;
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}
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void ppc_emb_timers_init (CPUState *env)
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{
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ppc_tb_t *tb_env;
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ppcemb_timer_t *ppcemb_timer;
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tb_env = env->tb_env;
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ppcemb_timer = qemu_mallocz(sizeof(ppcemb_timer_t));
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tb_env->opaque = ppcemb_timer;
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if (loglevel)
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fprintf(logfile, "%s %p %p\n", __func__, tb_env, ppcemb_timer);
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if (ppcemb_timer != NULL) {
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/* We use decr timer for PIT */
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tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_4xx_pit_cb, env);
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ppcemb_timer->fit_timer =
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qemu_new_timer(vm_clock, &cpu_4xx_fit_cb, env);
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ppcemb_timer->wdt_timer =
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qemu_new_timer(vm_clock, &cpu_4xx_wdt_cb, env);
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}
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}
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#if 0
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