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hw/timer: Add SiFive PWM support
This is the initial commit of the SiFive PWM timer. This is used by guest software as a timer and is included in the SiFive FU540 SoC. Signed-off-by: Justin Restivo <jrestivo@draper.com> Signed-off-by: Alexandra Clifford <aclifford@draper.com> Signed-off-by: Amanda Strnad <astrnad@draper.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 9f70a210acbfaf0e1ea6ad311ab892ac69134d8b.1631159656.git.alistair.francis@wdc.com
This commit is contained in:
Alistair Francis
parent
57a3a62265
commit
5bf6f1acdd
@ -25,6 +25,9 @@ config ALLWINNER_A10_PIT
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bool
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select PTIMER
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config SIFIVE_PWM
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bool
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config STM32F2XX_TIMER
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bool
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@ -35,5 +35,6 @@ softmmu_ss.add(when: 'CONFIG_STELLARIS_GPTM', if_true: files('stellaris-gptm.c')
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softmmu_ss.add(when: 'CONFIG_STM32F2XX_TIMER', if_true: files('stm32f2xx_timer.c'))
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softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_timer.c'))
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specific_ss.add(when: 'CONFIG_IBEX', if_true: files('ibex_timer.c'))
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softmmu_ss.add(when: 'CONFIG_SIFIVE_PWM', if_true: files('sifive_pwm.c'))
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specific_ss.add(when: 'CONFIG_AVR_TIMER16', if_true: files('avr_timer16.c'))
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468
hw/timer/sifive_pwm.c
Normal file
468
hw/timer/sifive_pwm.c
Normal file
@ -0,0 +1,468 @@
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/*
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* SiFive PWM
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*
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* Copyright (c) 2020 Western Digital
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*
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* Author: Alistair Francis <alistair.francis@wdc.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "trace.h"
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#include "hw/irq.h"
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#include "hw/timer/sifive_pwm.h"
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#include "hw/qdev-properties.h"
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#include "hw/registerfields.h"
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#include "migration/vmstate.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#define HAS_PWM_EN_BITS(cfg) ((cfg & R_CONFIG_ENONESHOT_MASK) || \
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(cfg & R_CONFIG_ENALWAYS_MASK))
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#define PWMCMP_MASK 0xFFFF
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#define PWMCOUNT_MASK 0x7FFFFFFF
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REG32(CONFIG, 0x00)
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FIELD(CONFIG, SCALE, 0, 4)
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FIELD(CONFIG, STICKY, 8, 1)
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FIELD(CONFIG, ZEROCMP, 9, 1)
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FIELD(CONFIG, DEGLITCH, 10, 1)
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FIELD(CONFIG, ENALWAYS, 12, 1)
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FIELD(CONFIG, ENONESHOT, 13, 1)
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FIELD(CONFIG, CMP0CENTER, 16, 1)
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FIELD(CONFIG, CMP1CENTER, 17, 1)
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FIELD(CONFIG, CMP2CENTER, 18, 1)
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FIELD(CONFIG, CMP3CENTER, 19, 1)
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FIELD(CONFIG, CMP0GANG, 24, 1)
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FIELD(CONFIG, CMP1GANG, 25, 1)
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FIELD(CONFIG, CMP2GANG, 26, 1)
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FIELD(CONFIG, CMP3GANG, 27, 1)
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FIELD(CONFIG, CMP0IP, 28, 1)
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FIELD(CONFIG, CMP1IP, 29, 1)
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FIELD(CONFIG, CMP2IP, 30, 1)
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FIELD(CONFIG, CMP3IP, 31, 1)
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REG32(COUNT, 0x08)
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REG32(PWMS, 0x10)
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REG32(PWMCMP0, 0x20)
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REG32(PWMCMP1, 0x24)
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REG32(PWMCMP2, 0x28)
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REG32(PWMCMP3, 0x2C)
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static inline uint64_t sifive_pwm_ns_to_ticks(SiFivePwmState *s,
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uint64_t time)
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{
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return muldiv64(time, s->freq_hz, NANOSECONDS_PER_SECOND);
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}
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static inline uint64_t sifive_pwm_ticks_to_ns(SiFivePwmState *s,
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uint64_t ticks)
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{
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return muldiv64(ticks, NANOSECONDS_PER_SECOND, s->freq_hz);
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}
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static inline uint64_t sifive_pwm_compute_scale(SiFivePwmState *s)
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{
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return s->pwmcfg & R_CONFIG_SCALE_MASK;
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}
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static void sifive_pwm_set_alarms(SiFivePwmState *s)
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{
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uint64_t now_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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if (HAS_PWM_EN_BITS(s->pwmcfg)) {
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/*
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* Subtract ticks from number of ticks when the timer was zero
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* and mask to the register width.
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*/
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uint64_t pwmcount = (sifive_pwm_ns_to_ticks(s, now_ns) -
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s->tick_offset) & PWMCOUNT_MASK;
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uint64_t scale = sifive_pwm_compute_scale(s);
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/* PWMs only contains PWMCMP_MASK bits starting at scale */
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uint64_t pwms = (pwmcount & (PWMCMP_MASK << scale)) >> scale;
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for (int i = 0; i < SIFIVE_PWM_CHANS; i++) {
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uint64_t pwmcmp = s->pwmcmp[i] & PWMCMP_MASK;
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uint64_t pwmcmp_ticks = pwmcmp << scale;
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/*
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* Per circuit diagram and spec, both cases raises corresponding
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* IP bit one clock cycle after time expires.
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*/
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if (pwmcmp > pwms) {
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uint64_t offset = pwmcmp_ticks - pwmcount + 1;
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uint64_t when_to_fire = now_ns +
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sifive_pwm_ticks_to_ns(s, offset);
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trace_sifive_pwm_set_alarm(when_to_fire, now_ns);
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timer_mod(&s->timer[i], when_to_fire);
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} else {
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/* Schedule interrupt for next cycle */
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trace_sifive_pwm_set_alarm(now_ns + 1, now_ns);
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timer_mod(&s->timer[i], now_ns + 1);
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}
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}
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} else {
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/*
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* If timer incrementing disabled, just do pwms > pwmcmp check since
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* a write may have happened to PWMs.
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*/
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uint64_t pwmcount = (s->tick_offset) & PWMCOUNT_MASK;
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uint64_t scale = sifive_pwm_compute_scale(s);
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uint64_t pwms = (pwmcount & (PWMCMP_MASK << scale)) >> scale;
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for (int i = 0; i < SIFIVE_PWM_CHANS; i++) {
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uint64_t pwmcmp = s->pwmcmp[i] & PWMCMP_MASK;
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if (pwms >= pwmcmp) {
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trace_sifive_pwm_set_alarm(now_ns + 1, now_ns);
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timer_mod(&s->timer[i], now_ns + 1);
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} else {
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/* Effectively disable timer by scheduling far in future. */
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trace_sifive_pwm_set_alarm(0xFFFFFFFFFFFFFF, now_ns);
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timer_mod(&s->timer[i], 0xFFFFFFFFFFFFFF);
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}
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}
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}
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}
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static void sifive_pwm_interrupt(SiFivePwmState *s, int num)
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{
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uint64_t now = sifive_pwm_ns_to_ticks(s,
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qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
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bool was_incrementing = HAS_PWM_EN_BITS(s->pwmcfg);
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trace_sifive_pwm_interrupt(num);
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s->pwmcfg |= R_CONFIG_CMP0IP_MASK << num;
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qemu_irq_raise(s->irqs[num]);
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/*
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* If the zerocmp is set and pwmcmp0 raised the interrupt
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* reset the zero ticks.
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*/
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if ((s->pwmcfg & R_CONFIG_ZEROCMP_MASK) && (num == 0)) {
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/* If reset signal conditions, disable ENONESHOT. */
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s->pwmcfg &= ~R_CONFIG_ENONESHOT_MASK;
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if (was_incrementing) {
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/* If incrementing, time in ticks is when pwmcount is zero */
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s->tick_offset = now;
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} else {
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/* If not incrementing, pwmcount = 0 */
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s->tick_offset = 0;
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}
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}
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/*
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* If carryout bit set, which we discern via looking for overflow,
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* also reset ENONESHOT.
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*/
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if (was_incrementing &&
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((now & PWMCOUNT_MASK) < (s->tick_offset & PWMCOUNT_MASK))) {
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s->pwmcfg &= ~R_CONFIG_ENONESHOT_MASK;
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}
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/* Schedule or disable interrupts */
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sifive_pwm_set_alarms(s);
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/* If was enabled, and now not enabled, switch tick rep */
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if (was_incrementing && !HAS_PWM_EN_BITS(s->pwmcfg)) {
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s->tick_offset = (now - s->tick_offset) & PWMCOUNT_MASK;
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}
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}
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static void sifive_pwm_interrupt_0(void *opaque)
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{
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SiFivePwmState *s = opaque;
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sifive_pwm_interrupt(s, 0);
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}
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static void sifive_pwm_interrupt_1(void *opaque)
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{
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SiFivePwmState *s = opaque;
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sifive_pwm_interrupt(s, 1);
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}
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static void sifive_pwm_interrupt_2(void *opaque)
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{
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SiFivePwmState *s = opaque;
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sifive_pwm_interrupt(s, 2);
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}
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static void sifive_pwm_interrupt_3(void *opaque)
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{
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SiFivePwmState *s = opaque;
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sifive_pwm_interrupt(s, 3);
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}
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static uint64_t sifive_pwm_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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SiFivePwmState *s = opaque;
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uint64_t cur_time, scale;
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uint64_t now = sifive_pwm_ns_to_ticks(s,
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qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
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trace_sifive_pwm_read(addr);
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switch (addr) {
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case A_CONFIG:
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return s->pwmcfg;
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case A_COUNT:
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cur_time = s->tick_offset;
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if (HAS_PWM_EN_BITS(s->pwmcfg)) {
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cur_time = now - cur_time;
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}
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/*
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* Return the value in the counter with bit 31 always 0
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* This is allowed to wrap around so we don't need to check that.
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*/
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return cur_time & PWMCOUNT_MASK;
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case A_PWMS:
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cur_time = s->tick_offset;
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scale = sifive_pwm_compute_scale(s);
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if (HAS_PWM_EN_BITS(s->pwmcfg)) {
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cur_time = now - cur_time;
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}
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return ((cur_time & PWMCOUNT_MASK) >> scale) & PWMCMP_MASK;
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case A_PWMCMP0:
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return s->pwmcmp[0] & PWMCMP_MASK;
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case A_PWMCMP1:
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return s->pwmcmp[1] & PWMCMP_MASK;
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case A_PWMCMP2:
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return s->pwmcmp[2] & PWMCMP_MASK;
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case A_PWMCMP3:
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return s->pwmcmp[3] & PWMCMP_MASK;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
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return 0;
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}
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return 0;
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}
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static void sifive_pwm_write(void *opaque, hwaddr addr,
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uint64_t val64, unsigned int size)
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{
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SiFivePwmState *s = opaque;
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uint32_t value = val64;
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uint64_t new_offset, scale;
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uint64_t now = sifive_pwm_ns_to_ticks(s,
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qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
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trace_sifive_pwm_write(value, addr);
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switch (addr) {
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case A_CONFIG:
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if (value & (R_CONFIG_CMP0CENTER_MASK | R_CONFIG_CMP1CENTER_MASK |
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R_CONFIG_CMP2CENTER_MASK | R_CONFIG_CMP3CENTER_MASK)) {
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qemu_log_mask(LOG_UNIMP, "%s: CMPxCENTER is not supported\n",
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__func__);
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}
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if (value & (R_CONFIG_CMP0GANG_MASK | R_CONFIG_CMP1GANG_MASK |
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R_CONFIG_CMP2GANG_MASK | R_CONFIG_CMP3GANG_MASK)) {
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qemu_log_mask(LOG_UNIMP, "%s: CMPxGANG is not supported\n",
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__func__);
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}
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if (value & (R_CONFIG_CMP0IP_MASK | R_CONFIG_CMP1IP_MASK |
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R_CONFIG_CMP2IP_MASK | R_CONFIG_CMP3IP_MASK)) {
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qemu_log_mask(LOG_UNIMP, "%s: CMPxIP is not supported\n",
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__func__);
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}
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if (!(value & R_CONFIG_CMP0IP_MASK)) {
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qemu_irq_lower(s->irqs[0]);
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}
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if (!(value & R_CONFIG_CMP1IP_MASK)) {
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qemu_irq_lower(s->irqs[1]);
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}
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if (!(value & R_CONFIG_CMP2IP_MASK)) {
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qemu_irq_lower(s->irqs[2]);
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}
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if (!(value & R_CONFIG_CMP3IP_MASK)) {
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qemu_irq_lower(s->irqs[3]);
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}
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/*
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* If this write enables the timer increment
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* set the time when pwmcount was zero to be cur_time - pwmcount.
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* If this write disables the timer increment
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* convert back from pwmcount to the time in ticks
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* when pwmcount was zero.
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*/
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if ((!HAS_PWM_EN_BITS(s->pwmcfg) && HAS_PWM_EN_BITS(value)) ||
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(HAS_PWM_EN_BITS(s->pwmcfg) && !HAS_PWM_EN_BITS(value))) {
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s->tick_offset = (now - s->tick_offset) & PWMCOUNT_MASK;
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}
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s->pwmcfg = value;
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break;
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case A_COUNT:
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/* The guest changed the counter, updated the offset value. */
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new_offset = value;
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if (HAS_PWM_EN_BITS(s->pwmcfg)) {
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new_offset = now - new_offset;
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}
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s->tick_offset = new_offset;
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break;
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case A_PWMS:
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scale = sifive_pwm_compute_scale(s);
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new_offset = (((value & PWMCMP_MASK) << scale) & PWMCOUNT_MASK);
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if (HAS_PWM_EN_BITS(s->pwmcfg)) {
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new_offset = now - new_offset;
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}
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s->tick_offset = new_offset;
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break;
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case A_PWMCMP0:
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s->pwmcmp[0] = value & PWMCMP_MASK;
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break;
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case A_PWMCMP1:
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s->pwmcmp[1] = value & PWMCMP_MASK;
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break;
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case A_PWMCMP2:
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s->pwmcmp[2] = value & PWMCMP_MASK;
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break;
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case A_PWMCMP3:
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s->pwmcmp[3] = value & PWMCMP_MASK;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
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}
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/* Update the alarms to reflect possible updated values */
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sifive_pwm_set_alarms(s);
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}
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static void sifive_pwm_reset(DeviceState *dev)
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{
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SiFivePwmState *s = SIFIVE_PWM(dev);
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uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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s->pwmcfg = 0x00000000;
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s->pwmcmp[0] = 0x00000000;
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s->pwmcmp[1] = 0x00000000;
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s->pwmcmp[2] = 0x00000000;
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s->pwmcmp[3] = 0x00000000;
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s->tick_offset = sifive_pwm_ns_to_ticks(s, now);
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}
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static const MemoryRegionOps sifive_pwm_ops = {
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.read = sifive_pwm_read,
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.write = sifive_pwm_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static const VMStateDescription vmstate_sifive_pwm = {
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.name = TYPE_SIFIVE_PWM,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_TIMER_ARRAY(timer, SiFivePwmState, 4),
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VMSTATE_UINT64(tick_offset, SiFivePwmState),
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VMSTATE_UINT32(pwmcfg, SiFivePwmState),
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VMSTATE_UINT32_ARRAY(pwmcmp, SiFivePwmState, 4),
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VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
|
||||
static Property sifive_pwm_properties[] = {
|
||||
/* 0.5Ghz per spec after FSBL */
|
||||
DEFINE_PROP_UINT64("clock-frequency", struct SiFivePwmState,
|
||||
freq_hz, 500000000ULL),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
||||
static void sifive_pwm_init(Object *obj)
|
||||
{
|
||||
SiFivePwmState *s = SIFIVE_PWM(obj);
|
||||
int i;
|
||||
|
||||
for (i = 0; i < SIFIVE_PWM_IRQS; i++) {
|
||||
sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irqs[i]);
|
||||
}
|
||||
|
||||
memory_region_init_io(&s->mmio, obj, &sifive_pwm_ops, s,
|
||||
TYPE_SIFIVE_PWM, 0x100);
|
||||
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
|
||||
}
|
||||
|
||||
static void sifive_pwm_realize(DeviceState *dev, Error **errp)
|
||||
{
|
||||
SiFivePwmState *s = SIFIVE_PWM(dev);
|
||||
|
||||
timer_init_ns(&s->timer[0], QEMU_CLOCK_VIRTUAL,
|
||||
sifive_pwm_interrupt_0, s);
|
||||
|
||||
timer_init_ns(&s->timer[1], QEMU_CLOCK_VIRTUAL,
|
||||
sifive_pwm_interrupt_1, s);
|
||||
|
||||
timer_init_ns(&s->timer[2], QEMU_CLOCK_VIRTUAL,
|
||||
sifive_pwm_interrupt_2, s);
|
||||
|
||||
timer_init_ns(&s->timer[3], QEMU_CLOCK_VIRTUAL,
|
||||
sifive_pwm_interrupt_3, s);
|
||||
}
|
||||
|
||||
static void sifive_pwm_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
|
||||
dc->reset = sifive_pwm_reset;
|
||||
device_class_set_props(dc, sifive_pwm_properties);
|
||||
dc->vmsd = &vmstate_sifive_pwm;
|
||||
dc->realize = sifive_pwm_realize;
|
||||
}
|
||||
|
||||
static const TypeInfo sifive_pwm_info = {
|
||||
.name = TYPE_SIFIVE_PWM,
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(SiFivePwmState),
|
||||
.instance_init = sifive_pwm_init,
|
||||
.class_init = sifive_pwm_class_init,
|
||||
};
|
||||
|
||||
static void sifive_pwm_register_types(void)
|
||||
{
|
||||
type_register_static(&sifive_pwm_info);
|
||||
}
|
||||
|
||||
type_init(sifive_pwm_register_types)
|
||||
@ -88,3 +88,9 @@ sse_counter_reset(void) "SSE system counter: reset"
|
||||
sse_timer_read(uint64_t offset, uint64_t data, unsigned size) "SSE system timer read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
|
||||
sse_timer_write(uint64_t offset, uint64_t data, unsigned size) "SSE system timer write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
|
||||
sse_timer_reset(void) "SSE system timer: reset"
|
||||
|
||||
# sifive_pwm.c
|
||||
sifive_pwm_set_alarm(uint64_t alarm, uint64_t now) "Setting alarm to: 0x%" PRIx64 ", now: 0x%" PRIx64
|
||||
sifive_pwm_interrupt(int num) "Interrupt %d"
|
||||
sifive_pwm_read(uint64_t offset) "Read at address: 0x%" PRIx64
|
||||
sifive_pwm_write(uint64_t data, uint64_t offset) "Write 0x%" PRIx64 " at address: 0x%" PRIx64
|
||||
|
||||
62
include/hw/timer/sifive_pwm.h
Normal file
62
include/hw/timer/sifive_pwm.h
Normal file
@ -0,0 +1,62 @@
|
||||
/*
|
||||
* SiFive PWM
|
||||
*
|
||||
* Copyright (c) 2020 Western Digital
|
||||
*
|
||||
* Author: Alistair Francis <alistair.francis@wdc.com>
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef HW_SIFIVE_PWM_H
|
||||
#define HW_SIFIVE_PWM_H
|
||||
|
||||
#include "hw/sysbus.h"
|
||||
#include "qemu/timer.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
#define TYPE_SIFIVE_PWM "sifive-pwm"
|
||||
|
||||
#define SIFIVE_PWM(obj) \
|
||||
OBJECT_CHECK(SiFivePwmState, (obj), TYPE_SIFIVE_PWM)
|
||||
|
||||
#define SIFIVE_PWM_CHANS 4
|
||||
#define SIFIVE_PWM_IRQS SIFIVE_PWM_CHANS
|
||||
|
||||
typedef struct SiFivePwmState {
|
||||
/* <private> */
|
||||
SysBusDevice parent_obj;
|
||||
|
||||
/* <public> */
|
||||
MemoryRegion mmio;
|
||||
QEMUTimer timer[SIFIVE_PWM_CHANS];
|
||||
/*
|
||||
* if en bit(s) set, is the number of ticks when pwmcount was 0
|
||||
* if en bit(s) not set, is the number of ticks in pwmcount
|
||||
*/
|
||||
uint64_t tick_offset;
|
||||
uint64_t freq_hz;
|
||||
|
||||
uint32_t pwmcfg;
|
||||
uint32_t pwmcmp[SIFIVE_PWM_CHANS];
|
||||
|
||||
qemu_irq irqs[SIFIVE_PWM_IRQS];
|
||||
} SiFivePwmState;
|
||||
|
||||
#endif /* HW_SIFIVE_PWM_H */
|
||||
Loading…
Reference in New Issue
Block a user