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tcg/tci: Implement the disassembler properly
Actually print arguments as opposed to simply the opcodes and, uselessly, the argument counts. Reuse all of the helpers developed as part of the interpreter. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
65f1b6cc9a
commit
59964b4f98
61
disas/tci.c
61
disas/tci.c
@ -1,61 +0,0 @@
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/*
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* Tiny Code Interpreter for QEMU - disassembler
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*
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* Copyright (c) 2011 Stefan Weil
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "disas/dis-asm.h"
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#include "tcg/tcg.h"
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/* Disassemble TCI bytecode. */
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int print_insn_tci(bfd_vma addr, disassemble_info *info)
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{
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int length;
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uint8_t byte;
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int status;
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TCGOpcode op;
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status = info->read_memory_func(addr, &byte, 1, info);
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if (status != 0) {
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info->memory_error_func(status, addr, info);
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return -1;
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}
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op = byte;
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addr++;
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status = info->read_memory_func(addr, &byte, 1, info);
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if (status != 0) {
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info->memory_error_func(status, addr, info);
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return -1;
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}
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length = byte;
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if (op >= tcg_op_defs_max) {
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info->fprintf_func(info->stream, "illegal opcode %d", op);
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} else {
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const TCGOpDef *def = &tcg_op_defs[op];
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int nb_oargs = def->nb_oargs;
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int nb_iargs = def->nb_iargs;
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int nb_cargs = def->nb_cargs;
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/* TODO: Improve disassembler output. */
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info->fprintf_func(info->stream, "%s\to=%d i=%d c=%d",
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def->name, nb_oargs, nb_iargs, nb_cargs);
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}
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return length;
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}
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@ -278,10 +278,8 @@ DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT)
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#ifdef TCG_TARGET_INTERPRETER
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/* These opcodes are only for use between the tci generator and interpreter. */
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DEF(tci_movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT)
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#if TCG_TARGET_REG_BITS == 64
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DEF(tci_movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT)
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#endif
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#endif
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#undef TLADDR_ARGS
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#undef DATA64_ARGS
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@ -1943,7 +1943,7 @@ specific_ss.add(when: 'CONFIG_TCG', if_true: files(
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'tcg/tcg-op.c',
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'tcg/tcg.c',
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))
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specific_ss.add(when: 'CONFIG_TCG_INTERPRETER', if_true: files('disas/tci.c', 'tcg/tci.c'))
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specific_ss.add(when: 'CONFIG_TCG_INTERPRETER', if_true: files('tcg/tci.c'))
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subdir('backends')
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subdir('disas')
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283
tcg/tci.c
283
tcg/tci.c
@ -1061,3 +1061,286 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
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}
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}
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}
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/*
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* Disassembler that matches the interpreter
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*/
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static const char *str_r(TCGReg r)
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{
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static const char regs[TCG_TARGET_NB_REGS][4] = {
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13", "env", "sp"
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};
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QEMU_BUILD_BUG_ON(TCG_AREG0 != TCG_REG_R14);
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QEMU_BUILD_BUG_ON(TCG_REG_CALL_STACK != TCG_REG_R15);
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assert((unsigned)r < TCG_TARGET_NB_REGS);
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return regs[r];
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}
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static const char *str_c(TCGCond c)
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{
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static const char cond[16][8] = {
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[TCG_COND_NEVER] = "never",
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[TCG_COND_ALWAYS] = "always",
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[TCG_COND_EQ] = "eq",
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[TCG_COND_NE] = "ne",
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[TCG_COND_LT] = "lt",
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[TCG_COND_GE] = "ge",
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[TCG_COND_LE] = "le",
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[TCG_COND_GT] = "gt",
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[TCG_COND_LTU] = "ltu",
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[TCG_COND_GEU] = "geu",
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[TCG_COND_LEU] = "leu",
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[TCG_COND_GTU] = "gtu",
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};
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assert((unsigned)c < ARRAY_SIZE(cond));
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assert(cond[c][0] != 0);
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return cond[c];
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}
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/* Disassemble TCI bytecode. */
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int print_insn_tci(bfd_vma addr, disassemble_info *info)
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{
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uint8_t buf[256];
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int length, status;
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const TCGOpDef *def;
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const char *op_name;
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TCGOpcode op;
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TCGReg r0, r1, r2, r3;
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#if TCG_TARGET_REG_BITS == 32
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TCGReg r4, r5;
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#endif
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tcg_target_ulong i1;
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int32_t s2;
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TCGCond c;
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TCGMemOpIdx oi;
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uint8_t pos, len;
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void *ptr;
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const uint8_t *tb_ptr;
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status = info->read_memory_func(addr, buf, 2, info);
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if (status != 0) {
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info->memory_error_func(status, addr, info);
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return -1;
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}
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op = buf[0];
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length = buf[1];
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if (length < 2) {
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info->fprintf_func(info->stream, "invalid length %d", length);
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return 1;
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}
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status = info->read_memory_func(addr + 2, buf + 2, length - 2, info);
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if (status != 0) {
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info->memory_error_func(status, addr + 2, info);
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return -1;
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}
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def = &tcg_op_defs[op];
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op_name = def->name;
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tb_ptr = buf + 2;
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switch (op) {
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case INDEX_op_br:
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case INDEX_op_call:
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case INDEX_op_exit_tb:
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case INDEX_op_goto_tb:
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tci_args_l(&tb_ptr, &ptr);
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info->fprintf_func(info->stream, "%-12s %p", op_name, ptr);
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break;
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case INDEX_op_brcond_i32:
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case INDEX_op_brcond_i64:
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tci_args_rrcl(&tb_ptr, &r0, &r1, &c, &ptr);
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info->fprintf_func(info->stream, "%-12s %s, %s, %s, %p",
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op_name, str_r(r0), str_r(r1), str_c(c), ptr);
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break;
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case INDEX_op_setcond_i32:
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case INDEX_op_setcond_i64:
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tci_args_rrrc(&tb_ptr, &r0, &r1, &r2, &c);
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info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s",
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op_name, str_r(r0), str_r(r1), str_r(r2), str_c(c));
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break;
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case INDEX_op_tci_movi_i32:
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tci_args_ri(&tb_ptr, &r0, &i1);
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info->fprintf_func(info->stream, "%-12s %s, 0x%" TCG_PRIlx,
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op_name, str_r(r0), i1);
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break;
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#if TCG_TARGET_REG_BITS == 64
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case INDEX_op_tci_movi_i64:
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tci_args_rI(&tb_ptr, &r0, &i1);
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info->fprintf_func(info->stream, "%-12s %s, 0x%" TCG_PRIlx,
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op_name, str_r(r0), i1);
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break;
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#endif
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case INDEX_op_ld8u_i32:
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case INDEX_op_ld8u_i64:
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case INDEX_op_ld8s_i32:
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case INDEX_op_ld8s_i64:
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case INDEX_op_ld16u_i32:
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case INDEX_op_ld16u_i64:
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case INDEX_op_ld16s_i32:
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case INDEX_op_ld16s_i64:
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case INDEX_op_ld32u_i64:
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case INDEX_op_ld32s_i64:
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case INDEX_op_ld_i32:
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case INDEX_op_ld_i64:
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case INDEX_op_st8_i32:
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case INDEX_op_st8_i64:
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case INDEX_op_st16_i32:
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case INDEX_op_st16_i64:
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case INDEX_op_st32_i64:
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case INDEX_op_st_i32:
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case INDEX_op_st_i64:
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tci_args_rrs(&tb_ptr, &r0, &r1, &s2);
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info->fprintf_func(info->stream, "%-12s %s, %s, %d",
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op_name, str_r(r0), str_r(r1), s2);
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break;
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case INDEX_op_mov_i32:
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case INDEX_op_mov_i64:
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case INDEX_op_ext8s_i32:
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case INDEX_op_ext8s_i64:
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case INDEX_op_ext8u_i32:
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case INDEX_op_ext8u_i64:
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case INDEX_op_ext16s_i32:
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case INDEX_op_ext16s_i64:
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case INDEX_op_ext16u_i32:
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case INDEX_op_ext32s_i64:
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case INDEX_op_ext32u_i64:
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case INDEX_op_ext_i32_i64:
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case INDEX_op_extu_i32_i64:
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case INDEX_op_bswap16_i32:
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case INDEX_op_bswap16_i64:
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case INDEX_op_bswap32_i32:
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case INDEX_op_bswap32_i64:
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case INDEX_op_bswap64_i64:
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case INDEX_op_not_i32:
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case INDEX_op_not_i64:
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case INDEX_op_neg_i32:
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case INDEX_op_neg_i64:
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tci_args_rr(&tb_ptr, &r0, &r1);
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info->fprintf_func(info->stream, "%-12s %s, %s",
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op_name, str_r(r0), str_r(r1));
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break;
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case INDEX_op_add_i32:
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case INDEX_op_add_i64:
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case INDEX_op_sub_i32:
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case INDEX_op_sub_i64:
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case INDEX_op_mul_i32:
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case INDEX_op_mul_i64:
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case INDEX_op_and_i32:
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case INDEX_op_and_i64:
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case INDEX_op_or_i32:
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case INDEX_op_or_i64:
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case INDEX_op_xor_i32:
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case INDEX_op_xor_i64:
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case INDEX_op_div_i32:
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case INDEX_op_div_i64:
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case INDEX_op_rem_i32:
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case INDEX_op_rem_i64:
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case INDEX_op_divu_i32:
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case INDEX_op_divu_i64:
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case INDEX_op_remu_i32:
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case INDEX_op_remu_i64:
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case INDEX_op_shl_i32:
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case INDEX_op_shl_i64:
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case INDEX_op_shr_i32:
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case INDEX_op_shr_i64:
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case INDEX_op_sar_i32:
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case INDEX_op_sar_i64:
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case INDEX_op_rotl_i32:
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case INDEX_op_rotl_i64:
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case INDEX_op_rotr_i32:
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case INDEX_op_rotr_i64:
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tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
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info->fprintf_func(info->stream, "%-12s %s, %s, %s",
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op_name, str_r(r0), str_r(r1), str_r(r2));
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break;
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case INDEX_op_deposit_i32:
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case INDEX_op_deposit_i64:
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tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len);
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info->fprintf_func(info->stream, "%-12s %s, %s, %s, %d, %d",
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op_name, str_r(r0), str_r(r1), str_r(r2), pos, len);
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break;
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#if TCG_TARGET_REG_BITS == 32
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case INDEX_op_setcond2_i32:
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tci_args_rrrrrc(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &c);
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info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s, %s",
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op_name, str_r(r0), str_r(r1), str_r(r2),
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str_r(r3), str_r(r4), str_c(c));
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break;
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case INDEX_op_brcond2_i32:
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tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &c, &ptr);
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info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s, %p",
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op_name, str_r(r0), str_r(r1),
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str_r(r2), str_r(r3), str_c(c), ptr);
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break;
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case INDEX_op_mulu2_i32:
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tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3);
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info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s",
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op_name, str_r(r0), str_r(r1),
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str_r(r2), str_r(r3));
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break;
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case INDEX_op_add2_i32:
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case INDEX_op_sub2_i32:
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tci_args_rrrrrr(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &r5);
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info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s, %s",
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op_name, str_r(r0), str_r(r1), str_r(r2),
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str_r(r3), str_r(r4), str_r(r5));
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break;
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#endif
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case INDEX_op_qemu_ld_i64:
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case INDEX_op_qemu_st_i64:
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len = DIV_ROUND_UP(64, TCG_TARGET_REG_BITS);
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goto do_qemu_ldst;
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case INDEX_op_qemu_ld_i32:
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case INDEX_op_qemu_st_i32:
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len = 1;
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do_qemu_ldst:
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len += DIV_ROUND_UP(TARGET_LONG_BITS, TCG_TARGET_REG_BITS);
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switch (len) {
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case 2:
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tci_args_rrm(&tb_ptr, &r0, &r1, &oi);
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info->fprintf_func(info->stream, "%-12s %s, %s, %x",
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op_name, str_r(r0), str_r(r1), oi);
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break;
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case 3:
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tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi);
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info->fprintf_func(info->stream, "%-12s %s, %s, %s, %x",
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op_name, str_r(r0), str_r(r1), str_r(r2), oi);
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break;
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case 4:
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tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi);
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info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %x",
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op_name, str_r(r0), str_r(r1),
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str_r(r2), str_r(r3), oi);
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break;
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default:
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g_assert_not_reached();
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}
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break;
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default:
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info->fprintf_func(info->stream, "illegal opcode %d", op);
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break;
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}
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return length;
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}
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