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target/riscv: Move leaf pte processing out of level loop
Move the code that never loops outside of the loop. Unchain the if-return-else statements. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230325105429.1142530-21-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-21-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Richard Henderson
Alistair Francis
parent
8d6a00cdc0
commit
59688aa023
@ -865,6 +865,8 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
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}
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int ptshift = (levels - 1) * ptidxbits;
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target_ulong pte;
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hwaddr pte_addr;
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int i;
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#if !TCG_OVERSIZED_GUEST
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@ -881,7 +883,6 @@ restart:
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}
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/* check that physical address of PTE is legal */
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hwaddr pte_addr;
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if (two_stage && first_stage) {
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int vbase_prot;
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@ -913,7 +914,6 @@ restart:
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return TRANSLATE_PMP_FAIL;
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}
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target_ulong pte;
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if (riscv_cpu_mxl(env) == MXL_RV32) {
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pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
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} else {
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@ -938,128 +938,140 @@ restart:
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if (!(pte & PTE_V)) {
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/* Invalid PTE */
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return TRANSLATE_FAIL;
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} else if (!pbmte && (pte & PTE_PBMT)) {
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}
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if (pte & (PTE_R | PTE_W | PTE_X)) {
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goto leaf;
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}
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/* Inner PTE, continue walking */
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if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) {
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return TRANSLATE_FAIL;
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} else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
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/* Inner PTE, continue walking */
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if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) {
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return TRANSLATE_FAIL;
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}
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base = ppn << PGSHIFT;
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} else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
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/* Reserved leaf PTE flags: PTE_W */
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return TRANSLATE_FAIL;
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} else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) {
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/* Reserved leaf PTE flags: PTE_W + PTE_X */
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return TRANSLATE_FAIL;
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} else if ((pte & PTE_U) && ((mode != PRV_U) &&
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(!sum || access_type == MMU_INST_FETCH))) {
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/* User PTE flags when not U mode and mstatus.SUM is not set,
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or the access type is an instruction fetch */
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return TRANSLATE_FAIL;
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} else if (!(pte & PTE_U) && (mode != PRV_S)) {
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/* Supervisor PTE flags when not S mode */
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return TRANSLATE_FAIL;
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} else if (ppn & ((1ULL << ptshift) - 1)) {
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/* Misaligned PPN */
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return TRANSLATE_FAIL;
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} else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) ||
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((pte & PTE_X) && mxr))) {
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/* Read access check failed */
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return TRANSLATE_FAIL;
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} else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) {
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/* Write access check failed */
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return TRANSLATE_FAIL;
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} else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) {
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/* Fetch access check failed */
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return TRANSLATE_FAIL;
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} else {
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/* if necessary, set accessed and dirty bits. */
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target_ulong updated_pte = pte | PTE_A |
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}
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base = ppn << PGSHIFT;
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}
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/* No leaf pte at any translation level. */
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return TRANSLATE_FAIL;
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leaf:
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if (ppn & ((1ULL << ptshift) - 1)) {
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/* Misaligned PPN */
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return TRANSLATE_FAIL;
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}
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if (!pbmte && (pte & PTE_PBMT)) {
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/* Reserved without Svpbmt. */
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return TRANSLATE_FAIL;
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}
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if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
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/* Reserved leaf PTE flags: PTE_W */
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return TRANSLATE_FAIL;
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}
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if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) {
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/* Reserved leaf PTE flags: PTE_W + PTE_X */
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return TRANSLATE_FAIL;
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}
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if ((pte & PTE_U) &&
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((mode != PRV_U) && (!sum || access_type == MMU_INST_FETCH))) {
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/*
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* User PTE flags when not U mode and mstatus.SUM is not set,
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* or the access type is an instruction fetch.
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*/
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return TRANSLATE_FAIL;
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}
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if (!(pte & PTE_U) && (mode != PRV_S)) {
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/* Supervisor PTE flags when not S mode */
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return TRANSLATE_FAIL;
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}
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if (access_type == MMU_DATA_LOAD &&
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!((pte & PTE_R) || ((pte & PTE_X) && mxr))) {
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/* Read access check failed */
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return TRANSLATE_FAIL;
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}
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if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) {
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/* Write access check failed */
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return TRANSLATE_FAIL;
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}
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if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) {
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/* Fetch access check failed */
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return TRANSLATE_FAIL;
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}
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/* If necessary, set accessed and dirty bits. */
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target_ulong updated_pte = pte | PTE_A |
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(access_type == MMU_DATA_STORE ? PTE_D : 0);
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/* Page table updates need to be atomic with MTTCG enabled */
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if (updated_pte != pte) {
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if (!hade) {
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return TRANSLATE_FAIL;
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}
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/* Page table updates need to be atomic with MTTCG enabled */
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if (updated_pte != pte) {
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if (!hade) {
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return TRANSLATE_FAIL;
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}
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/*
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* - if accessed or dirty bits need updating, and the PTE is
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* in RAM, then we do so atomically with a compare and swap.
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* - if the PTE is in IO space or ROM, then it can't be updated
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* and we return TRANSLATE_FAIL.
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* - if the PTE changed by the time we went to update it, then
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* it is no longer valid and we must re-walk the page table.
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*/
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MemoryRegion *mr;
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hwaddr l = sizeof(target_ulong), addr1;
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mr = address_space_translate(cs->as, pte_addr, &addr1, &l,
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false, MEMTXATTRS_UNSPECIFIED);
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if (memory_region_is_ram(mr)) {
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target_ulong *pte_pa =
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qemu_map_ram_ptr(mr->ram_block, addr1);
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/*
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* - if accessed or dirty bits need updating, and the PTE is
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* in RAM, then we do so atomically with a compare and swap.
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* - if the PTE is in IO space or ROM, then it can't be updated
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* and we return TRANSLATE_FAIL.
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* - if the PTE changed by the time we went to update it, then
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* it is no longer valid and we must re-walk the page table.
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*/
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MemoryRegion *mr;
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hwaddr l = sizeof(target_ulong), addr1;
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mr = address_space_translate(cs->as, pte_addr, &addr1, &l,
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false, MEMTXATTRS_UNSPECIFIED);
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if (memory_region_is_ram(mr)) {
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target_ulong *pte_pa = qemu_map_ram_ptr(mr->ram_block, addr1);
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#if TCG_OVERSIZED_GUEST
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/*
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* MTTCG is not enabled on oversized TCG guests so
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* page table updates do not need to be atomic
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*/
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*pte_pa = pte = updated_pte;
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/*
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* MTTCG is not enabled on oversized TCG guests so
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* page table updates do not need to be atomic
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*/
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*pte_pa = pte = updated_pte;
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#else
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target_ulong old_pte =
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qatomic_cmpxchg(pte_pa, pte, updated_pte);
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if (old_pte != pte) {
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goto restart;
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} else {
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pte = updated_pte;
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}
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target_ulong old_pte = qatomic_cmpxchg(pte_pa, pte, updated_pte);
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if (old_pte != pte) {
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goto restart;
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}
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pte = updated_pte;
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#endif
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} else {
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/*
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* misconfigured PTE in ROM (AD bits are not preset) or
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* PTE is in IO space and can't be updated atomically
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*/
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return TRANSLATE_FAIL;
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}
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}
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} else {
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/*
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* for superpage mappings, make a fake leaf PTE for the TLB's
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* benefit.
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* Misconfigured PTE in ROM (AD bits are not preset) or
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* PTE is in IO space and can't be updated atomically.
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*/
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target_ulong vpn = addr >> PGSHIFT;
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if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) {
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napot_bits = ctzl(ppn) + 1;
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if ((i != (levels - 1)) || (napot_bits != 4)) {
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return TRANSLATE_FAIL;
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}
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}
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napot_mask = (1 << napot_bits) - 1;
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*physical = (((ppn & ~napot_mask) | (vpn & napot_mask) |
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(vpn & (((target_ulong)1 << ptshift) - 1))
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) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK);
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/* set permissions on the TLB entry */
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if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
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*prot |= PAGE_READ;
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}
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if (pte & PTE_X) {
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*prot |= PAGE_EXEC;
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}
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/*
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* add write permission on stores or if the page is already dirty,
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* so that we TLB miss on later writes to update the dirty bit
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*/
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if ((pte & PTE_W) &&
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(access_type == MMU_DATA_STORE || (pte & PTE_D))) {
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*prot |= PAGE_WRITE;
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}
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return TRANSLATE_SUCCESS;
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return TRANSLATE_FAIL;
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}
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}
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return TRANSLATE_FAIL;
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/* For superpage mappings, make a fake leaf PTE for the TLB's benefit. */
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target_ulong vpn = addr >> PGSHIFT;
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if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) {
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napot_bits = ctzl(ppn) + 1;
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if ((i != (levels - 1)) || (napot_bits != 4)) {
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return TRANSLATE_FAIL;
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}
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}
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napot_mask = (1 << napot_bits) - 1;
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*physical = (((ppn & ~napot_mask) | (vpn & napot_mask) |
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(vpn & (((target_ulong)1 << ptshift) - 1))
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) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK);
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/* set permissions on the TLB entry */
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if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
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*prot |= PAGE_READ;
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}
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if (pte & PTE_X) {
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*prot |= PAGE_EXEC;
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}
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/*
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* Add write permission on stores or if the page is already dirty,
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* so that we TLB miss on later writes to update the dirty bit.
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*/
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if ((pte & PTE_W) && (access_type == MMU_DATA_STORE || (pte & PTE_D))) {
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*prot |= PAGE_WRITE;
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}
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return TRANSLATE_SUCCESS;
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}
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static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
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