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ppc4xx: Add device models found in PPC440 core SoCs
These devices are found in newer SoCs based on 440 core e.g. the 460EX (http://www.embeddeddeveloper.com/assets/processors/amcc/datasheets/ PP460EX_DS2063.pdf) Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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26
hw/ppc/ppc440.h
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26
hw/ppc/ppc440.h
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@ -0,0 +1,26 @@
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/*
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* QEMU PowerPC 440 shared definitions
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*
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* Copyright (c) 2012 François Revol
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* Copyright (c) 2016-2018 BALATON Zoltan
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*
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* This work is licensed under the GNU GPL license version 2 or later.
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*
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*/
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#ifndef PPC440_H
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#define PPC440_H
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#include "hw/ppc/ppc.h"
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void ppc4xx_l2sram_init(CPUPPCState *env);
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void ppc4xx_cpr_init(CPUPPCState *env);
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void ppc4xx_sdr_init(CPUPPCState *env);
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void ppc440_sdram_init(CPUPPCState *env, int nbanks,
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MemoryRegion *ram_memories,
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hwaddr *ram_bases, hwaddr *ram_sizes,
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int do_init);
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void ppc4xx_ahb_init(CPUPPCState *env);
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void ppc460ex_pcie_init(CPUPPCState *env);
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#endif /* PPC440_H */
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1159
hw/ppc/ppc440_uc.c
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1159
hw/ppc/ppc440_uc.c
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File diff suppressed because it is too large
Load Diff
@ -65,7 +65,7 @@ void pcie_host_mmcfg_update(PCIExpressHost *e,
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* bit 12 - 14: function number
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* bit 0 - 11: offset in configuration space of a given device
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*/
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#define PCIE_MMCFG_SIZE_MAX (1ULL << 28)
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#define PCIE_MMCFG_SIZE_MAX (1ULL << 29)
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#define PCIE_MMCFG_SIZE_MIN (1ULL << 20)
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#define PCIE_MMCFG_BUS_BIT 20
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#define PCIE_MMCFG_BUS_MASK 0x1ff
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