mirror of
https://github.com/qemu/qemu.git
synced 2024-11-28 14:24:02 +08:00
MIPS Malta system and devices support, by Aurelien Jarno and Stefan Weil.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2319 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths
parent
fde7d5bd73
commit
5856de800d
@ -361,8 +361,10 @@ VL_OBJS+= grackle_pci.o prep_pci.o unin_pci.o
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CPPFLAGS += -DHAS_AUDIO
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endif
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ifeq ($(TARGET_ARCH), mips)
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VL_OBJS+= mips_r4k.o mips_timer.o dma.o vga.o serial.o i8254.o i8259.o ide.o
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VL_OBJS+= mc146818rtc.o #pckbd.o fdc.o m48t59.o
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VL_OBJS+= mips_r4k.o mips_malta.o mips_timer.o dma.o vga.o serial.o i8254.o i8259.o
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VL_OBJS+= ide.o gt64xxx.o pckbd.o ps2.o fdc.o mc146818rtc.o usb-uhci.o acpi.o
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VL_OBJS+= piix_pci.o parallel.o mixeng.o cirrus_vga.o $(SOUND_HW) $(AUDIODRV)
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DEFINES += -DHAS_AUDIO
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endif
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ifeq ($(TARGET_BASE_ARCH), sparc)
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ifeq ($(TARGET_ARCH), sparc64)
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590
hw/mips_malta.c
Normal file
590
hw/mips_malta.c
Normal file
@ -0,0 +1,590 @@
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/*
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* QEMU Malta board support
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*
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* Copyright (c) 2006 Aurelien Jarno
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h"
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#define BIOS_FILENAME "mips_bios.bin"
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#ifdef MIPS_HAS_MIPS64
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#define INITRD_LOAD_ADDR (uint64_t)0x80800000
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#define ENVP_ADDR (uint64_t)0x80002000
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#else
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#define INITRD_LOAD_ADDR (uint32_t)0x80800000
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#define ENVP_ADDR (uint32_t)0x80002000
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#endif
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#define VIRT_TO_PHYS_ADDEND (-((uint64_t)(uint32_t)0x80000000))
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#define ENVP_NB_ENTRIES 16
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#define ENVP_ENTRY_SIZE 256
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extern FILE *logfile;
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typedef struct {
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uint32_t leds;
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uint32_t brk;
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uint32_t gpout;
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uint32_t i2coe;
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uint32_t i2cout;
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uint32_t i2csel;
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CharDriverState *display;
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char display_text[9];
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} MaltaFPGAState;
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static PITState *pit;
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static void pic_irq_request(void *opaque, int level)
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{
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CPUState *env = first_cpu;
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if (level) {
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env->CP0_Cause |= 0x00000400;
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cpu_interrupt(env, CPU_INTERRUPT_HARD);
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} else {
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env->CP0_Cause &= ~0x00000400;
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
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}
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}
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/* Malta FPGA */
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static void malta_fpga_update_display(void *opaque)
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{
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char leds_text[9];
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int i;
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MaltaFPGAState *s = opaque;
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for (i = 7 ; i >= 0 ; i--) {
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if (s->leds & (1 << i))
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leds_text[i] = '#';
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else
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leds_text[i] = ' ';
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}
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leds_text[8] = '\0';
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qemu_chr_printf(s->display, "\e[H\n\n|\e[31m%-8.8s\e[00m|\r\n", leds_text);
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qemu_chr_printf(s->display, "\n\n\n\n|\e[32m%-8.8s\e[00m|", s->display_text);
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}
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static uint32_t malta_fpga_readl(void *opaque, target_phys_addr_t addr)
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{
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MaltaFPGAState *s = opaque;
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uint32_t val = 0;
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uint32_t saddr;
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saddr = (addr & 0xfffff);
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switch (saddr) {
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/* SWITCH Register */
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case 0x00200:
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val = 0x00000000; /* All switches closed */
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break;
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/* STATUS Register */
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case 0x00208:
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#ifdef TARGET_WORDS_BIGENDIAN
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val = 0x00000012;
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#else
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val = 0x00000010;
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#endif
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break;
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/* JMPRS Register */
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case 0x00210:
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val = 0x00;
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break;
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/* LEDBAR Register */
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case 0x00408:
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val = s->leds;
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break;
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/* BRKRES Register */
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case 0x00508:
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val = s->brk;
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break;
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/* GPOUT Register */
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case 0x00a00:
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val = s->gpout;
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break;
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/* XXX: implement a real I2C controller */
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/* GPINP Register */
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case 0x00a08:
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/* IN = OUT until a real I2C control is implemented */
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if (s->i2csel)
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val = s->i2cout;
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else
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val = 0x00;
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break;
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/* I2CINP Register */
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case 0x00b00:
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val = 0x00000003;
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break;
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/* I2COE Register */
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case 0x00b08:
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val = s->i2coe;
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break;
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/* I2COUT Register */
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case 0x00b10:
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val = s->i2cout;
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break;
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/* I2CSEL Register */
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case 0x00b18:
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val = s->i2cout;
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break;
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default:
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#if 0
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printf ("malta_fpga_read: Bad register offset 0x%x\n", (int)addr);
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#endif
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break;
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}
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return val;
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}
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static void malta_fpga_writel(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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MaltaFPGAState *s = opaque;
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uint32_t saddr;
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saddr = (addr & 0xfffff);
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switch (saddr) {
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/* SWITCH Register */
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case 0x00200:
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break;
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/* JMPRS Register */
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case 0x00210:
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break;
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/* LEDBAR Register */
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/* XXX: implement a 8-LED array */
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case 0x00408:
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s->leds = val & 0xff;
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break;
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/* ASCIIWORD Register */
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case 0x00410:
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snprintf(s->display_text, 9, "%08X", val);
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malta_fpga_update_display(s);
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break;
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/* ASCIIPOS0 to ASCIIPOS7 Registers */
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case 0x00418:
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case 0x00420:
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case 0x00428:
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case 0x00430:
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case 0x00438:
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case 0x00440:
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case 0x00448:
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case 0x00450:
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s->display_text[(saddr - 0x00418) >> 3] = (char) val;
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malta_fpga_update_display(s);
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break;
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/* SOFTRES Register */
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case 0x00500:
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if (val == 0x42)
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qemu_system_reset_request ();
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break;
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/* BRKRES Register */
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case 0x00508:
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s->brk = val & 0xff;
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break;
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/* GPOUT Register */
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case 0x00a00:
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s->gpout = val & 0xff;
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break;
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/* I2COE Register */
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case 0x00b08:
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s->i2coe = val & 0x03;
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break;
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/* I2COUT Register */
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case 0x00b10:
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s->i2cout = val & 0x03;
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break;
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/* I2CSEL Register */
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case 0x00b18:
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s->i2cout = val & 0x01;
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break;
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default:
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#if 0
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printf ("malta_fpga_write: Bad register offset 0x%x\n", (int)addr);
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#endif
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break;
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}
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}
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static CPUReadMemoryFunc *malta_fpga_read[] = {
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malta_fpga_readl,
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malta_fpga_readl,
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malta_fpga_readl
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};
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static CPUWriteMemoryFunc *malta_fpga_write[] = {
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malta_fpga_writel,
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malta_fpga_writel,
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malta_fpga_writel
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};
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void malta_fpga_reset(void *opaque)
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{
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MaltaFPGAState *s = opaque;
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s->leds = 0x00;
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s->brk = 0x0a;
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s->gpout = 0x00;
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s->i2coe = 0x0;
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s->i2cout = 0x3;
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s->i2csel = 0x1;
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s->display_text[8] = '\0';
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snprintf(s->display_text, 9, " ");
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malta_fpga_update_display(s);
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}
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MaltaFPGAState *malta_fpga_init(target_phys_addr_t base)
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{
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MaltaFPGAState *s;
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int malta;
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s = (MaltaFPGAState *)qemu_mallocz(sizeof(MaltaFPGAState));
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malta = cpu_register_io_memory(0, malta_fpga_read,
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malta_fpga_write, s);
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cpu_register_physical_memory(base, 0x100000, malta);
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s->display = qemu_chr_open("vc");
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qemu_chr_printf(s->display, "\e[HMalta LEBDAR\r\n");
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qemu_chr_printf(s->display, "+--------+\r\n");
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qemu_chr_printf(s->display, "+ +\r\n");
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qemu_chr_printf(s->display, "+--------+\r\n");
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qemu_chr_printf(s->display, "\n");
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qemu_chr_printf(s->display, "Malta ASCII\r\n");
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qemu_chr_printf(s->display, "+--------+\r\n");
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qemu_chr_printf(s->display, "+ +\r\n");
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qemu_chr_printf(s->display, "+--------+\r\n");
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malta_fpga_reset(s);
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qemu_register_reset(malta_fpga_reset, s);
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return s;
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}
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/* Audio support */
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#ifdef HAS_AUDIO
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static void audio_init (PCIBus *pci_bus)
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{
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struct soundhw *c;
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int audio_enabled = 0;
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for (c = soundhw; !audio_enabled && c->name; ++c) {
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audio_enabled = c->enabled;
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}
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if (audio_enabled) {
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AudioState *s;
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s = AUD_init ();
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if (s) {
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for (c = soundhw; c->name; ++c) {
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if (c->enabled) {
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if (c->isa) {
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fprintf(stderr, "qemu: Unsupported Sound Card: %s\n", c->name);
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exit(1);
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}
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else {
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if (pci_bus) {
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c->init.init_pci (pci_bus, s);
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}
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}
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}
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}
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}
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}
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}
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#endif
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/* Network support */
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static void network_init (PCIBus *pci_bus)
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{
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int i;
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NICInfo *nd;
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for(i = 0; i < nb_nics; i++) {
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nd = &nd_table[i];
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if (!nd->model) {
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nd->model = "pcnet";
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}
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if (i == 0 && strcmp(nd->model, "pcnet") == 0) {
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/* The malta board has a PCNet card using PCI SLOT 11 */
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pci_nic_init(pci_bus, nd, 88);
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} else {
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pci_nic_init(pci_bus, nd, -1);
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}
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}
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}
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/* ROM and pseudo bootloader
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The following code implements a very very simple bootloader. It first
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loads the registers a0 to a3 to the values expected by the OS, and
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then jump at the kernel address.
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The bootloader should pass the locations of the kernel arguments and
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environment variables tables. Those tables contain the 32-bit address
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of NULL terminated strings. The environment variables table should be
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terminated by a NULL address.
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For a simpler implementation, the number of kernel arguments is fixed
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to two (the name of the kernel and the command line), and the two
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tables are actually the same one.
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The registers a0 to a3 should contain the following values:
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a0 - number of kernel arguments
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a1 - 32-bit address of the kernel arguments table
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a2 - 32-bit address of the environment variables table
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a3 - RAM size in bytes
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*/
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static void write_bootloader (CPUState *env, unsigned long bios_offset, int64_t kernel_addr)
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{
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uint32_t *p;
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/* Small bootloader */
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p = (uint32_t *) (phys_ram_base + bios_offset);
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stl_raw(p++, 0x0bf00010); /* j 0x1fc00040 */
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stl_raw(p++, 0x00000000); /* nop */
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/* Second part of the bootloader */
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p = (uint32_t *) (phys_ram_base + bios_offset + 0x040);
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stl_raw(p++, 0x3c040000); /* lui a0, 0 */
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stl_raw(p++, 0x34840002); /* ori a0, a0, 2 */
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stl_raw(p++, 0x3c050000 | ((ENVP_ADDR) >> 16)); /* lui a1, high(ENVP_ADDR) */
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stl_raw(p++, 0x34a50000 | ((ENVP_ADDR) & 0xffff)); /* ori a1, a0, low(ENVP_ADDR) */
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stl_raw(p++, 0x3c060000 | ((ENVP_ADDR + 8) >> 16)); /* lui a2, high(ENVP_ADDR + 8) */
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stl_raw(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff)); /* ori a2, a2, low(ENVP_ADDR + 8) */
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stl_raw(p++, 0x3c070000 | ((env->ram_size) >> 16)); /* lui a3, high(env->ram_size) */
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stl_raw(p++, 0x34e70000 | ((env->ram_size) & 0xffff)); /* ori a3, a3, low(env->ram_size) */
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stl_raw(p++, 0x3c1f0000 | ((kernel_addr) >> 16)); /* lui ra, high(kernel_addr) */;
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stl_raw(p++, 0x37ff0000 | ((kernel_addr) & 0xffff)); /* ori ra, ra, low(kernel_addr) */
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stl_raw(p++, 0x03e00008); /* jr ra */
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stl_raw(p++, 0x00000000); /* nop */
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}
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static void prom_set(int index, const char *string, ...)
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{
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va_list ap;
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uint32_t *p;
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uint32_t table_addr;
|
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char *s;
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if (index >= ENVP_NB_ENTRIES)
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return;
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p = (uint32_t *) (phys_ram_base + ENVP_ADDR + VIRT_TO_PHYS_ADDEND);
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p += index;
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if (string == NULL) {
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stl_raw(p, 0);
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return;
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}
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table_addr = ENVP_ADDR + sizeof(uint32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE;
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s = (char *) (phys_ram_base + VIRT_TO_PHYS_ADDEND + table_addr);
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stl_raw(p, table_addr);
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va_start(ap, string);
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vsnprintf (s, ENVP_ENTRY_SIZE, string, ap);
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va_end(ap);
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}
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/* Kernel */
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static int64_t load_kernel (CPUState *env)
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{
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int64_t kernel_addr = 0;
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int index = 0;
|
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long initrd_size;
|
||||
|
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if (load_elf(env->kernel_filename, VIRT_TO_PHYS_ADDEND, &kernel_addr) < 0) {
|
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
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env->kernel_filename);
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exit(1);
|
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}
|
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|
||||
/* load initrd */
|
||||
initrd_size = 0;
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if (env->initrd_filename) {
|
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initrd_size = load_image(env->initrd_filename,
|
||||
phys_ram_base + INITRD_LOAD_ADDR + VIRT_TO_PHYS_ADDEND);
|
||||
if (initrd_size == (target_ulong) -1) {
|
||||
fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
||||
env->initrd_filename);
|
||||
exit(1);
|
||||
}
|
||||
}
|
||||
|
||||
/* Store command line. */
|
||||
prom_set(index++, env->kernel_filename);
|
||||
if (initrd_size > 0)
|
||||
prom_set(index++, "rd_start=0x%08x rd_size=%li %s", INITRD_LOAD_ADDR, initrd_size, env->kernel_cmdline);
|
||||
else
|
||||
prom_set(index++, env->kernel_cmdline);
|
||||
|
||||
/* Setup minimum environment variables */
|
||||
prom_set(index++, "memsize");
|
||||
prom_set(index++, "%i", env->ram_size);
|
||||
prom_set(index++, "modetty0");
|
||||
prom_set(index++, "38400n8r");
|
||||
prom_set(index++, NULL);
|
||||
|
||||
return kernel_addr;
|
||||
}
|
||||
|
||||
static void main_cpu_reset(void *opaque)
|
||||
{
|
||||
CPUState *env = opaque;
|
||||
cpu_reset(env);
|
||||
|
||||
/* The bootload does not need to be rewritten as it is located in a
|
||||
read only location. The kernel location and the arguments table
|
||||
location does not change. */
|
||||
if (env->kernel_filename)
|
||||
load_kernel (env);
|
||||
}
|
||||
|
||||
void mips_malta_init (int ram_size, int vga_ram_size, int boot_device,
|
||||
DisplayState *ds, const char **fd_filename, int snapshot,
|
||||
const char *kernel_filename, const char *kernel_cmdline,
|
||||
const char *initrd_filename)
|
||||
{
|
||||
char buf[1024];
|
||||
unsigned long bios_offset;
|
||||
int64_t kernel_addr;
|
||||
PCIBus *pci_bus;
|
||||
CPUState *env;
|
||||
RTCState *rtc_state;
|
||||
fdctrl_t *floppy_controller;
|
||||
MaltaFPGAState *malta_fpga;
|
||||
int ret;
|
||||
|
||||
env = cpu_init();
|
||||
register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
|
||||
qemu_register_reset(main_cpu_reset, env);
|
||||
|
||||
/* allocate RAM */
|
||||
cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
|
||||
|
||||
/* Map the bios at two physical locations, as on the real board */
|
||||
bios_offset = ram_size + vga_ram_size;
|
||||
cpu_register_physical_memory(0x1e000000LL,
|
||||
BIOS_SIZE, bios_offset | IO_MEM_ROM);
|
||||
cpu_register_physical_memory(0x1fc00000LL,
|
||||
BIOS_SIZE, bios_offset | IO_MEM_ROM);
|
||||
|
||||
/* Load a BIOS image except if a kernel image has been specified. In
|
||||
the later case, just write a small bootloader to the flash
|
||||
location. */
|
||||
if (kernel_filename) {
|
||||
env->ram_size = ram_size;
|
||||
env->kernel_filename = kernel_filename;
|
||||
env->kernel_cmdline = kernel_cmdline;
|
||||
env->initrd_filename = initrd_filename;
|
||||
kernel_addr = load_kernel(env);
|
||||
write_bootloader(env, bios_offset, kernel_addr);
|
||||
} else {
|
||||
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
|
||||
ret = load_image(buf, phys_ram_base + bios_offset);
|
||||
if (ret != BIOS_SIZE) {
|
||||
fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
|
||||
buf);
|
||||
exit(1);
|
||||
}
|
||||
}
|
||||
|
||||
/* Board ID = 0x420 (Malta Board with CoreLV)
|
||||
XXX: theoretically 0x1e000010 should map to flash and 0x1fc00010 should
|
||||
map to the board ID. */
|
||||
stl_raw(phys_ram_base + bios_offset + 0x10, 0x00000420);
|
||||
|
||||
/* Init internal devices */
|
||||
cpu_mips_clock_init(env);
|
||||
cpu_mips_irqctrl_init();
|
||||
|
||||
/* FPGA */
|
||||
malta_fpga = malta_fpga_init(0x1f000000LL);
|
||||
|
||||
/* Interrupt controller */
|
||||
isa_pic = pic_init(pic_irq_request, env);
|
||||
|
||||
/* Northbridge */
|
||||
pci_bus = pci_gt64120_init(isa_pic);
|
||||
|
||||
/* Southbridge */
|
||||
piix4_init(pci_bus, 80);
|
||||
pci_piix3_ide_init(pci_bus, bs_table, 81);
|
||||
usb_uhci_init(pci_bus, 82);
|
||||
piix4_pm_init(pci_bus, 83);
|
||||
pit = pit_init(0x40, 0);
|
||||
DMA_init(0);
|
||||
|
||||
/* Super I/O */
|
||||
kbd_init();
|
||||
rtc_state = rtc_init(0x70, 8);
|
||||
serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]);
|
||||
parallel_init(0x378, 7, parallel_hds[0]);
|
||||
/* XXX: The floppy controller does not work correctly, something is
|
||||
probably wrong */
|
||||
floppy_controller = fdctrl_init(6, 2, 0, 0x3f0, fd_table);
|
||||
|
||||
/* Sound card */
|
||||
#ifdef HAS_AUDIO
|
||||
audio_init(pci_bus);
|
||||
#endif
|
||||
|
||||
/* Network card */
|
||||
network_init(pci_bus);
|
||||
}
|
||||
|
||||
QEMUMachine mips_malta_machine = {
|
||||
"malta",
|
||||
"MIPS Malta Core LV",
|
||||
mips_malta_init,
|
||||
};
|
||||
1
vl.c
1
vl.c
@ -6370,6 +6370,7 @@ void register_machines(void)
|
||||
qemu_register_machine(&prep_machine);
|
||||
#elif defined(TARGET_MIPS)
|
||||
qemu_register_machine(&mips_machine);
|
||||
qemu_register_machine(&mips_malta_machine);
|
||||
#elif defined(TARGET_SPARC)
|
||||
#ifdef TARGET_SPARC64
|
||||
qemu_register_machine(&sun4u_machine);
|
||||
|
||||
6
vl.h
6
vl.h
@ -302,6 +302,7 @@ typedef struct CharDriverState {
|
||||
QEMUBH *bh;
|
||||
} CharDriverState;
|
||||
|
||||
CharDriverState *qemu_chr_open(const char *filename);
|
||||
void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
|
||||
int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
|
||||
void qemu_chr_send_event(CharDriverState *s, int event);
|
||||
@ -824,6 +825,8 @@ void i440fx_set_smm(PCIDevice *d, int val);
|
||||
int piix3_init(PCIBus *bus, int devfn);
|
||||
void i440fx_init_memory_mappings(PCIDevice *d);
|
||||
|
||||
int piix4_init(PCIBus *bus, int devfn);
|
||||
|
||||
/* openpic.c */
|
||||
typedef struct openpic_t openpic_t;
|
||||
void openpic_set_irq(void *opaque, int n_IRQ, int level);
|
||||
@ -1059,6 +1062,9 @@ extern QEMUMachine heathrow_machine;
|
||||
/* mips_r4k.c */
|
||||
extern QEMUMachine mips_machine;
|
||||
|
||||
/* mips_malta.c */
|
||||
extern QEMUMachine mips_malta_machine;
|
||||
|
||||
/* mips_timer.c */
|
||||
extern void cpu_mips_clock_init(CPUState *);
|
||||
extern void cpu_mips_irqctrl_init (void);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user