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target/riscv: support for 128-bit U-type instructions

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Adding the 128-bit version of lui and auipc, and introducing to that end
a "set register with immediat" function to handle extension on 128 bits.

Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-12-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frédéric Pétrot 2022-01-06 22:01:01 +01:00 committed by Alistair Francis
parent 568f247f69
commit 57c108b864
2 changed files with 25 additions and 4 deletions
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8
target/riscv/insn_trans/trans_rvi.c.inc
View File

@ -26,14 +26,14 @@ static bool trans_illegal(DisasContext *ctx, arg_empty *a)
static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a) static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
{ {
REQUIRE_64BIT(ctx); REQUIRE_64_OR_128BIT(ctx);
return trans_illegal(ctx, a); return trans_illegal(ctx, a);
} }
static bool trans_lui(DisasContext *ctx, arg_lui *a) static bool trans_lui(DisasContext *ctx, arg_lui *a)
{ {
if (a->rd != 0) { if (a->rd != 0) {
tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm); gen_set_gpri(ctx, a->rd, a->imm);
} }
return true; return true;
} }
@ -41,7 +41,7 @@ static bool trans_lui(DisasContext *ctx, arg_lui *a)
static bool trans_auipc(DisasContext *ctx, arg_auipc *a) static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
{ {
if (a->rd != 0) { if (a->rd != 0) {
tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm + ctx->base.pc_next); gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next);
} }
return true; return true;
} }

21
target/riscv/translate.c
View File

@ -322,6 +322,27 @@ static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t)
} }
} }
static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm)
{
if (reg_num != 0) {
switch (get_ol(ctx)) {
case MXL_RV32:
tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm);
break;
case MXL_RV64:
case MXL_RV128:
tcg_gen_movi_tl(cpu_gpr[reg_num], imm);
break;
default:
g_assert_not_reached();
}
if (get_xl_max(ctx) == MXL_RV128) {
tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0));
}
}
}
static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh)
{ {
assert(get_ol(ctx) == MXL_RV128); assert(get_ol(ctx) == MXL_RV128);