From 562009e47c622298f82ee7557be9e15d5e50cee5 Mon Sep 17 00:00:00 2001 From: Atish Patra Date: Mon, 20 Jun 2022 16:15:51 -0700 Subject: [PATCH] target/riscv: Fix PMU CSR predicate function The predicate function calculates the counter index incorrectly for hpmcounterx. Fix the counter index to reflect correct CSR number. Fixes: e39a8320b088 ("target/riscv: Support the Virtual Instruction fault") Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Signed-off-by: Atish Patra Signed-off-by: Atish Patra Message-Id: <20220620231603.2547260-2-atishp@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6dbe9b541f..46bd417cc1 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -72,6 +72,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno) #if !defined(CONFIG_USER_ONLY) CPUState *cs = env_cpu(env); RISCVCPU *cpu = RISCV_CPU(cs); + int ctr_index; if (!cpu->cfg.ext_counters) { /* The Counters extensions is not enabled */ @@ -99,8 +100,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno) } break; case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: - if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) && - get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) { + ctr_index = csrno - CSR_CYCLE; + if (!get_field(env->hcounteren, 1 << ctr_index) && + get_field(env->mcounteren, 1 << ctr_index)) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } break; @@ -126,8 +128,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno) } break; case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: - if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) && - get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) { + ctr_index = csrno - CSR_CYCLEH; + if (!get_field(env->hcounteren, 1 << ctr_index) && + get_field(env->mcounteren, 1 << ctr_index)) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } break;