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tcg/loongarch64: Lower rotli_vec to vrotri
Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-16-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -1902,6 +1902,26 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
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tcg_out32(s, encode_vdvjvk_insn(rotrv_vec_insn[vece], a0, a1,
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temp_vec));
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break;
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case INDEX_op_rotli_vec:
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/* rotli_vec a1, a2 = rotri_vec a1, -a2 */
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a2 = extract32(-a2, 0, 3 + vece);
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switch (vece) {
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case MO_8:
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tcg_out_opc_vrotri_b(s, a0, a1, a2);
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break;
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case MO_16:
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tcg_out_opc_vrotri_h(s, a0, a1, a2);
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break;
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case MO_32:
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tcg_out_opc_vrotri_w(s, a0, a1, a2);
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break;
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case MO_64:
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tcg_out_opc_vrotri_d(s, a0, a1, a2);
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break;
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default:
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g_assert_not_reached();
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}
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break;
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case INDEX_op_bitsel_vec:
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/* vbitsel vd, vj, vk, va = bitsel_vec vd, va, vk, vj */
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tcg_out_opc_vbitsel_v(s, a0, a3, a2, a1);
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@ -2140,6 +2160,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
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case INDEX_op_shli_vec:
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case INDEX_op_shri_vec:
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case INDEX_op_sari_vec:
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case INDEX_op_rotli_vec:
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return C_O1_I1(w, w);
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case INDEX_op_bitsel_vec:
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@ -189,7 +189,7 @@ extern bool use_lsx_instructions;
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#define TCG_TARGET_HAS_shi_vec 1
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#define TCG_TARGET_HAS_shs_vec 0
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#define TCG_TARGET_HAS_shv_vec 1
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#define TCG_TARGET_HAS_roti_vec 0
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#define TCG_TARGET_HAS_roti_vec 1
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#define TCG_TARGET_HAS_rots_vec 0
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#define TCG_TARGET_HAS_rotv_vec 1
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#define TCG_TARGET_HAS_sat_vec 1
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