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arm: Factor out "generate right kind of step exception"

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We currently have two places that do:
            if (dc->ss_active) {
                gen_step_complete_exception(dc);
            } else {
                gen_exception_internal(EXCP_DEBUG);
            }

Factor this out into its own function, as we're about to add
a third place that needs the same logic.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1491844419-12485-4-git-send-email-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2017-04-20 17:32:30 +01:00
parent bedb8a6b09
commit 5425415ebb
1 changed files with 16 additions and 12 deletions
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28
target/arm/translate.c
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@ -296,6 +296,19 @@ static void gen_step_complete_exception(DisasContext *s)
s->is_jmp = DISAS_EXC; s->is_jmp = DISAS_EXC;
} }
static void gen_singlestep_exception(DisasContext *s)
{
/* Generate the right kind of exception for singlestep, which is
* either the architectural singlestep or EXCP_DEBUG for QEMU's
* gdb singlestepping.
*/
if (s->ss_active) {
gen_step_complete_exception(s);
} else {
gen_exception_internal(EXCP_DEBUG);
}
}
static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b) static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b)
{ {
TCGv_i32 tmp1 = tcg_temp_new_i32(); TCGv_i32 tmp1 = tcg_temp_new_i32();
@ -11998,24 +12011,15 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
gen_set_pc_im(dc, dc->pc); gen_set_pc_im(dc, dc->pc);
/* fall through */ /* fall through */
default: default:
if (dc->ss_active) { /* FIXME: Single stepping a WFI insn will not halt the CPU. */
gen_step_complete_exception(dc); gen_singlestep_exception(dc);
} else {
/* FIXME: Single stepping a WFI insn will not halt
the CPU. */
gen_exception_internal(EXCP_DEBUG);
}
} }
if (dc->condjmp) { if (dc->condjmp) {
/* "Condition failed" instruction codepath. */ /* "Condition failed" instruction codepath. */
gen_set_label(dc->condlabel); gen_set_label(dc->condlabel);
gen_set_condexec(dc); gen_set_condexec(dc);
gen_set_pc_im(dc, dc->pc); gen_set_pc_im(dc, dc->pc);
if (dc->ss_active) { gen_singlestep_exception(dc);
gen_step_complete_exception(dc);
} else {
gen_exception_internal(EXCP_DEBUG);
}
} }
} else { } else {
/* While branches must always occur at the end of an IT block, /* While branches must always occur at the end of an IT block,