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misc: introduce new mos6522 VIA device and enable it for ppc builds
The MOS6522 VIA forms the bridge part of several Mac devices, including the Mac via-cuda and via-pmu devices. Introduce a standard mos6522 device that can be shared amongst multiple implementations. This is effectively taking the 6522 parts out of cuda.c and turning them into a separate device whilst also applying some style tidy-ups and including a conversion to trace-events. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Mark Cave-Ayland
David Gibson
parent
ce19480e91
commit
51f233ec92
@ -30,6 +30,7 @@ CONFIG_MAC=y
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CONFIG_ESCC=y
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CONFIG_ESCC=y
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CONFIG_MACIO=y
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CONFIG_MACIO=y
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CONFIG_SUNGEM=y
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CONFIG_SUNGEM=y
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CONFIG_MOS6522=y
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CONFIG_CUDA=y
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CONFIG_CUDA=y
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CONFIG_ADB=y
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CONFIG_ADB=y
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CONFIG_MAC_NVRAM=y
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CONFIG_MAC_NVRAM=y
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@ -17,6 +17,9 @@ common-obj-$(CONFIG_INTEGRATOR_DEBUG) += arm_integrator_debug.o
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common-obj-$(CONFIG_A9SCU) += a9scu.o
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common-obj-$(CONFIG_A9SCU) += a9scu.o
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common-obj-$(CONFIG_ARM11SCU) += arm11scu.o
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common-obj-$(CONFIG_ARM11SCU) += arm11scu.o
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# Mac devices
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common-obj-$(CONFIG_MOS6522) += mos6522.o
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# PKUnity SoC devices
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# PKUnity SoC devices
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common-obj-$(CONFIG_PUV3) += puv3_pm.o
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common-obj-$(CONFIG_PUV3) += puv3_pm.o
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505
hw/misc/mos6522.c
Normal file
505
hw/misc/mos6522.c
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@ -0,0 +1,505 @@
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/*
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* QEMU MOS6522 VIA emulation
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*
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* Copyright (c) 2004-2007 Fabrice Bellard
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* Copyright (c) 2007 Jocelyn Mayer
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* Copyright (c) 2018 Mark Cave-Ayland
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/input/adb.h"
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#include "hw/misc/mos6522.h"
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#include "qemu/timer.h"
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#include "sysemu/sysemu.h"
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#include "qemu/cutils.h"
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#include "qemu/log.h"
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#include "trace.h"
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/* XXX: implement all timer modes */
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static void mos6522_timer_update(MOS6522State *s, MOS6522Timer *ti,
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int64_t current_time);
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static void mos6522_update_irq(MOS6522State *s)
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{
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if (s->ifr & s->ier & (SR_INT | T1_INT | T2_INT)) {
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qemu_irq_raise(s->irq);
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} else {
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qemu_irq_lower(s->irq);
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}
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}
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static uint64_t get_counter_value(MOS6522State *s, MOS6522Timer *ti)
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{
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MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(s);
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if (ti->index == 0) {
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return mdc->get_timer1_counter_value(s, ti);
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} else {
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return mdc->get_timer2_counter_value(s, ti);
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}
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}
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static uint64_t get_load_time(MOS6522State *s, MOS6522Timer *ti)
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{
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MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(s);
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if (ti->index == 0) {
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return mdc->get_timer1_load_time(s, ti);
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} else {
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return mdc->get_timer2_load_time(s, ti);
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}
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}
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static unsigned int get_counter(MOS6522State *s, MOS6522Timer *ti)
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{
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int64_t d;
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unsigned int counter;
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d = get_counter_value(s, ti);
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if (ti->index == 0) {
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/* the timer goes down from latch to -1 (period of latch + 2) */
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if (d <= (ti->counter_value + 1)) {
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counter = (ti->counter_value - d) & 0xffff;
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} else {
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counter = (d - (ti->counter_value + 1)) % (ti->latch + 2);
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counter = (ti->latch - counter) & 0xffff;
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}
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} else {
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counter = (ti->counter_value - d) & 0xffff;
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}
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return counter;
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}
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static void set_counter(MOS6522State *s, MOS6522Timer *ti, unsigned int val)
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{
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trace_mos6522_set_counter(1 + ti->index, val);
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ti->load_time = get_load_time(s, ti);
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ti->counter_value = val;
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mos6522_timer_update(s, ti, ti->load_time);
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}
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static int64_t get_next_irq_time(MOS6522State *s, MOS6522Timer *ti,
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int64_t current_time)
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{
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int64_t d, next_time;
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unsigned int counter;
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/* current counter value */
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d = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ti->load_time,
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ti->frequency, NANOSECONDS_PER_SECOND);
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/* the timer goes down from latch to -1 (period of latch + 2) */
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if (d <= (ti->counter_value + 1)) {
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counter = (ti->counter_value - d) & 0xffff;
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} else {
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counter = (d - (ti->counter_value + 1)) % (ti->latch + 2);
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counter = (ti->latch - counter) & 0xffff;
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}
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/* Note: we consider the irq is raised on 0 */
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if (counter == 0xffff) {
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next_time = d + ti->latch + 1;
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} else if (counter == 0) {
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next_time = d + ti->latch + 2;
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} else {
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next_time = d + counter;
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}
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trace_mos6522_get_next_irq_time(ti->latch, d, next_time - d);
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next_time = muldiv64(next_time, NANOSECONDS_PER_SECOND, ti->frequency) +
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ti->load_time;
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if (next_time <= current_time) {
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next_time = current_time + 1;
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}
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return next_time;
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}
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static void mos6522_timer_update(MOS6522State *s, MOS6522Timer *ti,
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int64_t current_time)
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{
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if (!ti->timer) {
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return;
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}
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if (ti->index == 0 && (s->acr & T1MODE) != T1MODE_CONT) {
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timer_del(ti->timer);
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} else {
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ti->next_irq_time = get_next_irq_time(s, ti, current_time);
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timer_mod(ti->timer, ti->next_irq_time);
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}
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}
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static void mos6522_timer1(void *opaque)
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{
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MOS6522State *s = opaque;
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MOS6522Timer *ti = &s->timers[0];
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mos6522_timer_update(s, ti, ti->next_irq_time);
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s->ifr |= T1_INT;
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mos6522_update_irq(s);
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}
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static void mos6522_timer2(void *opaque)
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{
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MOS6522State *s = opaque;
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MOS6522Timer *ti = &s->timers[1];
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mos6522_timer_update(s, ti, ti->next_irq_time);
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s->ifr |= T2_INT;
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mos6522_update_irq(s);
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}
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static void mos6522_set_sr_int(MOS6522State *s)
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{
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trace_mos6522_set_sr_int();
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s->ifr |= SR_INT;
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mos6522_update_irq(s);
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}
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static uint64_t mos6522_get_counter_value(MOS6522State *s, MOS6522Timer *ti)
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{
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uint64_t d;
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d = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ti->load_time,
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ti->frequency, NANOSECONDS_PER_SECOND);
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return d;
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}
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static uint64_t mos6522_get_load_time(MOS6522State *s, MOS6522Timer *ti)
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{
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uint64_t load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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return load_time;
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}
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static void mos6522_portA_write(MOS6522State *s)
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{
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qemu_log_mask(LOG_UNIMP, "portA_write unimplemented");
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}
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static void mos6522_portB_write(MOS6522State *s)
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{
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qemu_log_mask(LOG_UNIMP, "portB_write unimplemented");
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}
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uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size)
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{
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MOS6522State *s = opaque;
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uint32_t val;
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switch (addr) {
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case VIA_REG_B:
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val = s->b;
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break;
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case VIA_REG_A:
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val = s->a;
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break;
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case VIA_REG_DIRB:
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val = s->dirb;
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break;
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case VIA_REG_DIRA:
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val = s->dira;
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break;
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case VIA_REG_T1CL:
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val = get_counter(s, &s->timers[0]) & 0xff;
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s->ifr &= ~T1_INT;
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mos6522_update_irq(s);
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break;
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case VIA_REG_T1CH:
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val = get_counter(s, &s->timers[0]) >> 8;
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mos6522_update_irq(s);
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break;
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case VIA_REG_T1LL:
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val = s->timers[0].latch & 0xff;
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break;
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case VIA_REG_T1LH:
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/* XXX: check this */
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val = (s->timers[0].latch >> 8) & 0xff;
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break;
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case VIA_REG_T2CL:
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val = get_counter(s, &s->timers[1]) & 0xff;
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s->ifr &= ~T2_INT;
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mos6522_update_irq(s);
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break;
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case VIA_REG_T2CH:
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val = get_counter(s, &s->timers[1]) >> 8;
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break;
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case VIA_REG_SR:
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val = s->sr;
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s->ifr &= ~(SR_INT | CB1_INT | CB2_INT);
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mos6522_update_irq(s);
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break;
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case VIA_REG_ACR:
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val = s->acr;
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break;
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case VIA_REG_PCR:
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val = s->pcr;
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break;
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case VIA_REG_IFR:
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val = s->ifr;
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if (s->ifr & s->ier) {
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val |= 0x80;
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}
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break;
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case VIA_REG_IER:
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val = s->ier | 0x80;
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break;
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default:
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case VIA_REG_ANH:
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val = s->anh;
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break;
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}
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if (addr != VIA_REG_IFR || val != 0) {
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trace_mos6522_read(addr, val);
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}
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return val;
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}
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void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
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{
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MOS6522State *s = opaque;
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MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(s);
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trace_mos6522_write(addr, val);
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switch (addr) {
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case VIA_REG_B:
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s->b = (s->b & ~s->dirb) | (val & s->dirb);
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mdc->portB_write(s);
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break;
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case VIA_REG_A:
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s->a = (s->a & ~s->dira) | (val & s->dira);
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mdc->portA_write(s);
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break;
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case VIA_REG_DIRB:
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s->dirb = val;
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break;
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case VIA_REG_DIRA:
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s->dira = val;
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break;
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case VIA_REG_T1CL:
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s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
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mos6522_timer_update(s, &s->timers[0],
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qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
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break;
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case VIA_REG_T1CH:
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s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
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s->ifr &= ~T1_INT;
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set_counter(s, &s->timers[0], s->timers[0].latch);
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break;
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case VIA_REG_T1LL:
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s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
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mos6522_timer_update(s, &s->timers[0],
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qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
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break;
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case VIA_REG_T1LH:
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s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
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s->ifr &= ~T1_INT;
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mos6522_timer_update(s, &s->timers[0],
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qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
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break;
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case VIA_REG_T2CL:
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s->timers[1].latch = (s->timers[1].latch & 0xff00) | val;
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break;
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case VIA_REG_T2CH:
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/* To ensure T2 generates an interrupt on zero crossing with the
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common timer code, write the value directly from the latch to
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the counter */
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s->timers[1].latch = (s->timers[1].latch & 0xff) | (val << 8);
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s->ifr &= ~T2_INT;
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set_counter(s, &s->timers[1], s->timers[1].latch);
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break;
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case VIA_REG_SR:
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s->sr = val;
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||||||
|
break;
|
||||||
|
case VIA_REG_ACR:
|
||||||
|
s->acr = val;
|
||||||
|
mos6522_timer_update(s, &s->timers[0],
|
||||||
|
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
|
||||||
|
break;
|
||||||
|
case VIA_REG_PCR:
|
||||||
|
s->pcr = val;
|
||||||
|
break;
|
||||||
|
case VIA_REG_IFR:
|
||||||
|
/* reset bits */
|
||||||
|
s->ifr &= ~val;
|
||||||
|
mos6522_update_irq(s);
|
||||||
|
break;
|
||||||
|
case VIA_REG_IER:
|
||||||
|
if (val & IER_SET) {
|
||||||
|
/* set bits */
|
||||||
|
s->ier |= val & 0x7f;
|
||||||
|
} else {
|
||||||
|
/* reset bits */
|
||||||
|
s->ier &= ~val;
|
||||||
|
}
|
||||||
|
mos6522_update_irq(s);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
case VIA_REG_ANH:
|
||||||
|
s->anh = val;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static const MemoryRegionOps mos6522_ops = {
|
||||||
|
.read = mos6522_read,
|
||||||
|
.write = mos6522_write,
|
||||||
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
||||||
|
.valid = {
|
||||||
|
.min_access_size = 1,
|
||||||
|
.max_access_size = 1,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
static bool mos6522_timer_exist(void *opaque, int version_id)
|
||||||
|
{
|
||||||
|
MOS6522Timer *s = opaque;
|
||||||
|
|
||||||
|
return s->timer != NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const VMStateDescription vmstate_mos6522_timer = {
|
||||||
|
.name = "mos6522_timer",
|
||||||
|
.version_id = 0,
|
||||||
|
.minimum_version_id = 0,
|
||||||
|
.fields = (VMStateField[]) {
|
||||||
|
VMSTATE_UINT16(latch, MOS6522Timer),
|
||||||
|
VMSTATE_UINT16(counter_value, MOS6522Timer),
|
||||||
|
VMSTATE_INT64(load_time, MOS6522Timer),
|
||||||
|
VMSTATE_INT64(next_irq_time, MOS6522Timer),
|
||||||
|
VMSTATE_TIMER_PTR_TEST(timer, MOS6522Timer, mos6522_timer_exist),
|
||||||
|
VMSTATE_END_OF_LIST()
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
static const VMStateDescription vmstate_mos6522 = {
|
||||||
|
.name = "mos6522",
|
||||||
|
.version_id = 0,
|
||||||
|
.minimum_version_id = 0,
|
||||||
|
.fields = (VMStateField[]) {
|
||||||
|
VMSTATE_UINT8(a, MOS6522State),
|
||||||
|
VMSTATE_UINT8(b, MOS6522State),
|
||||||
|
VMSTATE_UINT8(dira, MOS6522State),
|
||||||
|
VMSTATE_UINT8(dirb, MOS6522State),
|
||||||
|
VMSTATE_UINT8(sr, MOS6522State),
|
||||||
|
VMSTATE_UINT8(acr, MOS6522State),
|
||||||
|
VMSTATE_UINT8(pcr, MOS6522State),
|
||||||
|
VMSTATE_UINT8(ifr, MOS6522State),
|
||||||
|
VMSTATE_UINT8(ier, MOS6522State),
|
||||||
|
VMSTATE_UINT8(anh, MOS6522State),
|
||||||
|
VMSTATE_STRUCT_ARRAY(timers, MOS6522State, 2, 1,
|
||||||
|
vmstate_mos6522_timer, MOS6522Timer),
|
||||||
|
VMSTATE_END_OF_LIST()
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
static void mos6522_reset(DeviceState *dev)
|
||||||
|
{
|
||||||
|
MOS6522State *s = MOS6522(dev);
|
||||||
|
|
||||||
|
s->b = 0;
|
||||||
|
s->a = 0;
|
||||||
|
s->dirb = 0xff;
|
||||||
|
s->dira = 0;
|
||||||
|
s->sr = 0;
|
||||||
|
s->acr = 0;
|
||||||
|
s->pcr = 0;
|
||||||
|
s->ifr = 0;
|
||||||
|
s->ier = 0;
|
||||||
|
/* s->ier = T1_INT | SR_INT; */
|
||||||
|
s->anh = 0;
|
||||||
|
|
||||||
|
s->timers[0].latch = 0xffff;
|
||||||
|
set_counter(s, &s->timers[0], 0xffff);
|
||||||
|
|
||||||
|
s->timers[1].latch = 0xffff;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void mos6522_realize(DeviceState *dev, Error **errp)
|
||||||
|
{
|
||||||
|
MOS6522State *s = MOS6522(dev);
|
||||||
|
|
||||||
|
s->timers[0].frequency = s->frequency;
|
||||||
|
s->timers[1].frequency = s->frequency;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void mos6522_init(Object *obj)
|
||||||
|
{
|
||||||
|
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
||||||
|
MOS6522State *s = MOS6522(obj);
|
||||||
|
int i;
|
||||||
|
|
||||||
|
memory_region_init_io(&s->mem, obj, &mos6522_ops, s, "mos6522", 0x10);
|
||||||
|
sysbus_init_mmio(sbd, &s->mem);
|
||||||
|
sysbus_init_irq(sbd, &s->irq);
|
||||||
|
|
||||||
|
for (i = 0; i < ARRAY_SIZE(s->timers); i++) {
|
||||||
|
s->timers[i].index = i;
|
||||||
|
}
|
||||||
|
|
||||||
|
s->timers[0].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, mos6522_timer1, s);
|
||||||
|
s->timers[1].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, mos6522_timer2, s);
|
||||||
|
}
|
||||||
|
|
||||||
|
static Property mos6522_properties[] = {
|
||||||
|
DEFINE_PROP_UINT64("frequency", MOS6522State, frequency, 0),
|
||||||
|
DEFINE_PROP_END_OF_LIST()
|
||||||
|
};
|
||||||
|
|
||||||
|
static void mos6522_class_init(ObjectClass *oc, void *data)
|
||||||
|
{
|
||||||
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
||||||
|
MOS6522DeviceClass *mdc = MOS6522_DEVICE_CLASS(oc);
|
||||||
|
|
||||||
|
dc->realize = mos6522_realize;
|
||||||
|
dc->reset = mos6522_reset;
|
||||||
|
dc->vmsd = &vmstate_mos6522;
|
||||||
|
dc->props = mos6522_properties;
|
||||||
|
mdc->parent_realize = dc->realize;
|
||||||
|
mdc->set_sr_int = mos6522_set_sr_int;
|
||||||
|
mdc->portB_write = mos6522_portB_write;
|
||||||
|
mdc->portA_write = mos6522_portA_write;
|
||||||
|
mdc->get_timer1_counter_value = mos6522_get_counter_value;
|
||||||
|
mdc->get_timer2_counter_value = mos6522_get_counter_value;
|
||||||
|
mdc->get_timer1_load_time = mos6522_get_load_time;
|
||||||
|
mdc->get_timer2_load_time = mos6522_get_load_time;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const TypeInfo mos6522_type_info = {
|
||||||
|
.name = TYPE_MOS6522,
|
||||||
|
.parent = TYPE_SYS_BUS_DEVICE,
|
||||||
|
.instance_size = sizeof(MOS6522State),
|
||||||
|
.instance_init = mos6522_init,
|
||||||
|
.abstract = true,
|
||||||
|
.class_size = sizeof(MOS6522DeviceClass),
|
||||||
|
.class_init = mos6522_class_init,
|
||||||
|
};
|
||||||
|
|
||||||
|
static void mos6522_register_types(void)
|
||||||
|
{
|
||||||
|
type_register_static(&mos6522_type_info);
|
||||||
|
}
|
||||||
|
|
||||||
|
type_init(mos6522_register_types)
|
||||||
@ -70,3 +70,10 @@ msf2_sysreg_write_pll_status(void) "Invalid write to read only PLL status regist
|
|||||||
#hw/misc/imx7_gpr.c
|
#hw/misc/imx7_gpr.c
|
||||||
imx7_gpr_read(uint64_t offset) "addr 0x%08" HWADDR_PRIx
|
imx7_gpr_read(uint64_t offset) "addr 0x%08" HWADDR_PRIx
|
||||||
imx7_gpr_write(uint64_t offset, uint64_t value) "addr 0x%08" HWADDR_PRIx "value 0x%08" HWADDR_PRIx
|
imx7_gpr_write(uint64_t offset, uint64_t value) "addr 0x%08" HWADDR_PRIx "value 0x%08" HWADDR_PRIx
|
||||||
|
|
||||||
|
# hw/misc/mos6522.c
|
||||||
|
mos6522_set_counter(int index, unsigned int val) "T%d.counter=%d"
|
||||||
|
mos6522_get_next_irq_time(uint16_t latch, int64_t d, int64_t delta) "latch=%d counter=0x%"PRId64 " delta_next=0x%"PRId64
|
||||||
|
mos6522_set_sr_int(void) "set sr_int"
|
||||||
|
mos6522_write(uint64_t addr, uint64_t val) "reg=0x%"PRIx64 " val=0x%"PRIx64
|
||||||
|
mos6522_read(uint64_t addr, unsigned val) "reg=0x%"PRIx64 " val=0x%x"
|
||||||
|
|||||||
152
include/hw/misc/mos6522.h
Normal file
152
include/hw/misc/mos6522.h
Normal file
@ -0,0 +1,152 @@
|
|||||||
|
/*
|
||||||
|
* QEMU MOS6522 VIA emulation
|
||||||
|
*
|
||||||
|
* Copyright (c) 2004-2007 Fabrice Bellard
|
||||||
|
* Copyright (c) 2007 Jocelyn Mayer
|
||||||
|
* Copyright (c) 2018 Mark Cave-Ayland
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||||
|
* of this software and associated documentation files (the "Software"), to deal
|
||||||
|
* in the Software without restriction, including without limitation the rights
|
||||||
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||||
|
* copies of the Software, and to permit persons to whom the Software is
|
||||||
|
* furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||||
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||||
|
* THE SOFTWARE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef MOS6522_H
|
||||||
|
#define MOS6522_H
|
||||||
|
|
||||||
|
#include "exec/memory.h"
|
||||||
|
#include "hw/sysbus.h"
|
||||||
|
#include "hw/ide/internal.h"
|
||||||
|
#include "hw/input/adb.h"
|
||||||
|
|
||||||
|
/* Bits in ACR */
|
||||||
|
#define SR_CTRL 0x1c /* Shift register control bits */
|
||||||
|
#define SR_EXT 0x0c /* Shift on external clock */
|
||||||
|
#define SR_OUT 0x10 /* Shift out if 1 */
|
||||||
|
|
||||||
|
/* Bits in IFR and IER */
|
||||||
|
#define IER_SET 0x80 /* set bits in IER */
|
||||||
|
#define IER_CLR 0 /* clear bits in IER */
|
||||||
|
|
||||||
|
#define CA2_INT 0x01
|
||||||
|
#define CA1_INT 0x02
|
||||||
|
#define SR_INT 0x04 /* Shift register full/empty */
|
||||||
|
#define CB2_INT 0x08
|
||||||
|
#define CB1_INT 0x10
|
||||||
|
#define T2_INT 0x20 /* Timer 2 interrupt */
|
||||||
|
#define T1_INT 0x40 /* Timer 1 interrupt */
|
||||||
|
|
||||||
|
/* Bits in ACR */
|
||||||
|
#define T1MODE 0xc0 /* Timer 1 mode */
|
||||||
|
#define T1MODE_CONT 0x40 /* continuous interrupts */
|
||||||
|
|
||||||
|
/* VIA registers */
|
||||||
|
#define VIA_REG_B 0x00
|
||||||
|
#define VIA_REG_A 0x01
|
||||||
|
#define VIA_REG_DIRB 0x02
|
||||||
|
#define VIA_REG_DIRA 0x03
|
||||||
|
#define VIA_REG_T1CL 0x04
|
||||||
|
#define VIA_REG_T1CH 0x05
|
||||||
|
#define VIA_REG_T1LL 0x06
|
||||||
|
#define VIA_REG_T1LH 0x07
|
||||||
|
#define VIA_REG_T2CL 0x08
|
||||||
|
#define VIA_REG_T2CH 0x09
|
||||||
|
#define VIA_REG_SR 0x0a
|
||||||
|
#define VIA_REG_ACR 0x0b
|
||||||
|
#define VIA_REG_PCR 0x0c
|
||||||
|
#define VIA_REG_IFR 0x0d
|
||||||
|
#define VIA_REG_IER 0x0e
|
||||||
|
#define VIA_REG_ANH 0x0f
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MOS6522Timer:
|
||||||
|
* @counter_value: counter value at load time
|
||||||
|
*/
|
||||||
|
typedef struct MOS6522Timer {
|
||||||
|
int index;
|
||||||
|
uint16_t latch;
|
||||||
|
uint16_t counter_value;
|
||||||
|
int64_t load_time;
|
||||||
|
int64_t next_irq_time;
|
||||||
|
uint64_t frequency;
|
||||||
|
QEMUTimer *timer;
|
||||||
|
} MOS6522Timer;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MOS6522State:
|
||||||
|
* @b: B-side data
|
||||||
|
* @a: A-side data
|
||||||
|
* @dirb: B-side direction (1=output)
|
||||||
|
* @dira: A-side direction (1=output)
|
||||||
|
* @sr: Shift register
|
||||||
|
* @acr: Auxiliary control register
|
||||||
|
* @pcr: Peripheral control register
|
||||||
|
* @ifr: Interrupt flag register
|
||||||
|
* @ier: Interrupt enable register
|
||||||
|
* @anh: A-side data, no handshake
|
||||||
|
* @last_b: last value of B register
|
||||||
|
* @last_acr: last value of ACR register
|
||||||
|
*/
|
||||||
|
typedef struct MOS6522State {
|
||||||
|
/*< private >*/
|
||||||
|
SysBusDevice parent_obj;
|
||||||
|
/*< public >*/
|
||||||
|
|
||||||
|
MemoryRegion mem;
|
||||||
|
/* VIA registers */
|
||||||
|
uint8_t b;
|
||||||
|
uint8_t a;
|
||||||
|
uint8_t dirb;
|
||||||
|
uint8_t dira;
|
||||||
|
uint8_t sr;
|
||||||
|
uint8_t acr;
|
||||||
|
uint8_t pcr;
|
||||||
|
uint8_t ifr;
|
||||||
|
uint8_t ier;
|
||||||
|
uint8_t anh;
|
||||||
|
|
||||||
|
MOS6522Timer timers[2];
|
||||||
|
uint64_t frequency;
|
||||||
|
|
||||||
|
qemu_irq irq;
|
||||||
|
} MOS6522State;
|
||||||
|
|
||||||
|
#define TYPE_MOS6522 "mos6522"
|
||||||
|
#define MOS6522(obj) OBJECT_CHECK(MOS6522State, (obj), TYPE_MOS6522)
|
||||||
|
|
||||||
|
typedef struct MOS6522DeviceClass {
|
||||||
|
DeviceClass parent_class;
|
||||||
|
|
||||||
|
DeviceRealize parent_realize;
|
||||||
|
void (*set_sr_int)(MOS6522State *dev);
|
||||||
|
void (*portB_write)(MOS6522State *dev);
|
||||||
|
void (*portA_write)(MOS6522State *dev);
|
||||||
|
/* These are used to influence the CUDA MacOS timebase calibration */
|
||||||
|
uint64_t (*get_timer1_counter_value)(MOS6522State *dev, MOS6522Timer *ti);
|
||||||
|
uint64_t (*get_timer2_counter_value)(MOS6522State *dev, MOS6522Timer *ti);
|
||||||
|
uint64_t (*get_timer1_load_time)(MOS6522State *dev, MOS6522Timer *ti);
|
||||||
|
uint64_t (*get_timer2_load_time)(MOS6522State *dev, MOS6522Timer *ti);
|
||||||
|
} MOS6522DeviceClass;
|
||||||
|
|
||||||
|
#define MOS6522_DEVICE_CLASS(cls) \
|
||||||
|
OBJECT_CLASS_CHECK(MOS6522DeviceClass, (cls), TYPE_MOS6522)
|
||||||
|
#define MOS6522_DEVICE_GET_CLASS(obj) \
|
||||||
|
OBJECT_GET_CLASS(MOS6522DeviceClass, (obj), TYPE_MOS6522)
|
||||||
|
|
||||||
|
uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size);
|
||||||
|
void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size);
|
||||||
|
|
||||||
|
#endif /* MOS6522_H */
|
||||||
Loading…
Reference in New Issue
Block a user