mirror of
https://github.com/qemu/qemu.git
synced 2024-11-24 03:13:44 +08:00
i8259: Factor out base class for KVM reuse
Analogously to the APIC, we will reuse some parts of the user space i8259 model for KVM. The base class provides a common device state, the vmstate, the property list, a reset core and some shared init bits. This also introduces a common helper to instantiate a single i8259 chip from the cascade-creating i8259_init function. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
This commit is contained in:
parent
9aa78c425f
commit
512709f559
@ -220,7 +220,7 @@ hw-obj-$(CONFIG_APPLESMC) += applesmc.o
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hw-obj-$(CONFIG_SMARTCARD) += usb-ccid.o ccid-card-passthru.o
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hw-obj-$(CONFIG_SMARTCARD_NSS) += ccid-card-emulated.o
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hw-obj-$(CONFIG_USB_REDIR) += usb-redir.o
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hw-obj-$(CONFIG_I8259) += i8259.o
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hw-obj-$(CONFIG_I8259) += i8259_common.o i8259.o
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# PPC devices
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hw-obj-$(CONFIG_PREP_PCI) += prep_pci.o
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158
hw/i8259.c
158
hw/i8259.c
@ -26,6 +26,7 @@
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#include "isa.h"
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#include "monitor.h"
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#include "qemu-timer.h"
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#include "i8259_internal.h"
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/* debug PIC */
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//#define DEBUG_PIC
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@ -40,35 +41,6 @@
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//#define DEBUG_IRQ_LATENCY
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//#define DEBUG_IRQ_COUNT
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typedef struct PicState PicState;
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struct PicState {
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ISADevice dev;
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uint8_t last_irr; /* edge detection */
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uint8_t irr; /* interrupt request register */
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uint8_t imr; /* interrupt mask register */
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uint8_t isr; /* interrupt service register */
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uint8_t priority_add; /* highest irq priority */
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uint8_t irq_base;
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uint8_t read_reg_select;
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uint8_t poll;
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uint8_t special_mask;
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uint8_t init_state;
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uint8_t auto_eoi;
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uint8_t rotate_on_auto_eoi;
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uint8_t special_fully_nested_mode;
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uint8_t init4; /* true if 4 byte init */
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uint8_t single_mode; /* true if slave pic is not initialized */
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uint8_t elcr; /* PIIX edge/trigger selection*/
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uint8_t elcr_mask;
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qemu_irq int_out[1];
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uint32_t master; /* reflects /SP input pin */
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uint32_t iobase;
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uint32_t elcr_addr;
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MemoryRegion base_io;
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MemoryRegion elcr_io;
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};
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#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
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static int irq_level[16];
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#endif
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@ -79,11 +51,11 @@ static uint64_t irq_count[16];
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static int64_t irq_time[16];
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#endif
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DeviceState *isa_pic;
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static PicState *slave_pic;
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static PICCommonState *slave_pic;
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/* return the highest priority found in mask (highest = smallest
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number). Return 8 if no irq */
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static int get_priority(PicState *s, int mask)
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static int get_priority(PICCommonState *s, int mask)
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{
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int priority;
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@ -98,7 +70,7 @@ static int get_priority(PicState *s, int mask)
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}
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/* return the pic wanted interrupt. return -1 if none */
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static int pic_get_irq(PicState *s)
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static int pic_get_irq(PICCommonState *s)
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{
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int mask, cur_priority, priority;
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@ -127,7 +99,7 @@ static int pic_get_irq(PicState *s)
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}
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/* Update INT output. Must be called every time the output may have changed. */
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static void pic_update_irq(PicState *s)
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static void pic_update_irq(PICCommonState *s)
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{
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int irq;
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@ -144,7 +116,7 @@ static void pic_update_irq(PicState *s)
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/* set irq level. If an edge is detected, then the IRR is set to 1 */
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static void pic_set_irq(void *opaque, int irq, int level)
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{
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PicState *s = opaque;
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PICCommonState *s = opaque;
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int mask = 1 << irq;
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#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT) || \
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@ -192,7 +164,7 @@ static void pic_set_irq(void *opaque, int irq, int level)
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}
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/* acknowledge interrupt 'irq' */
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static void pic_intack(PicState *s, int irq)
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static void pic_intack(PICCommonState *s, int irq)
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{
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if (s->auto_eoi) {
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if (s->rotate_on_auto_eoi) {
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@ -210,7 +182,7 @@ static void pic_intack(PicState *s, int irq)
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int pic_read_irq(DeviceState *d)
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{
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PicState *s = DO_UPCAST(PicState, dev.qdev, d);
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PICCommonState *s = DO_UPCAST(PICCommonState, dev.qdev, d);
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int irq, irq2, intno;
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irq = pic_get_irq(s);
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@ -249,30 +221,15 @@ int pic_read_irq(DeviceState *d)
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return intno;
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}
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static void pic_init_reset(PicState *s)
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static void pic_init_reset(PICCommonState *s)
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{
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s->last_irr = 0;
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s->irr = 0;
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s->imr = 0;
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s->isr = 0;
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s->priority_add = 0;
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s->irq_base = 0;
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s->read_reg_select = 0;
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s->poll = 0;
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s->special_mask = 0;
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s->init_state = 0;
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s->auto_eoi = 0;
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s->rotate_on_auto_eoi = 0;
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s->special_fully_nested_mode = 0;
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s->init4 = 0;
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s->single_mode = 0;
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/* Note: ELCR is not reset */
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pic_reset_common(s);
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pic_update_irq(s);
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}
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static void pic_reset(DeviceState *dev)
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{
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PicState *s = DO_UPCAST(PicState, dev.qdev, dev);
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PICCommonState *s = DO_UPCAST(PICCommonState, dev.qdev, dev);
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pic_init_reset(s);
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s->elcr = 0;
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@ -281,7 +238,7 @@ static void pic_reset(DeviceState *dev)
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static void pic_ioport_write(void *opaque, target_phys_addr_t addr64,
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uint64_t val64, unsigned size)
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{
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PicState *s = opaque;
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PICCommonState *s = opaque;
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uint32_t addr = addr64;
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uint32_t val = val64;
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int priority, cmd, irq;
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@ -375,7 +332,7 @@ static void pic_ioport_write(void *opaque, target_phys_addr_t addr64,
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static uint64_t pic_ioport_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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PicState *s = opaque;
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PICCommonState *s = opaque;
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int ret;
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if (s->poll) {
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@ -404,7 +361,7 @@ static uint64_t pic_ioport_read(void *opaque, target_phys_addr_t addr,
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int pic_get_output(DeviceState *d)
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{
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PicState *s = DO_UPCAST(PicState, dev.qdev, d);
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PICCommonState *s = DO_UPCAST(PICCommonState, dev.qdev, d);
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return (pic_get_irq(s) >= 0);
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}
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@ -412,43 +369,17 @@ int pic_get_output(DeviceState *d)
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static void elcr_ioport_write(void *opaque, target_phys_addr_t addr,
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uint64_t val, unsigned size)
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{
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PicState *s = opaque;
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PICCommonState *s = opaque;
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s->elcr = val & s->elcr_mask;
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}
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static uint64_t elcr_ioport_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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PicState *s = opaque;
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PICCommonState *s = opaque;
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return s->elcr;
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}
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static const VMStateDescription vmstate_pic = {
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.name = "i8259",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8(last_irr, PicState),
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VMSTATE_UINT8(irr, PicState),
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VMSTATE_UINT8(imr, PicState),
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VMSTATE_UINT8(isr, PicState),
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VMSTATE_UINT8(priority_add, PicState),
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VMSTATE_UINT8(irq_base, PicState),
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VMSTATE_UINT8(read_reg_select, PicState),
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VMSTATE_UINT8(poll, PicState),
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VMSTATE_UINT8(special_mask, PicState),
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VMSTATE_UINT8(init_state, PicState),
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VMSTATE_UINT8(auto_eoi, PicState),
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VMSTATE_UINT8(rotate_on_auto_eoi, PicState),
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VMSTATE_UINT8(special_fully_nested_mode, PicState),
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VMSTATE_UINT8(init4, PicState),
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VMSTATE_UINT8(single_mode, PicState),
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VMSTATE_UINT8(elcr, PicState),
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VMSTATE_END_OF_LIST()
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}
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};
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static const MemoryRegionOps pic_base_ioport_ops = {
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.read = pic_ioport_read,
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.write = pic_ioport_write,
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@ -467,36 +398,25 @@ static const MemoryRegionOps pic_elcr_ioport_ops = {
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},
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};
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static int pic_initfn(ISADevice *dev)
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static void pic_init(PICCommonState *s)
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{
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PicState *s = DO_UPCAST(PicState, dev, dev);
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memory_region_init_io(&s->base_io, &pic_base_ioport_ops, s, "pic", 2);
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memory_region_init_io(&s->elcr_io, &pic_elcr_ioport_ops, s, "elcr", 1);
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isa_register_ioport(dev, &s->base_io, s->iobase);
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if (s->elcr_addr != -1) {
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isa_register_ioport(dev, &s->elcr_io, s->elcr_addr);
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}
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qdev_init_gpio_out(&dev->qdev, s->int_out, ARRAY_SIZE(s->int_out));
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qdev_init_gpio_in(&dev->qdev, pic_set_irq, 8);
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qdev_set_legacy_instance_id(&dev->qdev, s->iobase, 1);
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return 0;
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qdev_init_gpio_out(&s->dev.qdev, s->int_out, ARRAY_SIZE(s->int_out));
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qdev_init_gpio_in(&s->dev.qdev, pic_set_irq, 8);
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}
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void pic_info(Monitor *mon)
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{
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int i;
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PicState *s;
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PICCommonState *s;
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if (!isa_pic) {
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return;
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}
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for (i = 0; i < 2; i++) {
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s = i == 0 ? DO_UPCAST(PicState, dev.qdev, isa_pic) : slave_pic;
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s = i == 0 ? DO_UPCAST(PICCommonState, dev.qdev, isa_pic) : slave_pic;
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monitor_printf(mon, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d "
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"irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
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i, s->irr, s->imr, s->isr, s->priority_add,
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@ -531,12 +451,7 @@ qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq)
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irq_set = g_malloc(ISA_NUM_IRQS * sizeof(qemu_irq));
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dev = isa_create(bus, "isa-i8259");
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qdev_prop_set_uint32(&dev->qdev, "iobase", 0x20);
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qdev_prop_set_uint32(&dev->qdev, "elcr_addr", 0x4d0);
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qdev_prop_set_uint8(&dev->qdev, "elcr_mask", 0xf8);
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qdev_prop_set_bit(&dev->qdev, "master", true);
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qdev_init_nofail(&dev->qdev);
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dev = i8259_init_chip("isa-i8259", bus, true);
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qdev_connect_gpio_out(&dev->qdev, 0, parent_irq);
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for (i = 0 ; i < 8; i++) {
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@ -545,40 +460,27 @@ qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq)
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isa_pic = &dev->qdev;
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dev = isa_create(bus, "isa-i8259");
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qdev_prop_set_uint32(&dev->qdev, "iobase", 0xa0);
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qdev_prop_set_uint32(&dev->qdev, "elcr_addr", 0x4d1);
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qdev_prop_set_uint8(&dev->qdev, "elcr_mask", 0xde);
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qdev_init_nofail(&dev->qdev);
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dev = i8259_init_chip("isa-i8259", bus, false);
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qdev_connect_gpio_out(&dev->qdev, 0, irq_set[2]);
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for (i = 0 ; i < 8; i++) {
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irq_set[i + 8] = qdev_get_gpio_in(&dev->qdev, i);
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}
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slave_pic = DO_UPCAST(PicState, dev, dev);
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slave_pic = DO_UPCAST(PICCommonState, dev, dev);
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return irq_set;
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}
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static ISADeviceInfo i8259_info = {
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.qdev.name = "isa-i8259",
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.qdev.size = sizeof(PicState),
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.qdev.vmsd = &vmstate_pic,
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.qdev.reset = pic_reset,
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.qdev.no_user = 1,
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.init = pic_initfn,
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.qdev.props = (Property[]) {
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DEFINE_PROP_HEX32("iobase", PicState, iobase, -1),
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DEFINE_PROP_HEX32("elcr_addr", PicState, elcr_addr, -1),
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DEFINE_PROP_HEX8("elcr_mask", PicState, elcr_mask, -1),
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DEFINE_PROP_BIT("master", PicState, master, 0, false),
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DEFINE_PROP_END_OF_LIST(),
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},
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static PICCommonInfo i8259_info = {
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.isadev.qdev.name = "isa-i8259",
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.isadev.qdev.reset = pic_reset,
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.init = pic_init,
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};
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static void pic_register(void)
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{
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isa_qdev_register(&i8259_info);
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pic_qdev_register(&i8259_info);
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}
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device_init(pic_register)
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147
hw/i8259_common.c
Normal file
147
hw/i8259_common.c
Normal file
@ -0,0 +1,147 @@
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/*
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* QEMU 8259 - common bits of emulated and KVM kernel model
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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* Copyright (c) 2011 Jan Kiszka, Siemens AG
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "pc.h"
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#include "i8259_internal.h"
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void pic_reset_common(PICCommonState *s)
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{
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s->last_irr = 0;
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s->irr = 0;
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s->imr = 0;
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s->isr = 0;
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s->priority_add = 0;
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s->irq_base = 0;
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s->read_reg_select = 0;
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s->poll = 0;
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s->special_mask = 0;
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s->init_state = 0;
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s->auto_eoi = 0;
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s->rotate_on_auto_eoi = 0;
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s->special_fully_nested_mode = 0;
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s->init4 = 0;
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s->single_mode = 0;
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/* Note: ELCR is not reset */
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}
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static void pic_dispatch_pre_save(void *opaque)
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{
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PICCommonState *s = opaque;
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PICCommonInfo *info =
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DO_UPCAST(PICCommonInfo, isadev.qdev, s->dev.qdev.info);
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if (info->pre_save) {
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info->pre_save(s);
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}
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}
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static int pic_dispatch_post_load(void *opaque, int version_id)
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{
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PICCommonState *s = opaque;
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PICCommonInfo *info =
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DO_UPCAST(PICCommonInfo, isadev.qdev, s->dev.qdev.info);
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if (info->post_load) {
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info->post_load(s);
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}
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return 0;
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}
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static int pic_init_common(ISADevice *dev)
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{
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PICCommonState *s = DO_UPCAST(PICCommonState, dev, dev);
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PICCommonInfo *info =
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DO_UPCAST(PICCommonInfo, isadev.qdev, dev->qdev.info);
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info->init(s);
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isa_register_ioport(NULL, &s->base_io, s->iobase);
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if (s->elcr_addr != -1) {
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isa_register_ioport(NULL, &s->elcr_io, s->elcr_addr);
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}
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qdev_set_legacy_instance_id(&s->dev.qdev, s->iobase, 1);
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return 0;
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}
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ISADevice *i8259_init_chip(const char *name, ISABus *bus, bool master)
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{
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ISADevice *dev;
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dev = isa_create(bus, name);
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||||
qdev_prop_set_uint32(&dev->qdev, "iobase", master ? 0x20 : 0xa0);
|
||||
qdev_prop_set_uint32(&dev->qdev, "elcr_addr", master ? 0x4d0 : 0x4d1);
|
||||
qdev_prop_set_uint8(&dev->qdev, "elcr_mask", master ? 0xf8 : 0xde);
|
||||
qdev_prop_set_bit(&dev->qdev, "master", master);
|
||||
qdev_init_nofail(&dev->qdev);
|
||||
|
||||
return dev;
|
||||
}
|
||||
|
||||
static const VMStateDescription vmstate_pic_common = {
|
||||
.name = "i8259",
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.minimum_version_id_old = 1,
|
||||
.pre_save = pic_dispatch_pre_save,
|
||||
.post_load = pic_dispatch_post_load,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_UINT8(last_irr, PICCommonState),
|
||||
VMSTATE_UINT8(irr, PICCommonState),
|
||||
VMSTATE_UINT8(imr, PICCommonState),
|
||||
VMSTATE_UINT8(isr, PICCommonState),
|
||||
VMSTATE_UINT8(priority_add, PICCommonState),
|
||||
VMSTATE_UINT8(irq_base, PICCommonState),
|
||||
VMSTATE_UINT8(read_reg_select, PICCommonState),
|
||||
VMSTATE_UINT8(poll, PICCommonState),
|
||||
VMSTATE_UINT8(special_mask, PICCommonState),
|
||||
VMSTATE_UINT8(init_state, PICCommonState),
|
||||
VMSTATE_UINT8(auto_eoi, PICCommonState),
|
||||
VMSTATE_UINT8(rotate_on_auto_eoi, PICCommonState),
|
||||
VMSTATE_UINT8(special_fully_nested_mode, PICCommonState),
|
||||
VMSTATE_UINT8(init4, PICCommonState),
|
||||
VMSTATE_UINT8(single_mode, PICCommonState),
|
||||
VMSTATE_UINT8(elcr, PICCommonState),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
|
||||
static Property pic_properties_common[] = {
|
||||
DEFINE_PROP_HEX32("iobase", PICCommonState, iobase, -1),
|
||||
DEFINE_PROP_HEX32("elcr_addr", PICCommonState, elcr_addr, -1),
|
||||
DEFINE_PROP_HEX8("elcr_mask", PICCommonState, elcr_mask, -1),
|
||||
DEFINE_PROP_BIT("master", PICCommonState, master, 0, false),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
||||
void pic_qdev_register(PICCommonInfo *info)
|
||||
{
|
||||
info->isadev.init = pic_init_common;
|
||||
info->isadev.qdev.size = sizeof(PICCommonState);
|
||||
info->isadev.qdev.vmsd = &vmstate_pic_common;
|
||||
info->isadev.qdev.no_user = 1;
|
||||
info->isadev.qdev.props = pic_properties_common;
|
||||
isa_qdev_register(&info->isadev);
|
||||
}
|
76
hw/i8259_internal.h
Normal file
76
hw/i8259_internal.h
Normal file
@ -0,0 +1,76 @@
|
||||
/*
|
||||
* QEMU 8259 - internal interfaces
|
||||
*
|
||||
* Copyright (c) 2011 Jan Kiszka, Siemens AG
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef QEMU_I8259_INTERNAL_H
|
||||
#define QEMU_I8259_INTERNAL_H
|
||||
|
||||
#include "hw.h"
|
||||
#include "pc.h"
|
||||
#include "isa.h"
|
||||
|
||||
typedef struct PICCommonState PICCommonState;
|
||||
|
||||
struct PICCommonState {
|
||||
ISADevice dev;
|
||||
uint8_t last_irr; /* edge detection */
|
||||
uint8_t irr; /* interrupt request register */
|
||||
uint8_t imr; /* interrupt mask register */
|
||||
uint8_t isr; /* interrupt service register */
|
||||
uint8_t priority_add; /* highest irq priority */
|
||||
uint8_t irq_base;
|
||||
uint8_t read_reg_select;
|
||||
uint8_t poll;
|
||||
uint8_t special_mask;
|
||||
uint8_t init_state;
|
||||
uint8_t auto_eoi;
|
||||
uint8_t rotate_on_auto_eoi;
|
||||
uint8_t special_fully_nested_mode;
|
||||
uint8_t init4; /* true if 4 byte init */
|
||||
uint8_t single_mode; /* true if slave pic is not initialized */
|
||||
uint8_t elcr; /* PIIX edge/trigger selection*/
|
||||
uint8_t elcr_mask;
|
||||
qemu_irq int_out[1];
|
||||
uint32_t master; /* reflects /SP input pin */
|
||||
uint32_t iobase;
|
||||
uint32_t elcr_addr;
|
||||
MemoryRegion base_io;
|
||||
MemoryRegion elcr_io;
|
||||
};
|
||||
|
||||
typedef struct PICCommonInfo PICCommonInfo;
|
||||
|
||||
struct PICCommonInfo {
|
||||
ISADeviceInfo isadev;
|
||||
void (*init)(PICCommonState *s);
|
||||
void (*pre_save)(PICCommonState *s);
|
||||
void (*post_load)(PICCommonState *s);
|
||||
};
|
||||
|
||||
void pic_reset_common(PICCommonState *s);
|
||||
|
||||
ISADevice *i8259_init_chip(const char *name, ISABus *bus, bool master);
|
||||
|
||||
void pic_qdev_register(PICCommonInfo *info);
|
||||
|
||||
#endif /* !QEMU_I8259_INTERNAL_H */
|
Loading…
Reference in New Issue
Block a user