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target-mips: optimize gen_arith()/gen_arith_imm()
Optimize code generation in gen_arith()/gen_arith_imm(): - Don't do sign extension when the value is already guaranteed to be sign extended (otherwise, results are marked as UNPREDICTABLE). - When the value is sign extended, compare the value to 0 instead of testing bit 31/63. - Temp variables are valid up to and *including* the brcond instruction. Use them instead of temp local variables. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5680 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32
parent
49bcf33cc7
commit
507563e85d
@ -1333,7 +1333,7 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
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switch (opc) {
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case OPC_ADDI:
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{
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TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_TL);
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TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
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TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
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int l1 = gen_new_label();
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@ -1341,24 +1341,21 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
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tcg_gen_ext32s_tl(r_tmp1, t0);
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tcg_gen_addi_tl(t0, r_tmp1, uimm);
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tcg_gen_xori_tl(r_tmp1, r_tmp1, uimm);
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tcg_gen_xori_tl(r_tmp1, r_tmp1, -1);
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tcg_gen_xori_tl(r_tmp1, r_tmp1, ~uimm);
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tcg_gen_xori_tl(r_tmp2, t0, uimm);
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tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);
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tcg_temp_free(r_tmp2);
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tcg_gen_shri_tl(r_tmp1, r_tmp1, 31);
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tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);
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tcg_temp_free(r_tmp1);
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tcg_gen_brcondi_tl(TCG_COND_GE, r_tmp1, 0, l1);
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/* operands of same sign, result different sign */
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generate_exception(ctx, EXCP_OVERFLOW);
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gen_set_label(l1);
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tcg_temp_free(r_tmp1);
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tcg_gen_ext32s_tl(t0, t0);
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}
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opn = "addi";
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break;
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case OPC_ADDIU:
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tcg_gen_ext32s_tl(t0, t0);
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tcg_gen_addi_tl(t0, t0, uimm);
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tcg_gen_ext32s_tl(t0, t0);
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opn = "addiu";
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@ -1366,7 +1363,7 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
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#if defined(TARGET_MIPS64)
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case OPC_DADDI:
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{
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TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_TL);
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TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
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TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
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int l1 = gen_new_label();
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@ -1374,17 +1371,15 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
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tcg_gen_mov_tl(r_tmp1, t0);
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tcg_gen_addi_tl(t0, t0, uimm);
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tcg_gen_xori_tl(r_tmp1, r_tmp1, uimm);
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tcg_gen_xori_tl(r_tmp1, r_tmp1, -1);
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tcg_gen_xori_tl(r_tmp1, r_tmp1, ~uimm);
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tcg_gen_xori_tl(r_tmp2, t0, uimm);
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tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);
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tcg_temp_free(r_tmp2);
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tcg_gen_shri_tl(r_tmp1, r_tmp1, 63);
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tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);
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tcg_temp_free(r_tmp1);
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tcg_gen_brcondi_tl(TCG_COND_GE, r_tmp1, 0, l1);
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/* operands of same sign, result different sign */
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generate_exception(ctx, EXCP_OVERFLOW);
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gen_set_label(l1);
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tcg_temp_free(r_tmp1);
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}
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opn = "daddi";
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break;
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@ -1417,7 +1412,6 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
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opn = "lui";
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break;
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case OPC_SLL:
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tcg_gen_ext32u_tl(t0, t0);
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tcg_gen_shli_tl(t0, t0, uimm);
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tcg_gen_ext32s_tl(t0, t0);
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opn = "sll";
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@ -1425,15 +1419,17 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
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case OPC_SRA:
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tcg_gen_ext32s_tl(t0, t0);
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tcg_gen_sari_tl(t0, t0, uimm);
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tcg_gen_ext32s_tl(t0, t0);
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opn = "sra";
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break;
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case OPC_SRL:
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switch ((ctx->opcode >> 21) & 0x1f) {
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case 0:
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tcg_gen_ext32u_tl(t0, t0);
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tcg_gen_shri_tl(t0, t0, uimm);
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tcg_gen_ext32s_tl(t0, t0);
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if (uimm != 0) {
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tcg_gen_ext32u_tl(t0, t0);
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tcg_gen_shri_tl(t0, t0, uimm);
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} else {
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tcg_gen_ext32s_tl(t0, t0);
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}
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opn = "srl";
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break;
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case 1:
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@ -1449,9 +1445,12 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
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}
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opn = "rotr";
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} else {
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tcg_gen_ext32u_tl(t0, t0);
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tcg_gen_shri_tl(t0, t0, uimm);
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tcg_gen_ext32s_tl(t0, t0);
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if (uimm != 0) {
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tcg_gen_ext32u_tl(t0, t0);
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tcg_gen_shri_tl(t0, t0, uimm);
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} else {
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tcg_gen_ext32s_tl(t0, t0);
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}
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opn = "srl";
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}
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break;
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@ -1562,7 +1561,7 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
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switch (opc) {
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case OPC_ADD:
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{
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TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_TL);
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TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
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TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
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int l1 = gen_new_label();
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@ -1576,27 +1575,24 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
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tcg_gen_xor_tl(r_tmp2, t0, t1);
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tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);
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tcg_temp_free(r_tmp2);
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tcg_gen_shri_tl(r_tmp1, r_tmp1, 31);
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tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);
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tcg_temp_free(r_tmp1);
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tcg_gen_brcondi_tl(TCG_COND_GE, r_tmp1, 0, l1);
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/* operands of same sign, result different sign */
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generate_exception(ctx, EXCP_OVERFLOW);
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gen_set_label(l1);
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tcg_temp_free(r_tmp1);
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tcg_gen_ext32s_tl(t0, t0);
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}
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opn = "add";
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break;
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case OPC_ADDU:
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tcg_gen_ext32s_tl(t0, t0);
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tcg_gen_ext32s_tl(t1, t1);
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tcg_gen_add_tl(t0, t0, t1);
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tcg_gen_ext32s_tl(t0, t0);
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opn = "addu";
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break;
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case OPC_SUB:
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{
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TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_TL);
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TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
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TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
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int l1 = gen_new_label();
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@ -1609,20 +1605,17 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
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tcg_gen_xor_tl(r_tmp1, r_tmp1, t0);
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tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);
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tcg_temp_free(r_tmp2);
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tcg_gen_shri_tl(r_tmp1, r_tmp1, 31);
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tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);
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tcg_temp_free(r_tmp1);
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tcg_gen_brcondi_tl(TCG_COND_GE, r_tmp1, 0, l1);
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/* operands of different sign, first operand and result different sign */
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generate_exception(ctx, EXCP_OVERFLOW);
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gen_set_label(l1);
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tcg_temp_free(r_tmp1);
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tcg_gen_ext32s_tl(t0, t0);
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}
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opn = "sub";
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break;
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case OPC_SUBU:
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tcg_gen_ext32s_tl(t0, t0);
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tcg_gen_ext32s_tl(t1, t1);
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tcg_gen_sub_tl(t0, t0, t1);
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tcg_gen_ext32s_tl(t0, t0);
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opn = "subu";
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@ -1630,7 +1623,7 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
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#if defined(TARGET_MIPS64)
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case OPC_DADD:
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{
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TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_TL);
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TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
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TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
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int l1 = gen_new_label();
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@ -1643,12 +1636,11 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
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tcg_gen_xor_tl(r_tmp2, t0, t1);
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tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);
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tcg_temp_free(r_tmp2);
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tcg_gen_shri_tl(r_tmp1, r_tmp1, 63);
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tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);
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tcg_temp_free(r_tmp1);
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tcg_gen_brcondi_tl(TCG_COND_GE, r_tmp1, 0, l1);
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/* operands of same sign, result different sign */
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generate_exception(ctx, EXCP_OVERFLOW);
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gen_set_label(l1);
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tcg_temp_free(r_tmp1);
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}
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opn = "dadd";
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break;
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@ -1658,7 +1650,7 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
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break;
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case OPC_DSUB:
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{
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TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_TL);
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TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
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TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
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int l1 = gen_new_label();
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@ -1670,12 +1662,11 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
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tcg_gen_xor_tl(r_tmp1, r_tmp1, t0);
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tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);
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tcg_temp_free(r_tmp2);
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tcg_gen_shri_tl(r_tmp1, r_tmp1, 63);
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tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);
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tcg_temp_free(r_tmp1);
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tcg_gen_brcondi_tl(TCG_COND_GE, r_tmp1, 0, l1);
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/* operands of different sign, first operand and result different sign */
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generate_exception(ctx, EXCP_OVERFLOW);
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gen_set_label(l1);
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tcg_temp_free(r_tmp1);
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}
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opn = "dsub";
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break;
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@ -1710,8 +1701,6 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
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opn = "xor";
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break;
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case OPC_MUL:
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tcg_gen_ext32s_tl(t0, t0);
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tcg_gen_ext32s_tl(t1, t1);
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tcg_gen_mul_tl(t0, t0, t1);
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tcg_gen_ext32s_tl(t0, t0);
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opn = "mul";
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@ -1737,8 +1726,6 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
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opn = "movz";
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goto print;
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case OPC_SLLV:
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tcg_gen_ext32u_tl(t0, t0);
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tcg_gen_ext32u_tl(t1, t1);
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tcg_gen_andi_tl(t0, t0, 0x1f);
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tcg_gen_shl_tl(t0, t1, t0);
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tcg_gen_ext32s_tl(t0, t0);
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@ -1748,7 +1735,6 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
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tcg_gen_ext32s_tl(t1, t1);
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tcg_gen_andi_tl(t0, t0, 0x1f);
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tcg_gen_sar_tl(t0, t1, t0);
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tcg_gen_ext32s_tl(t0, t0);
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opn = "srav";
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break;
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case OPC_SRLV:
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