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target-arm: lpae: Replace tsz with computed inputsize
Remove the tsz variable and introduce inputsize. This simplifies the code a little and makes it easier to compare with the reference manuals. No functional change. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1445864527-14520-6-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -6481,7 +6481,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
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uint32_t level = 1;
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uint32_t epd = 0;
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int32_t t0sz, t1sz;
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int32_t tsz;
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uint32_t tg;
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uint64_t ttbr;
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int ttbr_select;
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@ -6491,6 +6490,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
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uint32_t attrs;
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int32_t granule_sz = 9;
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int32_t va_size = 32;
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int inputsize;
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int32_t tbi = 0;
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TCR *tcr = regime_tcr(env, mmu_idx);
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int ap, ns, xn, pxn;
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@ -6593,7 +6593,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
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if (el < 2) {
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epd = extract32(tcr->raw_tcr, 7, 1);
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}
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tsz = t0sz;
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inputsize = va_size - t0sz;
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tg = extract32(tcr->raw_tcr, 14, 2);
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if (tg == 1) { /* 64KB pages */
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@ -6608,7 +6608,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
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ttbr = regime_ttbr(env, mmu_idx, 1);
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epd = extract32(tcr->raw_tcr, 23, 1);
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tsz = t1sz;
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inputsize = va_size - t1sz;
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tg = extract32(tcr->raw_tcr, 30, 2);
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if (tg == 3) { /* 64KB pages */
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@ -6620,7 +6620,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
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}
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/* Here we should have set up all the parameters for the translation:
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* va_size, ttbr, epd, tsz, granule_sz, tbi
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* va_size, inputsize, ttbr, epd, granule_sz, tbi
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*/
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if (epd) {
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@ -6635,27 +6635,27 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
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* of strides (granule_sz bits at a time) needed to consume the bits
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* of the input address. In the pseudocode this is:
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* level = 4 - RoundUp((inputsize - grainsize) / stride)
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* where their 'inputsize' is our 'va_size - tsz', 'grainsize' is
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* where their 'inputsize' is our 'inputsize', 'grainsize' is
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* our 'granule_sz + 3' and 'stride' is our 'granule_sz'.
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* Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
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* = 4 - (va_size - tsz - granule_sz - 3 + granule_sz - 1) / granule_sz
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* = 4 - (va_size - tsz - 4) / granule_sz;
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* = 4 - (inputsize - granule_sz - 3 + granule_sz - 1) / granule_sz
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* = 4 - (inputsize - 4) / granule_sz;
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*/
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level = 4 - (va_size - tsz - 4) / granule_sz;
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level = 4 - (inputsize - 4) / granule_sz;
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/* Clear the vaddr bits which aren't part of the within-region address,
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* so that we don't have to special case things when calculating the
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* first descriptor address.
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*/
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if (tsz) {
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address &= (1ULL << (va_size - tsz)) - 1;
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if (va_size != inputsize) {
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address &= (1ULL << inputsize) - 1;
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}
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descmask = (1ULL << (granule_sz + 3)) - 1;
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/* Now we can extract the actual base address from the TTBR */
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descaddr = extract64(ttbr, 0, 48);
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descaddr &= ~((1ULL << (va_size - tsz - (granule_sz * (4 - level)))) - 1);
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descaddr &= ~((1ULL << (inputsize - (granule_sz * (4 - level)))) - 1);
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/* Secure accesses start with the page table in secure memory and
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* can be downgraded to non-secure at any step. Non-secure accesses
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