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hw/xen/xen_pt: Confine igd-passthrough-isa-bridge to XEN
igd-passthrough-isa-bridge is only requested in xen_pt but was implemented in pc_piix.c. This caused xen_pt to dependend on i386/pc which is hereby resolved. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Acked-by: Anthony PERARD <anthony.perard@citrix.com> Message-Id: <20220326165825.30794-2-shentey@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Bernhard Beschow
Paolo Bonzini
parent
354d2d9b87
commit
4a8027363e
@ -813,124 +813,6 @@ static void pc_i440fx_1_4_machine_options(MachineClass *m)
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DEFINE_I440FX_MACHINE(v1_4, "pc-i440fx-1.4", pc_compat_1_4_fn,
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pc_i440fx_1_4_machine_options);
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typedef struct {
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uint16_t gpu_device_id;
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uint16_t pch_device_id;
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uint8_t pch_revision_id;
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} IGDDeviceIDInfo;
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/* In real world different GPU should have different PCH. But actually
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* the different PCH DIDs likely map to different PCH SKUs. We do the
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* same thing for the GPU. For PCH, the different SKUs are going to be
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* all the same silicon design and implementation, just different
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* features turn on and off with fuses. The SW interfaces should be
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* consistent across all SKUs in a given family (eg LPT). But just same
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* features may not be supported.
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*
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* Most of these different PCH features probably don't matter to the
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* Gfx driver, but obviously any difference in display port connections
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* will so it should be fine with any PCH in case of passthrough.
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*
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* So currently use one PCH version, 0x8c4e, to cover all HSW(Haswell)
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* scenarios, 0x9cc3 for BDW(Broadwell).
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*/
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static const IGDDeviceIDInfo igd_combo_id_infos[] = {
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/* HSW Classic */
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{0x0402, 0x8c4e, 0x04}, /* HSWGT1D, HSWD_w7 */
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{0x0406, 0x8c4e, 0x04}, /* HSWGT1M, HSWM_w7 */
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{0x0412, 0x8c4e, 0x04}, /* HSWGT2D, HSWD_w7 */
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{0x0416, 0x8c4e, 0x04}, /* HSWGT2M, HSWM_w7 */
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{0x041E, 0x8c4e, 0x04}, /* HSWGT15D, HSWD_w7 */
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/* HSW ULT */
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{0x0A06, 0x8c4e, 0x04}, /* HSWGT1UT, HSWM_w7 */
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{0x0A16, 0x8c4e, 0x04}, /* HSWGT2UT, HSWM_w7 */
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{0x0A26, 0x8c4e, 0x06}, /* HSWGT3UT, HSWM_w7 */
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{0x0A2E, 0x8c4e, 0x04}, /* HSWGT3UT28W, HSWM_w7 */
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{0x0A1E, 0x8c4e, 0x04}, /* HSWGT2UX, HSWM_w7 */
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{0x0A0E, 0x8c4e, 0x04}, /* HSWGT1ULX, HSWM_w7 */
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/* HSW CRW */
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{0x0D26, 0x8c4e, 0x04}, /* HSWGT3CW, HSWM_w7 */
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{0x0D22, 0x8c4e, 0x04}, /* HSWGT3CWDT, HSWD_w7 */
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/* HSW Server */
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{0x041A, 0x8c4e, 0x04}, /* HSWSVGT2, HSWD_w7 */
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/* HSW SRVR */
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{0x040A, 0x8c4e, 0x04}, /* HSWSVGT1, HSWD_w7 */
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/* BSW */
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{0x1606, 0x9cc3, 0x03}, /* BDWULTGT1, BDWM_w7 */
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{0x1616, 0x9cc3, 0x03}, /* BDWULTGT2, BDWM_w7 */
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{0x1626, 0x9cc3, 0x03}, /* BDWULTGT3, BDWM_w7 */
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{0x160E, 0x9cc3, 0x03}, /* BDWULXGT1, BDWM_w7 */
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{0x161E, 0x9cc3, 0x03}, /* BDWULXGT2, BDWM_w7 */
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{0x1602, 0x9cc3, 0x03}, /* BDWHALOGT1, BDWM_w7 */
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{0x1612, 0x9cc3, 0x03}, /* BDWHALOGT2, BDWM_w7 */
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{0x1622, 0x9cc3, 0x03}, /* BDWHALOGT3, BDWM_w7 */
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{0x162B, 0x9cc3, 0x03}, /* BDWHALO28W, BDWM_w7 */
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{0x162A, 0x9cc3, 0x03}, /* BDWGT3WRKS, BDWM_w7 */
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{0x162D, 0x9cc3, 0x03}, /* BDWGT3SRVR, BDWM_w7 */
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};
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static void isa_bridge_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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dc->desc = "ISA bridge faked to support IGD PT";
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set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
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k->vendor_id = PCI_VENDOR_ID_INTEL;
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k->class_id = PCI_CLASS_BRIDGE_ISA;
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};
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static const TypeInfo isa_bridge_info = {
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.name = "igd-passthrough-isa-bridge",
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PCIDevice),
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.class_init = isa_bridge_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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},
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};
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static void pt_graphics_register_types(void)
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{
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type_register_static(&isa_bridge_info);
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}
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type_init(pt_graphics_register_types)
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void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id)
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{
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struct PCIDevice *bridge_dev;
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int i, num;
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uint16_t pch_dev_id = 0xffff;
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uint8_t pch_rev_id = 0;
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num = ARRAY_SIZE(igd_combo_id_infos);
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for (i = 0; i < num; i++) {
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if (gpu_dev_id == igd_combo_id_infos[i].gpu_device_id) {
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pch_dev_id = igd_combo_id_infos[i].pch_device_id;
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pch_rev_id = igd_combo_id_infos[i].pch_revision_id;
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}
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}
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if (pch_dev_id == 0xffff) {
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return;
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}
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/* Currently IGD drivers always need to access PCH by 1f.0. */
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bridge_dev = pci_create_simple(bus, PCI_DEVFN(0x1f, 0),
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"igd-passthrough-isa-bridge");
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/*
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* Note that vendor id is always PCI_VENDOR_ID_INTEL.
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*/
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if (!bridge_dev) {
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fprintf(stderr, "set igd-passthrough-isa-bridge failed!\n");
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return;
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}
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pci_config_set_device_id(bridge_dev->config, pch_dev_id);
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pci_config_set_revision(bridge_dev->config, pch_rev_id);
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}
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#ifdef CONFIG_ISAPC
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static void isapc_machine_options(MachineClass *m)
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{
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@ -60,7 +60,6 @@
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#include "hw/qdev-properties.h"
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#include "hw/qdev-properties-system.h"
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#include "hw/xen/xen.h"
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#include "hw/i386/pc.h"
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#include "hw/xen/xen-legacy-backend.h"
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#include "xen_pt.h"
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#include "qemu/range.h"
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@ -43,6 +43,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(XenPCIPassthroughState, XEN_PT_DEVICE)
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uint32_t igd_read_opregion(XenPCIPassthroughState *s);
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void igd_write_opregion(XenPCIPassthroughState *s, uint32_t val);
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void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id);
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/* function type for config reg */
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typedef int (*xen_pt_conf_reg_init)
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@ -289,3 +289,122 @@ void igd_write_opregion(XenPCIPassthroughState *s, uint32_t val)
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(unsigned long)(igd_host_opregion >> XC_PAGE_SHIFT),
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(unsigned long)(igd_guest_opregion >> XC_PAGE_SHIFT));
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}
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typedef struct {
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uint16_t gpu_device_id;
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uint16_t pch_device_id;
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uint8_t pch_revision_id;
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} IGDDeviceIDInfo;
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/*
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* In real world different GPU should have different PCH. But actually
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* the different PCH DIDs likely map to different PCH SKUs. We do the
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* same thing for the GPU. For PCH, the different SKUs are going to be
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* all the same silicon design and implementation, just different
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* features turn on and off with fuses. The SW interfaces should be
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* consistent across all SKUs in a given family (eg LPT). But just same
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* features may not be supported.
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*
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* Most of these different PCH features probably don't matter to the
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* Gfx driver, but obviously any difference in display port connections
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* will so it should be fine with any PCH in case of passthrough.
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*
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* So currently use one PCH version, 0x8c4e, to cover all HSW(Haswell)
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* scenarios, 0x9cc3 for BDW(Broadwell).
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*/
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static const IGDDeviceIDInfo igd_combo_id_infos[] = {
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/* HSW Classic */
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{0x0402, 0x8c4e, 0x04}, /* HSWGT1D, HSWD_w7 */
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{0x0406, 0x8c4e, 0x04}, /* HSWGT1M, HSWM_w7 */
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{0x0412, 0x8c4e, 0x04}, /* HSWGT2D, HSWD_w7 */
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{0x0416, 0x8c4e, 0x04}, /* HSWGT2M, HSWM_w7 */
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{0x041E, 0x8c4e, 0x04}, /* HSWGT15D, HSWD_w7 */
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/* HSW ULT */
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{0x0A06, 0x8c4e, 0x04}, /* HSWGT1UT, HSWM_w7 */
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{0x0A16, 0x8c4e, 0x04}, /* HSWGT2UT, HSWM_w7 */
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{0x0A26, 0x8c4e, 0x06}, /* HSWGT3UT, HSWM_w7 */
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{0x0A2E, 0x8c4e, 0x04}, /* HSWGT3UT28W, HSWM_w7 */
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{0x0A1E, 0x8c4e, 0x04}, /* HSWGT2UX, HSWM_w7 */
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{0x0A0E, 0x8c4e, 0x04}, /* HSWGT1ULX, HSWM_w7 */
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/* HSW CRW */
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{0x0D26, 0x8c4e, 0x04}, /* HSWGT3CW, HSWM_w7 */
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{0x0D22, 0x8c4e, 0x04}, /* HSWGT3CWDT, HSWD_w7 */
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/* HSW Server */
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{0x041A, 0x8c4e, 0x04}, /* HSWSVGT2, HSWD_w7 */
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/* HSW SRVR */
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{0x040A, 0x8c4e, 0x04}, /* HSWSVGT1, HSWD_w7 */
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/* BSW */
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{0x1606, 0x9cc3, 0x03}, /* BDWULTGT1, BDWM_w7 */
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{0x1616, 0x9cc3, 0x03}, /* BDWULTGT2, BDWM_w7 */
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{0x1626, 0x9cc3, 0x03}, /* BDWULTGT3, BDWM_w7 */
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{0x160E, 0x9cc3, 0x03}, /* BDWULXGT1, BDWM_w7 */
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{0x161E, 0x9cc3, 0x03}, /* BDWULXGT2, BDWM_w7 */
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{0x1602, 0x9cc3, 0x03}, /* BDWHALOGT1, BDWM_w7 */
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{0x1612, 0x9cc3, 0x03}, /* BDWHALOGT2, BDWM_w7 */
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{0x1622, 0x9cc3, 0x03}, /* BDWHALOGT3, BDWM_w7 */
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{0x162B, 0x9cc3, 0x03}, /* BDWHALO28W, BDWM_w7 */
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{0x162A, 0x9cc3, 0x03}, /* BDWGT3WRKS, BDWM_w7 */
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{0x162D, 0x9cc3, 0x03}, /* BDWGT3SRVR, BDWM_w7 */
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};
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static void isa_bridge_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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dc->desc = "ISA bridge faked to support IGD PT";
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set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
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k->vendor_id = PCI_VENDOR_ID_INTEL;
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k->class_id = PCI_CLASS_BRIDGE_ISA;
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};
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static const TypeInfo isa_bridge_info = {
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.name = "igd-passthrough-isa-bridge",
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PCIDevice),
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.class_init = isa_bridge_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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},
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};
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static void pt_graphics_register_types(void)
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{
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type_register_static(&isa_bridge_info);
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}
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type_init(pt_graphics_register_types)
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void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id)
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{
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struct PCIDevice *bridge_dev;
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int i, num;
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uint16_t pch_dev_id = 0xffff;
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uint8_t pch_rev_id = 0;
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num = ARRAY_SIZE(igd_combo_id_infos);
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for (i = 0; i < num; i++) {
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if (gpu_dev_id == igd_combo_id_infos[i].gpu_device_id) {
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pch_dev_id = igd_combo_id_infos[i].pch_device_id;
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pch_rev_id = igd_combo_id_infos[i].pch_revision_id;
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}
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}
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if (pch_dev_id == 0xffff) {
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return;
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}
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/* Currently IGD drivers always need to access PCH by 1f.0. */
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bridge_dev = pci_create_simple(bus, PCI_DEVFN(0x1f, 0),
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"igd-passthrough-isa-bridge");
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/*
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* Note that vendor id is always PCI_VENDOR_ID_INTEL.
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*/
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if (!bridge_dev) {
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fprintf(stderr, "set igd-passthrough-isa-bridge failed!\n");
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return;
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}
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pci_config_set_device_id(bridge_dev->config, pch_dev_id);
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pci_config_set_revision(bridge_dev->config, pch_rev_id);
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}
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@ -315,5 +315,4 @@ extern const size_t pc_compat_1_4_len;
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} \
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type_init(pc_machine_init_##suffix)
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extern void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id);
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#endif
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