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Initial OMAP I^2C controller implementation (communication not tested).
Correct an i2c_start_transfer comment. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3514 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
balrog
parent
f34c417ba6
commit
4a2c8ac2bc
3
hw/i2c.c
3
hw/i2c.c
@ -51,8 +51,7 @@ int i2c_bus_busy(i2c_bus *bus)
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return bus->current_dev != NULL;
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}
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/* Returns nonzero if the bus is already busy, or is the address is not
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valid. */
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/* Returns non-zero if the address is not valid. */
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/* TODO: Make this handle multiple masters. */
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int i2c_start_transfer(i2c_bus *bus, int address, int recv)
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{
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420
hw/omap.c
420
hw/omap.c
@ -3603,6 +3603,421 @@ static void omap_pwt_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
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cpu_register_physical_memory(s->pwt.base, 0x800, iomemtype);
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}
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/* Inter-Integrated Circuit Controller (only the "New I2C") */
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struct omap_i2c_s {
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target_phys_addr_t base;
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qemu_irq irq;
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qemu_irq drq[2];
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i2c_slave slave;
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i2c_bus *bus;
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uint8_t mask;
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uint16_t stat;
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uint16_t dma;
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uint16_t count;
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int count_cur;
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uint32_t fifo;
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int rxlen;
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int txlen;
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uint16_t control;
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uint16_t addr[2];
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uint8_t divider;
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uint8_t times[2];
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uint16_t test;
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};
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static void omap_i2c_interrupts_update(struct omap_i2c_s *s)
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{
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qemu_set_irq(s->irq, s->stat & s->mask);
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if ((s->dma >> 15) & 1) /* RDMA_EN */
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qemu_set_irq(s->drq[0], (s->stat >> 3) & 1); /* RRDY */
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if ((s->dma >> 7) & 1) /* XDMA_EN */
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qemu_set_irq(s->drq[1], (s->stat >> 4) & 1); /* XRDY */
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}
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/* These are only stubs now. */
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static void omap_i2c_event(i2c_slave *i2c, enum i2c_event event)
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{
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struct omap_i2c_s *s = (struct omap_i2c_s *) i2c;
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if ((~s->control >> 15) & 1) /* I2C_EN */
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return;
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switch (event) {
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case I2C_START_SEND:
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case I2C_START_RECV:
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s->stat |= 1 << 9; /* AAS */
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break;
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case I2C_FINISH:
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s->stat |= 1 << 2; /* ARDY */
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break;
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case I2C_NACK:
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s->stat |= 1 << 1; /* NACK */
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break;
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}
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omap_i2c_interrupts_update(s);
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}
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static int omap_i2c_rx(i2c_slave *i2c)
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{
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struct omap_i2c_s *s = (struct omap_i2c_s *) i2c;
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uint8_t ret = 0;
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if ((~s->control >> 15) & 1) /* I2C_EN */
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return -1;
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if (s->txlen)
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ret = s->fifo >> ((-- s->txlen) << 3) & 0xff;
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else
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s->stat |= 1 << 10; /* XUDF */
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s->stat |= 1 << 4; /* XRDY */
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omap_i2c_interrupts_update(s);
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return ret;
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}
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static int omap_i2c_tx(i2c_slave *i2c, uint8_t data)
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{
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struct omap_i2c_s *s = (struct omap_i2c_s *) i2c;
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if ((~s->control >> 15) & 1) /* I2C_EN */
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return 1;
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if (s->rxlen < 4)
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s->fifo |= data << ((s->rxlen ++) << 3);
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else
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s->stat |= 1 << 11; /* ROVR */
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s->stat |= 1 << 3; /* RRDY */
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omap_i2c_interrupts_update(s);
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return 1;
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}
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static void omap_i2c_fifo_run(struct omap_i2c_s *s)
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{
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int ack = 1;
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if (!i2c_bus_busy(s->bus))
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return;
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if ((s->control >> 2) & 1) { /* RM */
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if ((s->control >> 1) & 1) { /* STP */
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i2c_end_transfer(s->bus);
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s->control &= ~(1 << 1); /* STP */
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s->count_cur = s->count;
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} else if ((s->control >> 9) & 1) { /* TRX */
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while (ack && s->txlen)
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ack = (i2c_send(s->bus,
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(s->fifo >> ((-- s->txlen) << 3)) &
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0xff) >= 0);
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s->stat |= 1 << 4; /* XRDY */
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} else {
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while (s->rxlen < 4)
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s->fifo |= i2c_recv(s->bus) << ((s->rxlen ++) << 3);
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s->stat |= 1 << 3; /* RRDY */
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}
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} else {
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if ((s->control >> 9) & 1) { /* TRX */
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while (ack && s->count_cur && s->txlen) {
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ack = (i2c_send(s->bus,
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(s->fifo >> ((-- s->txlen) << 3)) &
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0xff) >= 0);
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s->count_cur --;
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}
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if (ack && s->count_cur)
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s->stat |= 1 << 4; /* XRDY */
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if (!s->count_cur) {
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s->stat |= 1 << 2; /* ARDY */
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s->control &= ~(1 << 10); /* MST */
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}
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} else {
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while (s->count_cur && s->rxlen < 4) {
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s->fifo |= i2c_recv(s->bus) << ((s->rxlen ++) << 3);
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s->count_cur --;
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}
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if (s->rxlen)
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s->stat |= 1 << 3; /* RRDY */
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}
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if (!s->count_cur) {
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if ((s->control >> 1) & 1) { /* STP */
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i2c_end_transfer(s->bus);
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s->control &= ~(1 << 1); /* STP */
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s->count_cur = s->count;
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} else {
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s->stat |= 1 << 2; /* ARDY */
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s->control &= ~(1 << 10); /* MST */
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}
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}
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}
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s->stat |= (!ack) << 1; /* NACK */
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if (!ack)
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s->control &= ~(1 << 1); /* STP */
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}
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static void omap_i2c_reset(struct omap_i2c_s *s)
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{
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s->mask = 0;
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s->stat = 0;
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s->dma = 0;
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s->count = 0;
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s->count_cur = 0;
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s->fifo = 0;
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s->rxlen = 0;
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s->txlen = 0;
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s->control = 0;
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s->addr[0] = 0;
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s->addr[1] = 0;
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s->divider = 0;
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s->times[0] = 0;
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s->times[1] = 0;
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s->test = 0;
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}
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static uint32_t omap_i2c_read(void *opaque, target_phys_addr_t addr)
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{
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struct omap_i2c_s *s = (struct omap_i2c_s *) opaque;
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int offset = addr - s->base;
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uint16_t ret;
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switch (offset) {
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case 0x00: /* I2C_REV */
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/* TODO: set a value greater or equal to real hardware */
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return 0x11; /* REV */
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case 0x04: /* I2C_IE */
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return s->mask;
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case 0x08: /* I2C_STAT */
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return s->stat | (i2c_bus_busy(s->bus) << 12);
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case 0x0c: /* I2C_IV */
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ret = ffs(s->stat & s->mask);
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if (ret)
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s->stat ^= 1 << (ret - 1);
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omap_i2c_interrupts_update(s);
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return ret;
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case 0x14: /* I2C_BUF */
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return s->dma;
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case 0x18: /* I2C_CNT */
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return s->count_cur; /* DCOUNT */
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case 0x1c: /* I2C_DATA */
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ret = 0;
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if (s->control & (1 << 14)) { /* BE */
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ret |= ((s->fifo >> 0) & 0xff) << 8;
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ret |= ((s->fifo >> 8) & 0xff) << 0;
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} else {
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ret |= ((s->fifo >> 8) & 0xff) << 8;
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ret |= ((s->fifo >> 0) & 0xff) << 0;
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}
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if (s->rxlen == 1) {
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s->stat |= 1 << 15; /* SBD */
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s->rxlen = 0;
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} else if (s->rxlen > 1) {
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if (s->rxlen > 2)
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s->fifo >>= 16;
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s->rxlen -= 2;
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} else
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/* XXX: remote access (qualifier) error - what's that? */;
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if (!s->rxlen) {
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s->stat |= ~(1 << 3); /* RRDY */
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if (((s->control >> 10) & 1) && /* MST */
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((~s->control >> 9) & 1)) { /* TRX */
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s->stat |= 1 << 2; /* ARDY */
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s->control &= ~(1 << 10); /* MST */
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}
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}
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s->stat &= ~(1 << 11); /* ROVR */
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omap_i2c_fifo_run(s);
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omap_i2c_interrupts_update(s);
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return ret;
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case 0x24: /* I2C_CON */
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return s->control;
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case 0x28: /* I2C_OA */
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return s->addr[0];
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case 0x2c: /* I2C_SA */
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return s->addr[1];
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case 0x30: /* I2C_PSC */
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return s->divider;
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case 0x34: /* I2C_SCLL */
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return s->times[0];
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case 0x38: /* I2C_SCLH */
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return s->times[1];
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case 0x3c: /* I2C_SYSTEST */
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if (s->test & (1 << 15)) { /* ST_EN */
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s->test ^= 0xa;
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return s->test;
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} else
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return s->test & ~0x300f;
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}
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OMAP_BAD_REG(addr);
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return 0;
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}
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static void omap_i2c_write(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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struct omap_i2c_s *s = (struct omap_i2c_s *) opaque;
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int offset = addr - s->base;
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int nack;
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switch (offset) {
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case 0x00: /* I2C_REV */
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case 0x08: /* I2C_STAT */
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case 0x0c: /* I2C_IV */
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OMAP_BAD_REG(addr);
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return;
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case 0x04: /* I2C_IE */
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s->mask = value & 0x1f;
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break;
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case 0x14: /* I2C_BUF */
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s->dma = value & 0x8080;
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if (value & (1 << 15)) /* RDMA_EN */
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s->mask &= ~(1 << 3); /* RRDY_IE */
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if (value & (1 << 7)) /* XDMA_EN */
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s->mask &= ~(1 << 4); /* XRDY_IE */
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break;
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case 0x18: /* I2C_CNT */
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s->count = value; /* DCOUNT */
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break;
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case 0x1c: /* I2C_DATA */
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if (s->txlen > 2) {
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/* XXX: remote access (qualifier) error - what's that? */
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break;
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}
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s->fifo <<= 16;
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s->txlen += 2;
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if (s->control & (1 << 14)) { /* BE */
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s->fifo |= ((value >> 8) & 0xff) << 8;
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s->fifo |= ((value >> 0) & 0xff) << 0;
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} else {
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s->fifo |= ((value >> 0) & 0xff) << 8;
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s->fifo |= ((value >> 8) & 0xff) << 0;
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}
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s->stat &= ~(1 << 10); /* XUDF */
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if (s->txlen > 2)
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s->stat &= ~(1 << 4); /* XRDY */
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omap_i2c_fifo_run(s);
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omap_i2c_interrupts_update(s);
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break;
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case 0x24: /* I2C_CON */
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s->control = value & 0xcf07;
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if (~value & (1 << 15)) { /* I2C_EN */
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omap_i2c_reset(s);
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break;
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}
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if (~value & (1 << 10)) { /* MST */
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printf("%s: I^2C slave mode not supported\n", __FUNCTION__);
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break;
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}
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if (value & (1 << 9)) { /* XA */
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printf("%s: 10-bit addressing mode not supported\n", __FUNCTION__);
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break;
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}
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if (value & (1 << 0)) { /* STT */
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nack = !!i2c_start_transfer(s->bus, s->addr[1], /* SA */
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(~value >> 9) & 1); /* TRX */
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s->stat |= nack << 1; /* NACK */
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s->control &= ~(1 << 0); /* STT */
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if (nack)
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s->control &= ~(1 << 1); /* STP */
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else
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omap_i2c_fifo_run(s);
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omap_i2c_interrupts_update(s);
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}
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break;
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case 0x28: /* I2C_OA */
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s->addr[0] = value & 0x3ff;
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i2c_set_slave_address(&s->slave, value & 0x7f);
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break;
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case 0x2c: /* I2C_SA */
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s->addr[1] = value & 0x3ff;
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break;
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case 0x30: /* I2C_PSC */
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s->divider = value;
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break;
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case 0x34: /* I2C_SCLL */
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s->times[0] = value;
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break;
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case 0x38: /* I2C_SCLH */
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s->times[1] = value;
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break;
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case 0x3c: /* I2C_SYSTEST */
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s->test = value & 0xf00f;
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if (value & (1 << 15)) /* ST_EN */
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printf("%s: System Test not supported\n", __FUNCTION__);
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break;
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default:
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OMAP_BAD_REG(addr);
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return;
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}
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}
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static CPUReadMemoryFunc *omap_i2c_readfn[] = {
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omap_badwidth_read16,
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omap_i2c_read,
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omap_badwidth_read16,
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};
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static CPUWriteMemoryFunc *omap_i2c_writefn[] = {
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omap_badwidth_write16,
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omap_i2c_write,
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omap_i2c_write, /* TODO: Only the last fifo write can be 8 bit. */
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};
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struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
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qemu_irq irq, qemu_irq *dma, omap_clk clk)
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{
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int iomemtype;
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struct omap_i2c_s *s = (struct omap_i2c_s *)
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qemu_mallocz(sizeof(struct omap_i2c_s));
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s->base = base;
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s->irq = irq;
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s->drq[0] = dma[0];
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s->drq[1] = dma[1];
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s->slave.event = omap_i2c_event;
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s->slave.recv = omap_i2c_rx;
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s->slave.send = omap_i2c_tx;
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s->bus = i2c_init_bus();
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omap_i2c_reset(s);
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iomemtype = cpu_register_io_memory(0, omap_i2c_readfn,
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omap_i2c_writefn, s);
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cpu_register_physical_memory(s->base, 0x800, iomemtype);
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return s;
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}
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i2c_bus *omap_i2c_bus(struct omap_i2c_s *s)
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{
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return s->bus;
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}
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/* General chip reset */
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static void omap_mpu_reset(void *opaque)
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{
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@ -3634,6 +4049,8 @@ static void omap_mpu_reset(void *opaque)
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omap_gpio_reset(mpu->gpio);
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omap_uwire_reset(mpu->microwire);
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omap_pwl_reset(mpu);
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omap_pwt_reset(mpu);
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omap_i2c_reset(mpu->i2c);
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cpu_reset(mpu->env);
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}
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@ -3758,6 +4175,9 @@ struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
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omap_pwl_init(0xfffb5800, s, omap_findclk(s, "clk32-kHz"));
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omap_pwt_init(0xfffb6000, s, omap_findclk(s, "xtal_osc_12m"));
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s->i2c = omap_i2c_init(0xfffb3800, s->irq[1][OMAP_INT_I2C],
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&s->drq[OMAP_DMA_I2C_RX], omap_findclk(s, "mpuper_ck"));
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||||
|
||||
qemu_register_reset(omap_mpu_reset, s);
|
||||
|
||||
return s;
|
||||
|
||||
@ -475,6 +475,11 @@ struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
|
||||
void omap_uwire_attach(struct omap_uwire_s *s,
|
||||
struct uwire_slave_s *slave, int chipselect);
|
||||
|
||||
struct omap_i2c_s;
|
||||
struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
|
||||
qemu_irq irq, qemu_irq *dma, omap_clk clk);
|
||||
i2c_bus *omap_i2c_bus(struct omap_i2c_s *s);
|
||||
|
||||
/* omap_lcdc.c */
|
||||
struct omap_lcd_panel_s;
|
||||
void omap_lcdc_reset(struct omap_lcd_panel_s *s);
|
||||
@ -550,6 +555,8 @@ struct omap_mpu_state_s {
|
||||
omap_clk clk;
|
||||
} pwt;
|
||||
|
||||
struct omap_i2c_s *i2c;
|
||||
|
||||
/* MPU private TIPB peripherals */
|
||||
struct omap_intr_handler_s *ih[2];
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user