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tcg/ppc: Update vector support for VSX
The VSX instruction set instructions include double-word loads and
stores, double-word load and splat, double-word permute, and bit
select. All of which require multiple operations in the Altivec
instruction set.
Because the VSX registers map %vsr32 to %vr0, and we have no current
intention or need to use vector registers outside %vr0-%vr19, force
on the {ax,bx,cx,tx} bits within the added VSX insns so that we don't
have to otherwise modify the VR[TABC] macros.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
This commit is contained in:
Richard Henderson
parent
68f340d4cd
commit
47c906ae6f
@ -66,6 +66,7 @@ typedef enum {
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extern TCGPowerISA have_isa;
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extern bool have_altivec;
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extern bool have_vsx;
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#define have_isa_2_06 (have_isa >= tcg_isa_2_06)
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#define have_isa_3_00 (have_isa >= tcg_isa_3_00)
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@ -149,7 +150,7 @@ extern bool have_altivec;
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* instruction and substituting two 32-bit stores makes the generated
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* code quite large.
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*/
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#define TCG_TARGET_HAS_v64 0
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#define TCG_TARGET_HAS_v64 have_vsx
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#define TCG_TARGET_HAS_v128 have_altivec
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#define TCG_TARGET_HAS_v256 0
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@ -165,7 +166,7 @@ extern bool have_altivec;
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#define TCG_TARGET_HAS_mul_vec 1
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#define TCG_TARGET_HAS_sat_vec 1
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#define TCG_TARGET_HAS_minmax_vec 1
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#define TCG_TARGET_HAS_bitsel_vec 0
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#define TCG_TARGET_HAS_bitsel_vec have_vsx
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#define TCG_TARGET_HAS_cmpsel_vec 0
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void flush_icache_range(uintptr_t start, uintptr_t stop);
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@ -67,6 +67,7 @@ static tcg_insn_unit *tb_ret_addr;
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TCGPowerISA have_isa;
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static bool have_isel;
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bool have_altivec;
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bool have_vsx;
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#ifndef CONFIG_SOFTMMU
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#define TCG_GUEST_BASE_REG 30
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@ -467,9 +468,12 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
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#define LVEBX XO31(7)
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#define LVEHX XO31(39)
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#define LVEWX XO31(71)
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#define LXSDX (XO31(588) | 1) /* v2.06, force tx=1 */
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#define LXVDSX (XO31(332) | 1) /* v2.06, force tx=1 */
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#define STVX XO31(231)
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#define STVEWX XO31(199)
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#define STXSDX (XO31(716) | 1) /* v2.06, force sx=1 */
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#define VADDSBS VX4(768)
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#define VADDUBS VX4(512)
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@ -558,6 +562,9 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
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#define VSLDOI VX4(44)
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#define XXPERMDI (OPCD(60) | (10 << 3) | 7) /* v2.06, force ax=bx=tx=1 */
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#define XXSEL (OPCD(60) | (3 << 4) | 0xf) /* v2.06, force ax=bx=cx=tx=1 */
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#define RT(r) ((r)<<21)
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#define RS(r) ((r)<<21)
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#define RA(r) ((r)<<16)
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@ -884,11 +891,21 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg ret,
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add = 0;
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}
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load_insn = LVX | VRT(ret) | RB(TCG_REG_TMP1);
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if (TCG_TARGET_REG_BITS == 64) {
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new_pool_l2(s, rel, s->code_ptr, add, val, val);
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if (have_vsx) {
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load_insn = type == TCG_TYPE_V64 ? LXSDX : LXVDSX;
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load_insn |= VRT(ret) | RB(TCG_REG_TMP1);
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if (TCG_TARGET_REG_BITS == 64) {
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new_pool_label(s, val, rel, s->code_ptr, add);
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} else {
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new_pool_l2(s, rel, s->code_ptr, add, val, val);
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}
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} else {
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new_pool_l4(s, rel, s->code_ptr, add, val, val, val, val);
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load_insn = LVX | VRT(ret) | RB(TCG_REG_TMP1);
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if (TCG_TARGET_REG_BITS == 64) {
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new_pool_l2(s, rel, s->code_ptr, add, val, val);
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} else {
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new_pool_l4(s, rel, s->code_ptr, add, val, val, val, val);
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}
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}
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if (USE_REG_TB) {
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@ -1136,6 +1153,10 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
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/* fallthru */
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case TCG_TYPE_V64:
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tcg_debug_assert(ret >= TCG_REG_V0);
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if (have_vsx) {
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tcg_out_mem_long(s, 0, LXSDX, ret, base, offset);
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break;
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}
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tcg_debug_assert((offset & 7) == 0);
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tcg_out_mem_long(s, 0, LVX, ret, base, offset & -16);
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if (offset & 8) {
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@ -1180,6 +1201,10 @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
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/* fallthru */
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case TCG_TYPE_V64:
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tcg_debug_assert(arg >= TCG_REG_V0);
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if (have_vsx) {
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tcg_out_mem_long(s, 0, STXSDX, arg, base, offset);
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break;
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}
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tcg_debug_assert((offset & 7) == 0);
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if (offset & 8) {
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tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, 8);
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@ -2899,6 +2924,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
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case INDEX_op_shri_vec:
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case INDEX_op_sari_vec:
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return vece <= MO_32 ? -1 : 0;
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case INDEX_op_bitsel_vec:
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return have_vsx;
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default:
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return 0;
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}
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@ -2925,6 +2952,10 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
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tcg_out32(s, VSPLTW | VRT(dst) | VRB(src) | (1 << 16));
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break;
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case MO_64:
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if (have_vsx) {
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tcg_out32(s, XXPERMDI | VRT(dst) | VRA(src) | VRB(src));
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break;
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}
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tcg_out_vsldoi(s, TCG_VEC_TMP1, src, src, 8);
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tcg_out_vsldoi(s, dst, TCG_VEC_TMP1, src, 8);
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break;
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@ -2968,6 +2999,10 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
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tcg_out32(s, VSPLTW | VRT(out) | VRB(out) | (elt << 16));
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break;
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case MO_64:
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if (have_vsx) {
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tcg_out_mem_long(s, 0, LXVDSX, out, base, offset);
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break;
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}
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tcg_debug_assert((offset & 7) == 0);
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tcg_out_mem_long(s, 0, LVX, out, base, offset & -16);
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tcg_out_vsldoi(s, TCG_VEC_TMP1, out, out, 8);
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@ -3102,6 +3137,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
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}
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break;
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case INDEX_op_bitsel_vec:
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tcg_out32(s, XXSEL | VRT(a0) | VRC(a1) | VRB(a2) | VRA(args[3]));
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return;
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case INDEX_op_dup2_vec:
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assert(TCG_TARGET_REG_BITS == 32);
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/* With inputs a1 = xLxx, a2 = xHxx */
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@ -3497,6 +3536,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
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case INDEX_op_st_vec:
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case INDEX_op_dupm_vec:
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return &v_r;
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case INDEX_op_bitsel_vec:
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case INDEX_op_ppc_msum_vec:
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return &v_v_v_v;
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@ -3530,6 +3570,10 @@ static void tcg_target_init(TCGContext *s)
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if (hwcap & PPC_FEATURE_HAS_ALTIVEC) {
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have_altivec = true;
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/* We only care about the portion of VSX that overlaps Altivec. */
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if (hwcap & PPC_FEATURE_HAS_VSX) {
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have_vsx = true;
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}
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}
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tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
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