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target/riscv: Add a general status enum for extensions

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The pointer masking is the only extension that directly use status.
The vector or float extension uses the status in an indirect way.

Replace the pointer masking extension special status fields with
the general status.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-Id: <20230324143031.1093-3-zhiwei_liu@linux.alibaba.com>
[rth: Add a typedef for the enum]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-3-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-3-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
LIU Zhiwei 2023-04-12 13:43:10 +02:00 committed by Alistair Francis
parent f196639024
commit 42967f4073
4 changed files with 20 additions and 16 deletions
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2
target/riscv/cpu.c
View File

@ -759,7 +759,7 @@ static void riscv_cpu_reset_hold(Object *obj)
i++;
}
/* mmte is supposed to have pm.current hardwired to 1 */
env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT);
env->mmte |= (EXT_STATUS_INITIAL | MMTE_M_PM_CURRENT);
#endif
env->xl = riscv_cpu_mxl(env);
riscv_cpu_update_mask(env);

8
target/riscv/cpu.h
View File

@ -97,6 +97,14 @@ enum {
TRANSLATE_G_STAGE_FAIL
};
/* Extension context status */
typedef enum {
EXT_STATUS_DISABLED = 0,
EXT_STATUS_INITIAL,
EXT_STATUS_CLEAN,
EXT_STATUS_DIRTY,
} RISCVExtStatus;
#define MMU_USER_IDX 3
#define MAX_RISCV_PMPS (16)

12
target/riscv/cpu_bits.h
View File

@ -9,6 +9,9 @@
(((uint64_t)(val) * ((mask) & ~((mask) << 1))) & \
(uint64_t)(mask)))
/* Extension context status mask */
#define EXT_STATUS_MASK 0x3ULL
/* Floating point round mode */
#define FSR_RD_SHIFT 5
#define FSR_RD (0x7 << FSR_RD_SHIFT)
@ -735,13 +738,6 @@ typedef enum RISCVException {
#define PM_ENABLE 0x00000001ULL
#define PM_CURRENT 0x00000002ULL
#define PM_INSN 0x00000004ULL
#define PM_XS_MASK 0x00000003ULL
/* PointerMasking XS bits values */
#define PM_EXT_DISABLE 0x00000000ULL
#define PM_EXT_INITIAL 0x00000001ULL
#define PM_EXT_CLEAN 0x00000002ULL
#define PM_EXT_DIRTY 0x00000003ULL
/* Execution enviornment configuration bits */
#define MENVCFG_FIOM BIT(0)
@ -781,7 +777,7 @@ typedef enum RISCVException {
#define S_OFFSET 5ULL
#define M_OFFSET 8ULL
#define PM_XS_BITS (PM_XS_MASK << XS_OFFSET)
#define PM_XS_BITS (EXT_STATUS_MASK << XS_OFFSET)
#define U_PM_ENABLE (PM_ENABLE << U_OFFSET)
#define U_PM_CURRENT (PM_CURRENT << U_OFFSET)
#define U_PM_INSN (PM_INSN << U_OFFSET)

14
target/riscv/csr.c
View File

@ -3548,7 +3548,7 @@ static RISCVException write_mmte(CPURISCVState *env, int csrno,
/* hardwiring pm.instruction bit to 0, since it's not supported yet */
wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN);
env->mmte = wpri_val | PM_EXT_DIRTY;
env->mmte = wpri_val | EXT_STATUS_DIRTY;
riscv_cpu_update_mask(env);
/* Set XS and SD bits, since PM CSRs are dirty */
@ -3628,7 +3628,7 @@ static RISCVException write_mpmmask(CPURISCVState *env, int csrno,
if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
env->cur_pmmask = val;
}
env->mmte |= PM_EXT_DIRTY;
env->mmte |= EXT_STATUS_DIRTY;
/* Set XS and SD bits, since PM CSRs are dirty */
mstatus = env->mstatus | MSTATUS_XS;
@ -3656,7 +3656,7 @@ static RISCVException write_spmmask(CPURISCVState *env, int csrno,
if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
env->cur_pmmask = val;
}
env->mmte |= PM_EXT_DIRTY;
env->mmte |= EXT_STATUS_DIRTY;
/* Set XS and SD bits, since PM CSRs are dirty */
mstatus = env->mstatus | MSTATUS_XS;
@ -3684,7 +3684,7 @@ static RISCVException write_upmmask(CPURISCVState *env, int csrno,
if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
env->cur_pmmask = val;
}
env->mmte |= PM_EXT_DIRTY;
env->mmte |= EXT_STATUS_DIRTY;
/* Set XS and SD bits, since PM CSRs are dirty */
mstatus = env->mstatus | MSTATUS_XS;
@ -3708,7 +3708,7 @@ static RISCVException write_mpmbase(CPURISCVState *env, int csrno,
if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
env->cur_pmbase = val;
}
env->mmte |= PM_EXT_DIRTY;
env->mmte |= EXT_STATUS_DIRTY;
/* Set XS and SD bits, since PM CSRs are dirty */
mstatus = env->mstatus | MSTATUS_XS;
@ -3736,7 +3736,7 @@ static RISCVException write_spmbase(CPURISCVState *env, int csrno,
if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
env->cur_pmbase = val;
}
env->mmte |= PM_EXT_DIRTY;
env->mmte |= EXT_STATUS_DIRTY;
/* Set XS and SD bits, since PM CSRs are dirty */
mstatus = env->mstatus | MSTATUS_XS;
@ -3764,7 +3764,7 @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
env->cur_pmbase = val;
}
env->mmte |= PM_EXT_DIRTY;
env->mmte |= EXT_STATUS_DIRTY;
/* Set XS and SD bits, since PM CSRs are dirty */
mstatus = env->mstatus | MSTATUS_XS;