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https://github.com/qemu/qemu.git
synced 2024-11-25 11:53:39 +08:00
ehci: switch to new-style memory ops
Also register different memory regions for capabilities, operational registers and port status registers. Create separate tracepoints for operational regs and port status regs. Ditch a bunch of sanity checks because the memory core will do this for us now. Offloading the byte, word and dword access handling to the memory core also has the side effect of fixing ehci register access on bigendian hosts. Cc: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
This commit is contained in:
Gerd Hoffmann
parent
63587e3135
commit
3e4f910c8d
@ -389,6 +389,9 @@ struct EHCIState {
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USBBus bus;
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qemu_irq irq;
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MemoryRegion mem;
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MemoryRegion mem_caps;
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MemoryRegion mem_opreg;
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MemoryRegion mem_ports;
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int companion_count;
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/* properties */
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@ -398,10 +401,10 @@ struct EHCIState {
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* EHCI spec version 1.0 Section 2.3
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* Host Controller Operational Registers
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*/
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uint8_t caps[OPREGBASE];
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union {
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uint8_t mmio[MMIO_SIZE];
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uint32_t opreg[(PORTSC_BEGIN-OPREGBASE)/sizeof(uint32_t)];
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struct {
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uint8_t cap[OPREGBASE];
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uint32_t usbcmd;
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uint32_t usbsts;
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uint32_t usbintr;
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@ -411,9 +414,9 @@ struct EHCIState {
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uint32_t asynclistaddr;
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uint32_t notused[9];
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uint32_t configflag;
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};
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};
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uint32_t portsc[NB_PORTS];
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};
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};
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/*
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* Internal states, shadow registers, etc
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@ -471,22 +474,12 @@ static const char *ehci_state_names[] = {
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};
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static const char *ehci_mmio_names[] = {
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[CAPLENGTH] = "CAPLENGTH",
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[HCIVERSION] = "HCIVERSION",
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[HCSPARAMS] = "HCSPARAMS",
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[HCCPARAMS] = "HCCPARAMS",
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[USBCMD] = "USBCMD",
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[USBSTS] = "USBSTS",
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[USBINTR] = "USBINTR",
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[FRINDEX] = "FRINDEX",
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[PERIODICLISTBASE] = "P-LIST BASE",
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[ASYNCLISTADDR] = "A-LIST ADDR",
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[PORTSC_BEGIN] = "PORTSC #0",
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[PORTSC_BEGIN + 4] = "PORTSC #1",
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[PORTSC_BEGIN + 8] = "PORTSC #2",
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[PORTSC_BEGIN + 12] = "PORTSC #3",
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[PORTSC_BEGIN + 16] = "PORTSC #4",
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[PORTSC_BEGIN + 20] = "PORTSC #5",
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[CONFIGFLAG] = "CONFIGFLAG",
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};
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@ -509,7 +502,8 @@ static const char *state2str(uint32_t state)
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static const char *addr2str(target_phys_addr_t addr)
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{
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return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr);
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return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names),
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addr + OPREGBASE);
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}
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static void ehci_trace_usbsts(uint32_t mask, int state)
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@ -1018,7 +1012,7 @@ static int ehci_register_companion(USBBus *bus, USBPort *ports[],
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}
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s->companion_count++;
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s->mmio[0x05] = (s->companion_count << 4) | portcount;
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s->caps[0x05] = (s->companion_count << 4) | portcount;
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return 0;
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}
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@ -1063,7 +1057,8 @@ static void ehci_reset(void *opaque)
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}
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}
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memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE);
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memset(&s->opreg, 0x00, sizeof(s->opreg));
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memset(&s->portsc, 0x00, sizeof(s->portsc));
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s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH;
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s->usbsts = USBSTS_HALT;
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@ -1090,50 +1085,35 @@ static void ehci_reset(void *opaque)
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qemu_bh_cancel(s->async_bh);
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}
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static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr)
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static uint64_t ehci_caps_read(void *ptr, target_phys_addr_t addr,
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unsigned size)
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{
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EHCIState *s = ptr;
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return s->caps[addr];
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}
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static uint64_t ehci_opreg_read(void *ptr, target_phys_addr_t addr,
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unsigned size)
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{
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EHCIState *s = ptr;
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uint32_t val;
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val = s->mmio[addr];
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val = s->opreg[addr >> 2];
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trace_usb_ehci_opreg_read(addr + OPREGBASE, addr2str(addr), val);
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return val;
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}
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static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr)
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static uint64_t ehci_port_read(void *ptr, target_phys_addr_t addr,
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unsigned size)
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{
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EHCIState *s = ptr;
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uint32_t val;
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val = s->mmio[addr] | (s->mmio[addr+1] << 8);
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val = s->portsc[addr >> 2];
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trace_usb_ehci_portsc_read(addr + PORTSC_BEGIN, addr >> 2, val);
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return val;
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}
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static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr)
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{
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EHCIState *s = ptr;
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uint32_t val;
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val = s->mmio[addr] | (s->mmio[addr+1] << 8) |
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(s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24);
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trace_usb_ehci_mmio_readl(addr, addr2str(addr), val);
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return val;
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}
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static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val)
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{
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fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n");
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exit(1);
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}
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static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val)
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{
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fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n");
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exit(1);
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}
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static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner)
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{
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USBDevice *dev = s->ports[port].dev;
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@ -1162,11 +1142,17 @@ static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner)
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}
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}
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static void handle_port_status_write(EHCIState *s, int port, uint32_t val)
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static void ehci_port_write(void *ptr, target_phys_addr_t addr,
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uint64_t val, unsigned size)
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{
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EHCIState *s = ptr;
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int port = addr >> 2;
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uint32_t *portsc = &s->portsc[port];
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uint32_t old = *portsc;
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USBDevice *dev = s->ports[port].dev;
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trace_usb_ehci_portsc_write(addr + PORTSC_BEGIN, addr >> 2, val);
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/* Clear rwc bits */
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*portsc &= ~(val & PORTSC_RWC_MASK);
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/* The guest may clear, but not set the PED bit */
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@ -1198,39 +1184,20 @@ static void handle_port_status_write(EHCIState *s, int port, uint32_t val)
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*portsc &= ~PORTSC_RO_MASK;
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*portsc |= val;
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trace_usb_ehci_portsc_change(addr + PORTSC_BEGIN, addr >> 2, *portsc, old);
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}
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static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
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static void ehci_opreg_write(void *ptr, target_phys_addr_t addr,
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uint64_t val, unsigned size)
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{
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EHCIState *s = ptr;
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uint32_t *mmio = (uint32_t *)(&s->mmio[addr]);
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uint32_t *mmio = s->opreg + (addr >> 2);
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uint32_t old = *mmio;
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int i;
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trace_usb_ehci_mmio_writel(addr, addr2str(addr), val);
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trace_usb_ehci_opreg_write(addr + OPREGBASE, addr2str(addr), val);
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/* Only aligned reads are allowed on OHCI */
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if (addr & 3) {
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fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x"
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TARGET_FMT_plx "\n", addr);
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return;
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}
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if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) {
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handle_port_status_write(s, (addr-PORTSC)/4, val);
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trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
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return;
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}
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if (addr < OPREGBASE) {
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fprintf(stderr, "usb-ehci: write attempt to read-only register"
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TARGET_FMT_plx "\n", addr);
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return;
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}
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/* Do any register specific pre-write processing here. */
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switch(addr) {
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switch (addr + OPREGBASE) {
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case USBCMD:
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if (val & USBCMD_HCRESET) {
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ehci_reset(s);
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@ -1241,7 +1208,7 @@ static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
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/* not supporting dynamic frame list size at the moment */
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if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {
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fprintf(stderr, "attempt to set frame list size -- value %d\n",
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val & USBCMD_FLS);
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(int)val & USBCMD_FLS);
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val &= ~USBCMD_FLS;
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}
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@ -1308,7 +1275,7 @@ static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
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}
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*mmio = val;
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trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
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trace_usb_ehci_opreg_change(addr + OPREGBASE, addr2str(addr), *mmio, old);
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}
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@ -2520,11 +2487,28 @@ static void ehci_async_bh(void *opaque)
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ehci_advance_async_state(ehci);
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}
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static const MemoryRegionOps ehci_mem_ops = {
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.old_mmio = {
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.read = { ehci_mem_readb, ehci_mem_readw, ehci_mem_readl },
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.write = { ehci_mem_writeb, ehci_mem_writew, ehci_mem_writel },
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},
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static const MemoryRegionOps ehci_mmio_caps_ops = {
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.read = ehci_caps_read,
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.valid.min_access_size = 1,
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.valid.max_access_size = 4,
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.impl.min_access_size = 1,
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.impl.max_access_size = 1,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static const MemoryRegionOps ehci_mmio_opreg_ops = {
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.read = ehci_opreg_read,
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.write = ehci_opreg_write,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static const MemoryRegionOps ehci_mmio_port_ops = {
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.read = ehci_port_read,
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.write = ehci_port_write,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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@ -2681,19 +2665,19 @@ static int usb_ehci_initfn(PCIDevice *dev)
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pci_conf[0x6e] = 0x00;
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pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS
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// 2.2 host controller interface version
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s->mmio[0x00] = (uint8_t) OPREGBASE;
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s->mmio[0x01] = 0x00;
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s->mmio[0x02] = 0x00;
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s->mmio[0x03] = 0x01; // HC version
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s->mmio[0x04] = NB_PORTS; // Number of downstream ports
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s->mmio[0x05] = 0x00; // No companion ports at present
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s->mmio[0x06] = 0x00;
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s->mmio[0x07] = 0x00;
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s->mmio[0x08] = 0x80; // We can cache whole frame, not 64-bit capable
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s->mmio[0x09] = 0x68; // EECP
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s->mmio[0x0a] = 0x00;
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s->mmio[0x0b] = 0x00;
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/* 2.2 host controller interface version */
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s->caps[0x00] = (uint8_t) OPREGBASE;
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s->caps[0x01] = 0x00;
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s->caps[0x02] = 0x00;
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s->caps[0x03] = 0x01; /* HC version */
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s->caps[0x04] = NB_PORTS; /* Number of downstream ports */
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s->caps[0x05] = 0x00; /* No companion ports at present */
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s->caps[0x06] = 0x00;
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s->caps[0x07] = 0x00;
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s->caps[0x08] = 0x80; /* We can cache whole frame, no 64-bit */
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s->caps[0x09] = 0x68; /* EECP */
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s->caps[0x0a] = 0x00;
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s->caps[0x0b] = 0x00;
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s->irq = s->dev.irq[3];
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@ -2712,7 +2696,18 @@ static int usb_ehci_initfn(PCIDevice *dev)
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qemu_register_reset(ehci_reset, s);
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memory_region_init_io(&s->mem, &ehci_mem_ops, s, "ehci", MMIO_SIZE);
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memory_region_init(&s->mem, "ehci", MMIO_SIZE);
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memory_region_init_io(&s->mem_caps, &ehci_mmio_caps_ops, s,
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"capabilities", OPREGBASE);
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memory_region_init_io(&s->mem_opreg, &ehci_mmio_opreg_ops, s,
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"operational", PORTSC_BEGIN - OPREGBASE);
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memory_region_init_io(&s->mem_ports, &ehci_mmio_port_ops, s,
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"ports", PORTSC_END - PORTSC_BEGIN);
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memory_region_add_subregion(&s->mem, 0, &s->mem_caps);
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memory_region_add_subregion(&s->mem, OPREGBASE, &s->mem_opreg);
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memory_region_add_subregion(&s->mem, PORTSC_BEGIN, &s->mem_ports);
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pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem);
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return 0;
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@ -243,9 +243,12 @@ usb_port_release(int bus, const char *port) "bus %d, port %s"
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# hw/usb/hcd-ehci.c
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usb_ehci_reset(void) "=== RESET ==="
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usb_ehci_mmio_readl(uint32_t addr, const char *str, uint32_t val) "rd mmio %04x [%s] = %x"
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usb_ehci_mmio_writel(uint32_t addr, const char *str, uint32_t val) "wr mmio %04x [%s] = %x"
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usb_ehci_mmio_change(uint32_t addr, const char *str, uint32_t new, uint32_t old) "ch mmio %04x [%s] = %x (old: %x)"
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usb_ehci_opreg_read(uint32_t addr, const char *str, uint32_t val) "rd mmio %04x [%s] = %x"
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usb_ehci_opreg_write(uint32_t addr, const char *str, uint32_t val) "wr mmio %04x [%s] = %x"
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usb_ehci_opreg_change(uint32_t addr, const char *str, uint32_t new, uint32_t old) "ch mmio %04x [%s] = %x (old: %x)"
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usb_ehci_portsc_read(uint32_t addr, uint32_t port, uint32_t val) "rd mmio %04x [port %d] = %x"
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usb_ehci_portsc_write(uint32_t addr, uint32_t port, uint32_t val) "wr mmio %04x [port %d] = %x"
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usb_ehci_portsc_change(uint32_t addr, uint32_t port, uint32_t new, uint32_t old) "ch mmio %04x [port %d] = %x (old: %x)"
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usb_ehci_usbsts(const char *sts, int state) "usbsts %s %d"
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usb_ehci_state(const char *schedule, const char *state) "%s schedule %s"
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usb_ehci_qh_ptrs(void *q, uint32_t addr, uint32_t nxt, uint32_t c_qtd, uint32_t n_qtd, uint32_t a_qtd) "q %p - QH @ %08x: next %08x qtds %08x,%08x,%08x"
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