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target/ppc: implement vslq
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-21-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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@ -473,6 +473,7 @@ VSLB 000100 ..... ..... ..... 00100000100 @VX
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VSLH 000100 ..... ..... ..... 00101000100 @VX
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VSLW 000100 ..... ..... ..... 00110000100 @VX
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VSLD 000100 ..... ..... ..... 10111000100 @VX
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VSLQ 000100 ..... ..... ..... 00100000101 @VX
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VSRB 000100 ..... ..... ..... 01000000100 @VX
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VSRH 000100 ..... ..... ..... 01001000100 @VX
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@ -834,6 +834,46 @@ TRANS_FLAGS(ALTIVEC, VSRAH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_sarv);
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TRANS_FLAGS(ALTIVEC, VSRAW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_sarv);
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TRANS_FLAGS2(ALTIVEC_207, VSRAD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_sarv);
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static bool trans_VSLQ(DisasContext *ctx, arg_VX *a)
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{
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TCGv_i64 hi, lo, t0, n, zero = tcg_constant_i64(0);
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REQUIRE_INSNS_FLAGS2(ctx, ISA310);
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REQUIRE_VECTOR(ctx);
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n = tcg_temp_new_i64();
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hi = tcg_temp_new_i64();
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lo = tcg_temp_new_i64();
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t0 = tcg_temp_new_i64();
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get_avr64(lo, a->vra, false);
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get_avr64(hi, a->vra, true);
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get_avr64(n, a->vrb, true);
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tcg_gen_andi_i64(t0, n, 64);
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tcg_gen_movcond_i64(TCG_COND_NE, hi, t0, zero, lo, hi);
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tcg_gen_movcond_i64(TCG_COND_NE, lo, t0, zero, zero, lo);
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tcg_gen_andi_i64(n, n, 0x3F);
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tcg_gen_shl_i64(t0, lo, n);
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set_avr64(a->vrt, t0, false);
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tcg_gen_shl_i64(hi, hi, n);
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tcg_gen_xori_i64(n, n, 63);
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tcg_gen_shr_i64(lo, lo, n);
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tcg_gen_shri_i64(lo, lo, 1);
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tcg_gen_or_i64(hi, hi, lo);
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set_avr64(a->vrt, hi, true);
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tcg_temp_free_i64(hi);
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tcg_temp_free_i64(lo);
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tcg_temp_free_i64(t0);
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tcg_temp_free_i64(n);
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return true;
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}
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#define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3) \
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static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t, \
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TCGv_vec sat, TCGv_vec a, \
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