mirror of
https://github.com/qemu/qemu.git
synced 2024-11-23 19:03:38 +08:00
imx_serial: Generate interrupt on receive data ready if enabled
Generate an interrupt if USR2_RDR and UCR4_DREN are both set. Signed-off-by: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com> Message-id: 1534341354-11956-1-git-send-email-hans-erik.floryd@rt-labs.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
parent
84be3ef1de
commit
3c54cf7705
@ -74,8 +74,9 @@ static void imx_update(IMXSerialState *s)
|
||||
mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
|
||||
/*
|
||||
* TCEN and TXDC are both bit 3
|
||||
* RDR and DREN are both bit 0
|
||||
*/
|
||||
mask |= s->ucr4 & UCR4_TCEN;
|
||||
mask |= s->ucr4 & (UCR4_TCEN | UCR4_DREN);
|
||||
|
||||
usr2 = s->usr2 & mask;
|
||||
|
||||
|
@ -68,6 +68,7 @@
|
||||
#define UCR2_RXEN (1<<1) /* Receiver enable */
|
||||
#define UCR2_SRST (1<<0) /* Reset complete */
|
||||
|
||||
#define UCR4_DREN BIT(0) /* Receive Data Ready interrupt enable */
|
||||
#define UCR4_TCEN BIT(3) /* TX complete interrupt enable */
|
||||
|
||||
#define UTS1_TXEMPTY (1<<6)
|
||||
|
Loading…
Reference in New Issue
Block a user