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softmmu: Add probe_write()
Probe for whether the specified guest write access is permitted. If it is not permitted then an exception will be taken in the same way as if this were a real write access (and we will not return). Otherwise the function will return, and there will be a valid entry in the TLB for this access. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
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@ -105,6 +105,8 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
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hwaddr paddr, MemTxAttrs attrs,
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int prot, int mmu_idx, target_ulong size);
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void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
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void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx,
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uintptr_t retaddr);
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#else
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static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
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{
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@ -548,6 +548,28 @@ glue(glue(helper_st, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
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helper_te_st_name(env, addr, val, oi, GETRA());
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}
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#if DATA_SIZE == 1
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/* Probe for whether the specified guest write access is permitted.
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* If it is not permitted then an exception will be taken in the same
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* way as if this were a real write access (and we will not return).
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* Otherwise the function will return, and there will be a valid
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* entry in the TLB for this access.
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*/
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void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx,
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uintptr_t retaddr)
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{
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int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
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if ((addr & TARGET_PAGE_MASK)
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!= (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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/* TLB entry is for a different page */
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if (!VICTIM_TLB_HIT(addr_write)) {
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tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
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}
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}
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}
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#endif
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#endif /* !defined(SOFTMMU_CODE_ACCESS) */
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#undef READ_ACCESS_TYPE
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