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hw/pci-bridge/pxb-cxl: Drop RAS capability from host bridge.
This CXL component isn't allowed to have a RAS capability. Whilst this should be harmless as software is not expected to look here, good to clean it up. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20240215155206.2736-1-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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@ -297,6 +297,7 @@ void cxl_component_register_init_common(uint32_t *reg_state,
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caps = 3;
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break;
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case CXL2_ROOT_PORT:
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case CXL2_RC:
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/* + Extended Security, + Snoop */
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caps = 5;
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break;
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@ -326,8 +327,19 @@ void cxl_component_register_init_common(uint32_t *reg_state,
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CXL_##reg##_REGISTERS_OFFSET); \
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} while (0)
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switch (type) {
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case CXL2_DEVICE:
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case CXL2_TYPE3_DEVICE:
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case CXL2_LOGICAL_DEVICE:
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case CXL2_ROOT_PORT:
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case CXL2_UPSTREAM_PORT:
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case CXL2_DOWNSTREAM_PORT:
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init_cap_reg(RAS, 2, CXL_RAS_CAPABILITY_VERSION);
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ras_init_common(reg_state, write_msk);
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ras_init_common(reg_state, write_msk);
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break;
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default:
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break;
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}
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init_cap_reg(LINK, 4, CXL_LINK_CAPABILITY_VERSION);
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@ -335,9 +347,10 @@ void cxl_component_register_init_common(uint32_t *reg_state,
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return;
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}
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init_cap_reg(HDM, 5, CXL_HDM_CAPABILITY_VERSION);
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hdm_init_common(reg_state, write_msk, type);
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if (type != CXL2_ROOT_PORT) {
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init_cap_reg(HDM, 5, CXL_HDM_CAPABILITY_VERSION);
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hdm_init_common(reg_state, write_msk, type);
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}
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if (caps < 5) {
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return;
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}
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@ -290,7 +290,7 @@ static void pxb_cxl_dev_reset(DeviceState *dev)
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uint32_t *write_msk = cxl_cstate->crb.cache_mem_regs_write_mask;
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int dsp_count = 0;
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cxl_component_register_init_common(reg_state, write_msk, CXL2_ROOT_PORT);
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cxl_component_register_init_common(reg_state, write_msk, CXL2_RC);
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/*
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* The CXL specification allows for host bridges with no HDM decoders
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* if they only have a single root port.
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@ -25,6 +25,7 @@ enum reg_type {
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CXL2_TYPE3_DEVICE,
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CXL2_LOGICAL_DEVICE,
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CXL2_ROOT_PORT,
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CXL2_RC,
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CXL2_UPSTREAM_PORT,
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CXL2_DOWNSTREAM_PORT,
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CXL3_SWITCH_MAILBOX_CCI,
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