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tcg/loongarch64: Implement add/sub ops
The neg_i{32,64} ops is fully expressible with sub, so omitted for simplicity. Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211221054105.178795-18-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -18,6 +18,8 @@ C_O0_I1(r)
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C_O1_I1(r, r)
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C_O1_I2(r, r, rC)
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C_O1_I2(r, r, ri)
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C_O1_I2(r, r, rI)
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C_O1_I2(r, r, rU)
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C_O1_I2(r, r, rW)
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C_O1_I2(r, 0, rZ)
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C_O1_I2(r, rZ, rN)
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@ -687,6 +687,36 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
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}
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break;
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case INDEX_op_add_i32:
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if (c2) {
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tcg_out_opc_addi_w(s, a0, a1, a2);
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} else {
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tcg_out_opc_add_w(s, a0, a1, a2);
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}
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break;
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case INDEX_op_add_i64:
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if (c2) {
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tcg_out_opc_addi_d(s, a0, a1, a2);
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} else {
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tcg_out_opc_add_d(s, a0, a1, a2);
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}
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break;
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case INDEX_op_sub_i32:
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if (c2) {
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tcg_out_opc_addi_w(s, a0, a1, -a2);
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} else {
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tcg_out_opc_sub_w(s, a0, a1, a2);
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}
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break;
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case INDEX_op_sub_i64:
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if (c2) {
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tcg_out_opc_addi_d(s, a0, a1, -a2);
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} else {
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tcg_out_opc_sub_d(s, a0, a1, a2);
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}
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break;
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case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
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case INDEX_op_mov_i64:
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default:
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@ -748,6 +778,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
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case INDEX_op_rotr_i64:
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return C_O1_I2(r, r, ri);
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case INDEX_op_add_i32:
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case INDEX_op_add_i64:
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return C_O1_I2(r, r, rI);
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case INDEX_op_and_i32:
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case INDEX_op_and_i64:
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case INDEX_op_nor_i32:
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@ -770,6 +804,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
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/* Must deposit into the same register as input */
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return C_O1_I2(r, 0, rZ);
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case INDEX_op_sub_i32:
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case INDEX_op_sub_i64:
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return C_O1_I2(r, rZ, rN);
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default:
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g_assert_not_reached();
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}
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