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Coding style fixes in PowerPC related code (no functional change):

Browse Source 
- avoid useless blanks at EOL.
- avoid tabs.
- fix wrapping lines on 80 chars terminals.
- add missing ';' at macros EOL to avoid confusing auto-identers.
- fix identation.
- Remove historical macros in micro-ops (PARAM, SPARAM, PPC_OP, regs)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3178 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
j_mayer 2007-09-17 08:21:54 +00:00
parent 3b46e62427
commit 3608160206
13 changed files with 274 additions and 267 deletions
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11
hw/ppc405_uc.c
View File

@ -924,7 +924,8 @@ enum {
SDRAM0_CFGDATA = 0x011,
};
static uint32_t sdram_bcr (target_phys_addr_t ram_base, target_phys_addr_t ram_size)
static uint32_t sdram_bcr (target_phys_addr_t ram_base,
target_phys_addr_t ram_size)
{
uint32_t bcr;
@ -1217,9 +1218,11 @@ void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
sdram->irq = irq;
sdram->nbanks = nbanks;
memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t));
memcpy(sdram->ram_bases, ram_bases, nbanks * sizeof(target_phys_addr_t));
memcpy(sdram->ram_bases, ram_bases,
nbanks * sizeof(target_phys_addr_t));
memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t));
memcpy(sdram->ram_sizes, ram_sizes, nbanks * sizeof(target_phys_addr_t));
memcpy(sdram->ram_sizes, ram_sizes,
nbanks * sizeof(target_phys_addr_t));
sdram_reset(sdram);
qemu_register_reset(&sdram_reset, sdram);
ppc_dcr_register(env, SDRAM0_CFGADDR,
@ -2212,7 +2215,6 @@ static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
}
mask = mask >> 1;
}
}
static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
@ -2228,7 +2230,6 @@ static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
qemu_irq_lower(gpt->irqs[i]);
mask = mask >> 1;
}
}
static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)

35
hw/ppc_chrp.c
View File

@ -46,22 +46,26 @@ static int macio_nvram_mem_index = -1;
/* DBDMA: currently no op - should suffice right now */
static void dbdma_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
static void dbdma_writeb (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
printf("%s: 0x" PADDRX " <= 0x%08x\n", __func__, addr, value);
}
static void dbdma_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
static void dbdma_writew (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
}
static void dbdma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
static void dbdma_writel (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
}
static uint32_t dbdma_readb (void *opaque, target_phys_addr_t addr)
{
printf("%s: 0x" PADDRX " => 0x00000000\n", __func__, addr);
return 0;
}
@ -92,7 +96,8 @@ typedef struct MacIONVRAMState {
uint8_t data[0x2000];
} MacIONVRAMState;
static void macio_nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
static void macio_nvram_writeb (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
MacIONVRAMState *s = opaque;
addr = (addr >> 4) & 0x1fff;
@ -108,6 +113,7 @@ static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr)
addr = (addr >> 4) & 0x1fff;
value = s->data[addr];
// printf("macio_nvram_readb %04x = %02x\n", addr, value);
return value;
}
@ -123,7 +129,7 @@ static CPUReadMemoryFunc *macio_nvram_read[] = {
&macio_nvram_readb,
};
static MacIONVRAMState *macio_nvram_init(void)
static MacIONVRAMState *macio_nvram_init (void)
{
MacIONVRAMState *s;
s = qemu_mallocz(sizeof(MacIONVRAMState));
@ -131,10 +137,11 @@ static MacIONVRAMState *macio_nvram_init(void)
return NULL;
macio_nvram_mem_index = cpu_register_io_memory(0, macio_nvram_read,
macio_nvram_write, s);
return s;
}
static void macio_map(PCIDevice *pci_dev, int region_num,
static void macio_map (PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
{
if (heathrow_pic_mem_index >= 0) {
@ -152,10 +159,11 @@ static void macio_map(PCIDevice *pci_dev, int region_num,
openpic_mem_index);
}
if (macio_nvram_mem_index >= 0)
cpu_register_physical_memory(addr + 0x60000, 0x20000, macio_nvram_mem_index);
cpu_register_physical_memory(addr + 0x60000, 0x20000,
macio_nvram_mem_index);
}
static void macio_init(PCIBus *bus, int device_id)
static void macio_init (PCIBus *bus, int device_id)
{
PCIDevice *d;
@ -204,7 +212,8 @@ static CPUReadMemoryFunc *unin_read[] = {
/* temporary frame buffer OSI calls for the video.x driver. The right
solution is to modify the driver to use VGA PCI I/Os */
static int vga_osi_call(CPUState *env)
/* XXX: to be removed. This is no way related to emulation */
static int vga_osi_call (CPUState *env)
{
static int vga_vbl_enabled;
int linesize;
@ -264,10 +273,11 @@ static int vga_osi_call(CPUState *env)
fprintf(stderr, "unsupported OSI call R5=" REGX "\n", env->gpr[5]);
break;
}
return 1; /* osi_call handled */
}
static uint8_t nvram_chksum(const uint8_t *buf, int n)
static uint8_t nvram_chksum (const uint8_t *buf, int n)
{
int sum, i;
sum = 0;
@ -277,7 +287,7 @@ static uint8_t nvram_chksum(const uint8_t *buf, int n)
}
/* set a free Mac OS NVRAM partition */
void pmac_format_nvram_partition(uint8_t *buf, int len)
void pmac_format_nvram_partition (uint8_t *buf, int len)
{
char partition_name[12] = "wwwwwwwwwwww";
@ -503,8 +513,7 @@ static void ppc_chrp_init (int ram_size, int vga_ram_size, int boot_device,
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET];
break;
default:
cpu_abort(env,
"Only bus model not supported on mac99 machine\n");
cpu_abort(env, "Bus model not supported on mac99 machine\n");
exit(1);
}
}

14
hw/ppc_prep.c
View File

@ -76,7 +76,7 @@ static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
int speaker_data_on;
int dummy_refresh_clock;
static void speaker_ioport_write(void *opaque, uint32_t addr, uint32_t val)
static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val)
{
#if 0
speaker_data_on = (val >> 1) & 1;
@ -177,12 +177,14 @@ static struct {
/* Error diagnostic */
} XCSR;
static void PPC_XCSR_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
static void PPC_XCSR_writeb (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
}
static void PPC_XCSR_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
static void PPC_XCSR_writew (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
#ifdef TARGET_WORDS_BIGENDIAN
value = bswap16(value);
@ -190,7 +192,8 @@ static void PPC_XCSR_writew (void *opaque, target_phys_addr_t addr, uint32_t val
printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
}
static void PPC_XCSR_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
static void PPC_XCSR_writel (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
#ifdef TARGET_WORDS_BIGENDIAN
value = bswap32(value);
@ -664,7 +667,8 @@ static void ppc_prep_init (int ram_size, int vga_ram_size, int boot_device,
cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
/* PowerPC control and status register group */
#if 0
PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write, NULL);
PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write,
NULL);
cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
#endif

12
target-ppc/cpu.h
View File

@ -822,18 +822,18 @@ struct mmu_ctx_t {
};
/*****************************************************************************/
CPUPPCState *cpu_ppc_init(void);
int cpu_ppc_exec(CPUPPCState *s);
void cpu_ppc_close(CPUPPCState *s);
CPUPPCState *cpu_ppc_init (void);
int cpu_ppc_exec (CPUPPCState *s);
void cpu_ppc_close (CPUPPCState *s);
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
is returned if the signal was handled by the virtual CPU. */
int cpu_ppc_signal_handler(int host_signum, void *pinfo,
int cpu_ppc_signal_handler (int host_signum, void *pinfo,
void *puc);
void do_interrupt (CPUPPCState *env);
void ppc_hw_interrupt (CPUPPCState *env);
void cpu_loop_exit(void);
void cpu_loop_exit (void);
void dump_stack (CPUPPCState *env);
@ -891,7 +891,7 @@ void store_40x_sler (CPUPPCState *env, uint32_t val);
void store_booke_tcr (CPUPPCState *env, target_ulong val);
void store_booke_tsr (CPUPPCState *env, target_ulong val);
void ppc_tlb_invalidate_all (CPUPPCState *env);
int ppcemb_tlb_search (CPUPPCState *env, target_ulong address);
int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
#endif
#endif

11
target-ppc/exec.h
View File

@ -58,10 +58,6 @@ register unsigned long T2 asm(AREG3);
#define T1_avr (env->t1_avr)
#define T2_avr (env->t2_avr)
/* XXX: to clean: remove this mess */
#define PARAM(n) ((uint32_t)PARAM##n)
#define SPARAM(n) ((int32_t)PARAM##n)
#define FT0 (env->ft0)
#define FT1 (env->ft1)
#define FT2 (env->ft2)
@ -111,18 +107,19 @@ void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
target_ulong pte0, target_ulong pte1);
void ppc4xx_tlb_invalidate_all (CPUState *env);
static inline void env_to_regs(void)
static inline void env_to_regs (void)
{
}
static inline void regs_to_env(void)
static inline void regs_to_env (void)
{
}
int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
int is_user, int is_softmmu);
static inline int cpu_halted(CPUState *env) {
static inline int cpu_halted (CPUState *env)
{
if (!env->halted)
return 0;
if (env->msr[MSR_EE] && (env->interrupt_request & CPU_INTERRUPT_HARD)) {

26
target-ppc/helper.c
View File

@ -64,6 +64,7 @@ target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
{
return addr;
}
#else
/* Common routines used by software and hardware TLBs emulation */
static inline int pte_is_valid (target_ulong pte0)
@ -635,7 +636,8 @@ static int get_segment (CPUState *env, mmu_ctx_t *ctx,
/* Generic TLB check function for embedded PowerPC implementations */
static int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb,
target_phys_addr_t *raddrp,
target_ulong address, int i)
target_ulong address,
uint32_t pid, int ext, int i)
{
target_ulong mask;
@ -649,22 +651,25 @@ static int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb,
if (loglevel != 0) {
fprintf(logfile, "%s: TLB %d address " ADDRX " PID %d <=> "
ADDRX " " ADDRX " %d\n",
__func__, i, address, (int)env->spr[SPR_40x_PID],
tlb->EPN, mask, (int)tlb->PID);
__func__, i, address, pid, tlb->EPN, mask, (int)tlb->PID);
}
/* Check PID */
if (tlb->PID != 0 && tlb->PID != env->spr[SPR_40x_PID])
if (tlb->PID != 0 && tlb->PID != pid)
return -1;
/* Check effective address */
if ((address & mask) != tlb->EPN)
return -1;
*raddrp = (tlb->RPN & mask) | (address & ~mask);
if (ext) {
/* Extend the physical address to 36 bits */
*raddrp |= (target_phys_addr_t)(tlb->RPN & 0xF) << 32;
}
return 0;
}
/* Generic TLB search function for PowerPC embedded implementations */
int ppcemb_tlb_search (CPUState *env, target_ulong address)
int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)
{
ppcemb_tlb_t *tlb;
target_phys_addr_t raddr;
@ -674,7 +679,7 @@ int ppcemb_tlb_search (CPUState *env, target_ulong address)
ret = -1;
for (i = 0; i < 64; i++) {
tlb = &env->tlb[i].tlbe;
if (ppcemb_tlb_check(env, tlb, &raddr, address, i) == 0) {
if (ppcemb_tlb_check(env, tlb, &raddr, address, pid, 0, i) == 0) {
ret = i;
break;
}
@ -703,7 +708,7 @@ void ppc4xx_tlb_invalidate_all (CPUState *env)
tlb_flush(env, 1);
}
int mmu4xx_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
target_ulong address, int rw, int access_type)
{
ppcemb_tlb_t *tlb;
@ -714,7 +719,8 @@ int mmu4xx_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
raddr = -1;
for (i = 0; i < env->nb_tlb; i++) {
tlb = &env->tlb[i].tlbe;
if (ppcemb_tlb_check(env, tlb, &raddr, address, i) < 0)
if (ppcemb_tlb_check(env, tlb, &raddr, address,
env->spr[SPR_40x_PID], 0, i) < 0)
continue;
zsel = (tlb->attr >> 4) & 0xF;
zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3;
@ -890,7 +896,7 @@ int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
break;
case PPC_FLAGS_MMU_SOFT_4xx:
case PPC_FLAGS_MMU_403:
ret = mmu4xx_get_physical_address(env, ctx, eaddr,
ret = mmu40x_get_physical_address(env, ctx, eaddr,
rw, access_type);
break;
case PPC_FLAGS_MMU_601:
@ -1536,7 +1542,7 @@ void ppc_hw_interrupt (CPUState *env)
env->exception_index = -1;
}
#else /* defined (CONFIG_USER_ONLY) */
static void dump_syscall(CPUState *env)
static void dump_syscall (CPUState *env)
{
fprintf(logfile, "syscall r0=0x" REGX " r3=0x" REGX " r4=0x" REGX
" r5=0x" REGX " r6=0x" REGX " nip=0x" ADDRX "\n",

292
target-ppc/op.c
View File

@ -24,16 +24,6 @@
#include "exec.h"
#include "op_helper.h"
/* XXX: this is to be suppressed */
#define regs (env)
#define FT0 (env->ft0)
#define FT1 (env->ft1)
#define FT2 (env->ft2)
/* XXX: this is to be suppressed... */
#define PPC_OP(name) void OPPROTO glue(op_, name)(void)
#define REG 0
#include "op_template.h"
@ -139,16 +129,16 @@ void OPPROTO op_print_mem_EA (void)
/* PowerPC state maintenance operations */
/* set_Rc0 */
PPC_OP(set_Rc0)
void OPPROTO op_set_Rc0 (void)
{
env->crf[0] = T0 | xer_ov;
RETURN();
}
/* Set Rc1 (for floating point arithmetic) */
PPC_OP(set_Rc1)
void OPPROTO op_set_Rc1 (void)
{
env->crf[1] = regs->fpscr[7];
env->crf[1] = env->fpscr[7];
RETURN();
}
@ -159,7 +149,7 @@ void OPPROTO op_reset_T0 (void)
RETURN();
}
PPC_OP(set_T0)
void OPPROTO op_set_T0 (void)
{
T0 = (uint32_t)PARAM1;
RETURN();
@ -173,7 +163,7 @@ void OPPROTO op_set_T0_64 (void)
}
#endif
PPC_OP(set_T1)
void OPPROTO op_set_T1 (void)
{
T1 = (uint32_t)PARAM1;
RETURN();
@ -188,9 +178,9 @@ void OPPROTO op_set_T1_64 (void)
#endif
#if 0 // unused
PPC_OP(set_T2)
void OPPROTO op_set_T2 (void)
{
T2 = PARAM(1);
T2 = PARAM1;
RETURN();
}
#endif
@ -208,12 +198,12 @@ void OPPROTO op_move_T2_T0 (void)
}
/* Generate exceptions */
PPC_OP(raise_exception_err)
void OPPROTO op_raise_exception_err (void)
{
do_raise_exception_err(PARAM(1), PARAM(2));
do_raise_exception_err(PARAM1, PARAM2);
}
PPC_OP(update_nip)
void OPPROTO op_update_nip (void)
{
env->nip = (uint32_t)PARAM1;
RETURN();
@ -227,26 +217,26 @@ void OPPROTO op_update_nip_64 (void)
}
#endif
PPC_OP(debug)
void OPPROTO op_debug (void)
{
do_raise_exception(EXCP_DEBUG);
}
PPC_OP(exit_tb)
void OPPROTO op_exit_tb (void)
{
EXIT_TB();
}
/* Load/store special registers */
PPC_OP(load_cr)
void OPPROTO op_load_cr (void)
{
do_load_cr();
RETURN();
}
PPC_OP(store_cr)
void OPPROTO op_store_cr (void)
{
do_store_cr(PARAM(1));
do_store_cr(PARAM1);
RETURN();
}
@ -262,26 +252,26 @@ void OPPROTO op_store_cro (void)
RETURN();
}
PPC_OP(load_xer_cr)
void OPPROTO op_load_xer_cr (void)
{
T0 = (xer_so << 3) | (xer_ov << 2) | (xer_ca << 1);
RETURN();
}
PPC_OP(clear_xer_ov)
void OPPROTO op_clear_xer_ov (void)
{
xer_so = 0;
xer_ov = 0;
RETURN();
}
PPC_OP(clear_xer_ca)
void OPPROTO op_clear_xer_ca (void)
{
xer_ca = 0;
RETURN();
}
PPC_OP(load_xer_bc)
void OPPROTO op_load_xer_bc (void)
{
T1 = xer_bc;
RETURN();
@ -293,13 +283,13 @@ void OPPROTO op_store_xer_bc (void)
RETURN();
}
PPC_OP(load_xer)
void OPPROTO op_load_xer (void)
{
do_load_xer();
RETURN();
}
PPC_OP(store_xer)
void OPPROTO op_store_xer (void)
{
do_store_xer();
RETURN();
@ -307,25 +297,25 @@ PPC_OP(store_xer)
#if !defined(CONFIG_USER_ONLY)
/* Segment registers load and store */
PPC_OP(load_sr)
void OPPROTO op_load_sr (void)
{
T0 = regs->sr[T1];
T0 = env->sr[T1];
RETURN();
}
PPC_OP(store_sr)
void OPPROTO op_store_sr (void)
{
do_store_sr(env, T1, T0);
RETURN();
}
PPC_OP(load_sdr1)
void OPPROTO op_load_sdr1 (void)
{
T0 = regs->sdr1;
T0 = env->sdr1;
RETURN();
}
PPC_OP(store_sdr1)
void OPPROTO op_store_sdr1 (void)
{
do_store_sdr1(env, T0);
RETURN();
@ -345,13 +335,13 @@ void OPPROTO op_store_asr (void)
}
#endif
PPC_OP(load_msr)
void OPPROTO op_load_msr (void)
{
T0 = do_load_msr(env);
RETURN();
}
PPC_OP(store_msr)
void OPPROTO op_store_msr (void)
{
do_store_msr(env, T0);
RETURN();
@ -397,70 +387,70 @@ void OPPROTO op_mask_spr (void)
RETURN();
}
PPC_OP(load_lr)
void OPPROTO op_load_lr (void)
{
T0 = regs->lr;
T0 = env->lr;
RETURN();
}
PPC_OP(store_lr)
void OPPROTO op_store_lr (void)
{
regs->lr = T0;
env->lr = T0;
RETURN();
}
PPC_OP(load_ctr)
void OPPROTO op_load_ctr (void)
{
T0 = regs->ctr;
T0 = env->ctr;
RETURN();
}
PPC_OP(store_ctr)
void OPPROTO op_store_ctr (void)
{
regs->ctr = T0;
env->ctr = T0;
RETURN();
}
PPC_OP(load_tbl)
void OPPROTO op_load_tbl (void)
{
T0 = cpu_ppc_load_tbl(regs);
T0 = cpu_ppc_load_tbl(env);
RETURN();
}
PPC_OP(load_tbu)
void OPPROTO op_load_tbu (void)
{
T0 = cpu_ppc_load_tbu(regs);
T0 = cpu_ppc_load_tbu(env);
RETURN();
}
#if !defined(CONFIG_USER_ONLY)
PPC_OP(store_tbl)
void OPPROTO op_store_tbl (void)
{
cpu_ppc_store_tbl(regs, T0);
cpu_ppc_store_tbl(env, T0);
RETURN();
}
PPC_OP(store_tbu)
void OPPROTO op_store_tbu (void)
{
cpu_ppc_store_tbu(regs, T0);
cpu_ppc_store_tbu(env, T0);
RETURN();
}
PPC_OP(load_decr)
void OPPROTO op_load_decr (void)
{
T0 = cpu_ppc_load_decr(regs);
T0 = cpu_ppc_load_decr(env);
RETURN();
}
PPC_OP(store_decr)
void OPPROTO op_store_decr (void)
{
cpu_ppc_store_decr(regs, T0);
cpu_ppc_store_decr(env, T0);
RETURN();
}
PPC_OP(load_ibat)
void OPPROTO op_load_ibat (void)
{
T0 = regs->IBAT[PARAM(1)][PARAM(2)];
T0 = env->IBAT[PARAM1][PARAM2];
RETURN();
}
@ -480,9 +470,9 @@ void OPPROTO op_store_ibatl (void)
RETURN();
}
PPC_OP(load_dbat)
void OPPROTO op_load_dbat (void)
{
T0 = regs->DBAT[PARAM(1)][PARAM(2)];
T0 = env->DBAT[PARAM1][PARAM2];
RETURN();
}
@ -504,85 +494,85 @@ void OPPROTO op_store_dbatl (void)
#endif /* !defined(CONFIG_USER_ONLY) */
/* FPSCR */
PPC_OP(load_fpscr)
void OPPROTO op_load_fpscr (void)
{
do_load_fpscr();
RETURN();
}
PPC_OP(store_fpscr)
void OPPROTO op_store_fpscr (void)
{
do_store_fpscr(PARAM1);
RETURN();
}
PPC_OP(reset_scrfx)
void OPPROTO op_reset_scrfx (void)
{
regs->fpscr[7] &= ~0x8;
env->fpscr[7] &= ~0x8;
RETURN();
}
/* crf operations */
PPC_OP(getbit_T0)
void OPPROTO op_getbit_T0 (void)
{
T0 = (T0 >> PARAM(1)) & 1;
T0 = (T0 >> PARAM1) & 1;
RETURN();
}
PPC_OP(getbit_T1)
void OPPROTO op_getbit_T1 (void)
{
T1 = (T1 >> PARAM(1)) & 1;
T1 = (T1 >> PARAM1) & 1;
RETURN();
}
PPC_OP(setcrfbit)
void OPPROTO op_setcrfbit (void)
{
T1 = (T1 & PARAM(1)) | (T0 << PARAM(2));
T1 = (T1 & PARAM1) | (T0 << PARAM2);
RETURN();
}
/* Branch */
#define EIP regs->nip
#define EIP env->nip
PPC_OP(setlr)
void OPPROTO op_setlr (void)
{
regs->lr = (uint32_t)PARAM1;
env->lr = (uint32_t)PARAM1;
RETURN();
}
#if defined (TARGET_PPC64)
void OPPROTO op_setlr_64 (void)
{
regs->lr = ((uint64_t)PARAM1 << 32) | (uint64_t)PARAM2;
env->lr = ((uint64_t)PARAM1 << 32) | (uint64_t)PARAM2;
RETURN();
}
#endif
PPC_OP(goto_tb0)
void OPPROTO op_goto_tb0 (void)
{
GOTO_TB(op_goto_tb0, PARAM1, 0);
}
PPC_OP(goto_tb1)
void OPPROTO op_goto_tb1 (void)
{
GOTO_TB(op_goto_tb1, PARAM1, 1);
}
void OPPROTO op_b_T1 (void)
{
regs->nip = (uint32_t)(T1 & ~3);
env->nip = (uint32_t)(T1 & ~3);
RETURN();
}
#if defined (TARGET_PPC64)
void OPPROTO op_b_T1_64 (void)
{
regs->nip = (uint64_t)(T1 & ~3);
env->nip = (uint64_t)(T1 & ~3);
RETURN();
}
#endif
PPC_OP(jz_T0)
void OPPROTO op_jz_T0 (void)
{
if (!T0)
GOTO_LABEL_PARAM(1);
@ -592,9 +582,9 @@ PPC_OP(jz_T0)
void OPPROTO op_btest_T1 (void)
{
if (T0) {
regs->nip = (uint32_t)(T1 & ~3);
env->nip = (uint32_t)(T1 & ~3);
} else {
regs->nip = (uint32_t)PARAM1;
env->nip = (uint32_t)PARAM1;
}
RETURN();
}
@ -603,133 +593,133 @@ void OPPROTO op_btest_T1 (void)
void OPPROTO op_btest_T1_64 (void)
{
if (T0) {
regs->nip = (uint64_t)(T1 & ~3);
env->nip = (uint64_t)(T1 & ~3);
} else {
regs->nip = ((uint64_t)PARAM1 << 32) | (uint64_t)PARAM2;
env->nip = ((uint64_t)PARAM1 << 32) | (uint64_t)PARAM2;
}
RETURN();
}
#endif
PPC_OP(movl_T1_ctr)
void OPPROTO op_movl_T1_ctr (void)
{
T1 = regs->ctr;
T1 = env->ctr;
RETURN();
}
PPC_OP(movl_T1_lr)
void OPPROTO op_movl_T1_lr (void)
{
T1 = regs->lr;
T1 = env->lr;
RETURN();
}
/* tests with result in T0 */
void OPPROTO op_test_ctr (void)
{
T0 = (uint32_t)regs->ctr;
T0 = (uint32_t)env->ctr;
RETURN();
}
#if defined(TARGET_PPC64)
void OPPROTO op_test_ctr_64 (void)
{
T0 = (uint64_t)regs->ctr;
T0 = (uint64_t)env->ctr;
RETURN();
}
#endif
void OPPROTO op_test_ctr_true (void)
{
T0 = ((uint32_t)regs->ctr != 0 && (T0 & PARAM1) != 0);
T0 = ((uint32_t)env->ctr != 0 && (T0 & PARAM1) != 0);
RETURN();
}
#if defined(TARGET_PPC64)
void OPPROTO op_test_ctr_true_64 (void)
{
T0 = ((uint64_t)regs->ctr != 0 && (T0 & PARAM1) != 0);
T0 = ((uint64_t)env->ctr != 0 && (T0 & PARAM1) != 0);
RETURN();
}
#endif
void OPPROTO op_test_ctr_false (void)
{
T0 = ((uint32_t)regs->ctr != 0 && (T0 & PARAM1) == 0);
T0 = ((uint32_t)env->ctr != 0 && (T0 & PARAM1) == 0);
RETURN();
}
#if defined(TARGET_PPC64)
void OPPROTO op_test_ctr_false_64 (void)
{
T0 = ((uint64_t)regs->ctr != 0 && (T0 & PARAM1) == 0);
T0 = ((uint64_t)env->ctr != 0 && (T0 & PARAM1) == 0);
RETURN();
}
#endif
void OPPROTO op_test_ctrz (void)
{
T0 = ((uint32_t)regs->ctr == 0);
T0 = ((uint32_t)env->ctr == 0);
RETURN();
}
#if defined(TARGET_PPC64)
void OPPROTO op_test_ctrz_64 (void)
{
T0 = ((uint64_t)regs->ctr == 0);
T0 = ((uint64_t)env->ctr == 0);
RETURN();
}
#endif
void OPPROTO op_test_ctrz_true (void)
{
T0 = ((uint32_t)regs->ctr == 0 && (T0 & PARAM1) != 0);
T0 = ((uint32_t)env->ctr == 0 && (T0 & PARAM1) != 0);
RETURN();
}
#if defined(TARGET_PPC64)
void OPPROTO op_test_ctrz_true_64 (void)
{
T0 = ((uint64_t)regs->ctr == 0 && (T0 & PARAM1) != 0);
T0 = ((uint64_t)env->ctr == 0 && (T0 & PARAM1) != 0);
RETURN();
}
#endif
void OPPROTO op_test_ctrz_false (void)
{
T0 = ((uint32_t)regs->ctr == 0 && (T0 & PARAM1) == 0);
T0 = ((uint32_t)env->ctr == 0 && (T0 & PARAM1) == 0);
RETURN();
}
#if defined(TARGET_PPC64)
void OPPROTO op_test_ctrz_false_64 (void)
{
T0 = ((uint64_t)regs->ctr == 0 && (T0 & PARAM1) == 0);
T0 = ((uint64_t)env->ctr == 0 && (T0 & PARAM1) == 0);
RETURN();
}
#endif
PPC_OP(test_true)
void OPPROTO op_test_true (void)
{
T0 = (T0 & PARAM(1));
T0 = (T0 & PARAM1);
RETURN();
}
PPC_OP(test_false)
void OPPROTO op_test_false (void)
{
T0 = ((T0 & PARAM(1)) == 0);
T0 = ((T0 & PARAM1) == 0);
RETURN();
}
/* CTR maintenance */
PPC_OP(dec_ctr)
void OPPROTO op_dec_ctr (void)
{
regs->ctr--;
env->ctr--;
RETURN();
}
/*** Integer arithmetic ***/
/* add */
PPC_OP(add)
void OPPROTO op_add (void)
{
T0 += T1;
RETURN();
@ -800,9 +790,9 @@ void OPPROTO op_adde_64 (void)
#endif
/* add immediate */
PPC_OP(addi)
void OPPROTO op_addi (void)
{
T0 += (int32_t)PARAM(1);
T0 += (int32_t)PARAM1;
RETURN();
}
@ -957,14 +947,14 @@ void OPPROTO op_mulhdu (void)
#endif
/* multiply low immediate */
PPC_OP(mulli)
void OPPROTO op_mulli (void)
{
T0 = ((int32_t)T0 * (int32_t)PARAM1);
RETURN();
}
/* multiply low word */
PPC_OP(mullw)
void OPPROTO op_mullw (void)
{
T0 = (int32_t)(T0 * T1);
RETURN();
@ -1026,7 +1016,7 @@ void OPPROTO op_nego_64 (void)
#endif
/* subtract from */
PPC_OP(subf)
void OPPROTO op_subf (void)
{
T0 = T1 - T0;
RETURN();
@ -1329,14 +1319,14 @@ void OPPROTO op_popcntb_64 (void)
/*** Integer logical ***/
/* and */
PPC_OP(and)
void OPPROTO op_and (void)
{
T0 &= T1;
RETURN();
}
/* andc */
PPC_OP(andc)
void OPPROTO op_andc (void)
{
T0 &= ~T1;
RETURN();
@ -1345,7 +1335,7 @@ PPC_OP(andc)
/* andi. */
void OPPROTO op_andi_T0 (void)
{
T0 &= PARAM(1);
T0 &= PARAM1;
RETURN();
}
@ -1371,7 +1361,7 @@ void OPPROTO op_cntlzd (void)
#endif
/* eqv */
PPC_OP(eqv)
void OPPROTO op_eqv (void)
{
T0 = ~(T0 ^ T1);
RETURN();
@ -1408,51 +1398,51 @@ void OPPROTO op_extsw (void)
#endif
/* nand */
PPC_OP(nand)
void OPPROTO op_nand (void)
{
T0 = ~(T0 & T1);
RETURN();
}
/* nor */
PPC_OP(nor)
void OPPROTO op_nor (void)
{
T0 = ~(T0 | T1);
RETURN();
}
/* or */
PPC_OP(or)
void OPPROTO op_or (void)
{
T0 |= T1;
RETURN();
}
/* orc */
PPC_OP(orc)
void OPPROTO op_orc (void)
{
T0 |= ~T1;
RETURN();
}
/* ori */
PPC_OP(ori)
void OPPROTO op_ori (void)
{
T0 |= PARAM(1);
T0 |= PARAM1;
RETURN();
}
/* xor */
PPC_OP(xor)
void OPPROTO op_xor (void)
{
T0 ^= T1;
RETURN();
}
/* xori */
PPC_OP(xori)
void OPPROTO op_xori (void)
{
T0 ^= PARAM(1);
T0 ^= PARAM1;
RETURN();
}
@ -1630,56 +1620,56 @@ void OPPROTO op_srli_T1_64 (void)
/*** Floating-Point arithmetic ***/
/* fadd - fadd. */
PPC_OP(fadd)
void OPPROTO op_fadd (void)
{
FT0 = float64_add(FT0, FT1, &env->fp_status);
RETURN();
}
/* fsub - fsub. */
PPC_OP(fsub)
void OPPROTO op_fsub (void)
{
FT0 = float64_sub(FT0, FT1, &env->fp_status);
RETURN();
}
/* fmul - fmul. */
PPC_OP(fmul)
void OPPROTO op_fmul (void)
{
FT0 = float64_mul(FT0, FT1, &env->fp_status);
RETURN();
}
/* fdiv - fdiv. */
PPC_OP(fdiv)
void OPPROTO op_fdiv (void)
{
FT0 = float64_div(FT0, FT1, &env->fp_status);
RETURN();
}
/* fsqrt - fsqrt. */
PPC_OP(fsqrt)
void OPPROTO op_fsqrt (void)
{
do_fsqrt();
RETURN();
}
/* fres - fres. */
PPC_OP(fres)
void OPPROTO op_fres (void)
{
do_fres();
RETURN();
}
/* frsqrte - frsqrte. */
PPC_OP(frsqrte)
void OPPROTO op_frsqrte (void)
{
do_frsqrte();
RETURN();
}
/* fsel - fsel. */
PPC_OP(fsel)
void OPPROTO op_fsel (void)
{
do_fsel();
RETURN();
@ -1687,7 +1677,7 @@ PPC_OP(fsel)
/*** Floating-Point multiply-and-add ***/
/* fmadd - fmadd. */
PPC_OP(fmadd)
void OPPROTO op_fmadd (void)
{
#if USE_PRECISE_EMULATION
do_fmadd();
@ -1699,7 +1689,7 @@ PPC_OP(fmadd)
}
/* fmsub - fmsub. */
PPC_OP(fmsub)
void OPPROTO op_fmsub (void)
{
#if USE_PRECISE_EMULATION
do_fmsub();
@ -1711,14 +1701,14 @@ PPC_OP(fmsub)
}
/* fnmadd - fnmadd. - fnmadds - fnmadds. */
PPC_OP(fnmadd)
void OPPROTO op_fnmadd (void)
{
do_fnmadd();
RETURN();
}
/* fnmsub - fnmsub. */
PPC_OP(fnmsub)
void OPPROTO op_fnmsub (void)
{
do_fnmsub();
RETURN();
@ -1726,21 +1716,21 @@ PPC_OP(fnmsub)
/*** Floating-Point round & convert ***/
/* frsp - frsp. */
PPC_OP(frsp)
void OPPROTO op_frsp (void)
{
FT0 = float64_to_float32(FT0, &env->fp_status);
RETURN();
}
/* fctiw - fctiw. */
PPC_OP(fctiw)
void OPPROTO op_fctiw (void)
{
do_fctiw();
RETURN();
}
/* fctiwz - fctiwz. */
PPC_OP(fctiwz)
void OPPROTO op_fctiwz (void)
{
do_fctiwz();
RETURN();
@ -1748,21 +1738,21 @@ PPC_OP(fctiwz)
#if defined(TARGET_PPC64)
/* fcfid - fcfid. */
PPC_OP(fcfid)
void OPPROTO op_fcfid (void)
{
do_fcfid();
RETURN();
}
/* fctid - fctid. */
PPC_OP(fctid)
void OPPROTO op_fctid (void)
{
do_fctid();
RETURN();
}
/* fctidz - fctidz. */
PPC_OP(fctidz)
void OPPROTO op_fctidz (void)
{
do_fctidz();
RETURN();
@ -1771,14 +1761,14 @@ PPC_OP(fctidz)
/*** Floating-Point compare ***/
/* fcmpu */
PPC_OP(fcmpu)
void OPPROTO op_fcmpu (void)
{
do_fcmpu();
RETURN();
}
/* fcmpo */
PPC_OP(fcmpo)
void OPPROTO op_fcmpo (void)
{
do_fcmpo();
RETURN();
@ -1786,14 +1776,14 @@ PPC_OP(fcmpo)
/*** Floating-point move ***/
/* fabs */
PPC_OP(fabs)
void OPPROTO op_fabs (void)
{
FT0 = float64_abs(FT0);
RETURN();
}
/* fnabs */
PPC_OP(fnabs)
void OPPROTO op_fnabs (void)
{
FT0 = float64_abs(FT0);
FT0 = float64_chs(FT0);
@ -1801,7 +1791,7 @@ PPC_OP(fnabs)
}
/* fneg */
PPC_OP(fneg)
void OPPROTO op_fneg (void)
{
FT0 = float64_chs(FT0);
RETURN();
@ -1871,7 +1861,7 @@ void OPPROTO op_td (void)
#if !defined(CONFIG_USER_ONLY)
/* tlbia */
PPC_OP(tlbia)
void OPPROTO op_tlbia (void)
{
do_tlbia();
RETURN();

11
target-ppc/op_helper.c
View File

@ -88,7 +88,7 @@ void do_store_cr (uint32_t mask)
{
int i, sh;
for (i = 0, sh = 7; i < 8; i++, sh --) {
for (i = 0, sh = 7; i < 8; i++, sh--) {
if (mask & (1 << sh))
env->crf[i] = (T0 >> (sh * 4)) & 0xFUL;
}
@ -216,8 +216,8 @@ static void add128 (uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
static void neg128 (uint64_t *plow, uint64_t *phigh)
{
*plow = ~ *plow;
*phigh = ~ *phigh;
*plow = ~*plow;
*phigh = ~*phigh;
add128(plow, phigh, 1, 0);
}
@ -258,6 +258,7 @@ void do_mul64 (uint64_t *plow, uint64_t *phigh)
static void imul64 (uint64_t *plow, uint64_t *phigh, int64_t a, int64_t b)
{
int sa, sb;
sa = (a < 0);
if (sa)
a = -a;
@ -2493,14 +2494,14 @@ void do_4xx_tlbre_hi (void)
void do_4xx_tlbsx (void)
{
T0 = ppcemb_tlb_search(env, T0);
T0 = ppcemb_tlb_search(env, T0, env->spr[SPR_40x_PID]);
}
void do_4xx_tlbsx_ (void)
{
int tmp = xer_ov;
T0 = ppcemb_tlb_search(env, T0);
T0 = ppcemb_tlb_search(env, T0, env->spr[SPR_40x_PID]);
if (T0 != -1)
tmp |= 0x02;
env->crf[0] = tmp;

2
target-ppc/op_helper_mem.h
View File

@ -271,7 +271,7 @@ void glue(do_icbi_64, MEMSUFFIX) (void)
}
#endif
/* PPC 601 specific instructions (POWER bridge) */
/* PowerPC 601 specific instructions (POWER bridge) */
// XXX: to be tested
void glue(do_POWER_lscbx, MEMSUFFIX) (int dest, int ra, int rb)
{

48
target-ppc/op_mem.h
View File

@ -517,7 +517,7 @@ void OPPROTO glue(op_lwarx, MEMSUFFIX) (void)
do_raise_exception(EXCP_ALIGN);
} else {
T1 = glue(ldl, MEMSUFFIX)((uint32_t)T0);
regs->reserve = (uint32_t)T0;
env->reserve = (uint32_t)T0;
}
RETURN();
}
@ -529,7 +529,7 @@ void OPPROTO glue(op_lwarx_64, MEMSUFFIX) (void)
do_raise_exception(EXCP_ALIGN);
} else {
T1 = glue(ldl, MEMSUFFIX)((uint64_t)T0);
regs->reserve = (uint64_t)T0;
env->reserve = (uint64_t)T0;
}
RETURN();
}
@ -540,7 +540,7 @@ void OPPROTO glue(op_ldarx, MEMSUFFIX) (void)
do_raise_exception(EXCP_ALIGN);
} else {
T1 = glue(ldq, MEMSUFFIX)((uint32_t)T0);
regs->reserve = (uint32_t)T0;
env->reserve = (uint32_t)T0;
}
RETURN();
}
@ -551,7 +551,7 @@ void OPPROTO glue(op_ldarx_64, MEMSUFFIX) (void)
do_raise_exception(EXCP_ALIGN);
} else {
T1 = glue(ldq, MEMSUFFIX)((uint64_t)T0);
regs->reserve = (uint64_t)T0;
env->reserve = (uint64_t)T0;
}
RETURN();
}
@ -563,7 +563,7 @@ void OPPROTO glue(op_lwarx_le, MEMSUFFIX) (void)
do_raise_exception(EXCP_ALIGN);
} else {
T1 = glue(ld32r, MEMSUFFIX)((uint32_t)T0);
regs->reserve = (uint32_t)T0;
env->reserve = (uint32_t)T0;
}
RETURN();
}
@ -575,7 +575,7 @@ void OPPROTO glue(op_lwarx_le_64, MEMSUFFIX) (void)
do_raise_exception(EXCP_ALIGN);
} else {
T1 = glue(ld32r, MEMSUFFIX)((uint64_t)T0);
regs->reserve = (uint64_t)T0;
env->reserve = (uint64_t)T0;
}
RETURN();
}
@ -586,7 +586,7 @@ void OPPROTO glue(op_ldarx_le, MEMSUFFIX) (void)
do_raise_exception(EXCP_ALIGN);
} else {
T1 = glue(ld64r, MEMSUFFIX)((uint32_t)T0);
regs->reserve = (uint32_t)T0;
env->reserve = (uint32_t)T0;
}
RETURN();
}
@ -597,7 +597,7 @@ void OPPROTO glue(op_ldarx_le_64, MEMSUFFIX) (void)
do_raise_exception(EXCP_ALIGN);
} else {
T1 = glue(ld64r, MEMSUFFIX)((uint64_t)T0);
regs->reserve = (uint64_t)T0;
env->reserve = (uint64_t)T0;
}
RETURN();
}
@ -609,14 +609,14 @@ void OPPROTO glue(op_stwcx, MEMSUFFIX) (void)
if (unlikely(T0 & 0x03)) {
do_raise_exception(EXCP_ALIGN);
} else {
if (unlikely(regs->reserve != (uint32_t)T0)) {
if (unlikely(env->reserve != (uint32_t)T0)) {
env->crf[0] = xer_ov;
} else {
glue(stl, MEMSUFFIX)((uint32_t)T0, T1);
env->crf[0] = xer_ov | 0x02;
}
}
regs->reserve = -1;
env->reserve = -1;
RETURN();
}
@ -626,14 +626,14 @@ void OPPROTO glue(op_stwcx_64, MEMSUFFIX) (void)
if (unlikely(T0 & 0x03)) {
do_raise_exception(EXCP_ALIGN);
} else {
if (unlikely(regs->reserve != (uint64_t)T0)) {
if (unlikely(env->reserve != (uint64_t)T0)) {
env->crf[0] = xer_ov;
} else {
glue(stl, MEMSUFFIX)((uint64_t)T0, T1);
env->crf[0] = xer_ov | 0x02;
}
}
regs->reserve = -1;
env->reserve = -1;
RETURN();
}
@ -642,14 +642,14 @@ void OPPROTO glue(op_stdcx, MEMSUFFIX) (void)
if (unlikely(T0 & 0x03)) {
do_raise_exception(EXCP_ALIGN);
} else {
if (unlikely(regs->reserve != (uint32_t)T0)) {
if (unlikely(env->reserve != (uint32_t)T0)) {
env->crf[0] = xer_ov;
} else {
glue(stq, MEMSUFFIX)((uint32_t)T0, T1);
env->crf[0] = xer_ov | 0x02;
}
}
regs->reserve = -1;
env->reserve = -1;
RETURN();
}
@ -658,14 +658,14 @@ void OPPROTO glue(op_stdcx_64, MEMSUFFIX) (void)
if (unlikely(T0 & 0x03)) {
do_raise_exception(EXCP_ALIGN);
} else {
if (unlikely(regs->reserve != (uint64_t)T0)) {
if (unlikely(env->reserve != (uint64_t)T0)) {
env->crf[0] = xer_ov;
} else {
glue(stq, MEMSUFFIX)((uint64_t)T0, T1);
env->crf[0] = xer_ov | 0x02;
}
}
regs->reserve = -1;
env->reserve = -1;
RETURN();
}
#endif
@ -675,14 +675,14 @@ void OPPROTO glue(op_stwcx_le, MEMSUFFIX) (void)
if (unlikely(T0 & 0x03)) {
do_raise_exception(EXCP_ALIGN);
} else {
if (unlikely(regs->reserve != (uint32_t)T0)) {
if (unlikely(env->reserve != (uint32_t)T0)) {
env->crf[0] = xer_ov;
} else {
glue(st32r, MEMSUFFIX)((uint32_t)T0, T1);
env->crf[0] = xer_ov | 0x02;
}
}
regs->reserve = -1;
env->reserve = -1;
RETURN();
}
@ -692,14 +692,14 @@ void OPPROTO glue(op_stwcx_le_64, MEMSUFFIX) (void)
if (unlikely(T0 & 0x03)) {
do_raise_exception(EXCP_ALIGN);
} else {
if (unlikely(regs->reserve != (uint64_t)T0)) {
if (unlikely(env->reserve != (uint64_t)T0)) {
env->crf[0] = xer_ov;
} else {
glue(st32r, MEMSUFFIX)((uint64_t)T0, T1);
env->crf[0] = xer_ov | 0x02;
}
}
regs->reserve = -1;
env->reserve = -1;
RETURN();
}
@ -708,14 +708,14 @@ void OPPROTO glue(op_stdcx_le, MEMSUFFIX) (void)
if (unlikely(T0 & 0x03)) {
do_raise_exception(EXCP_ALIGN);
} else {
if (unlikely(regs->reserve != (uint32_t)T0)) {
if (unlikely(env->reserve != (uint32_t)T0)) {
env->crf[0] = xer_ov;
} else {
glue(st64r, MEMSUFFIX)((uint32_t)T0, T1);
env->crf[0] = xer_ov | 0x02;
}
}
regs->reserve = -1;
env->reserve = -1;
RETURN();
}
@ -724,14 +724,14 @@ void OPPROTO glue(op_stdcx_le_64, MEMSUFFIX) (void)
if (unlikely(T0 & 0x03)) {
do_raise_exception(EXCP_ALIGN);
} else {
if (unlikely(regs->reserve != (uint64_t)T0)) {
if (unlikely(env->reserve != (uint64_t)T0)) {
env->crf[0] = xer_ov;
} else {
glue(st64r, MEMSUFFIX)((uint64_t)T0, T1);
env->crf[0] = xer_ov | 0x02;
}
}
regs->reserve = -1;
env->reserve = -1;
RETURN();
}
#endif

42
target-ppc/op_template.h
View File

@ -21,38 +21,38 @@
/* General purpose registers moves */
void OPPROTO glue(op_load_gpr_T0_gpr, REG) (void)
{
T0 = regs->gpr[REG];
T0 = env->gpr[REG];
RETURN();
}
void OPPROTO glue(op_load_gpr_T1_gpr, REG) (void)
{
T1 = regs->gpr[REG];
T1 = env->gpr[REG];
RETURN();
}
void OPPROTO glue(op_load_gpr_T2_gpr, REG) (void)
{
T2 = regs->gpr[REG];
T2 = env->gpr[REG];
RETURN();
}
void OPPROTO glue(op_store_T0_gpr_gpr, REG) (void)
{
regs->gpr[REG] = T0;
env->gpr[REG] = T0;
RETURN();
}
void OPPROTO glue(op_store_T1_gpr_gpr, REG) (void)
{
regs->gpr[REG] = T1;
env->gpr[REG] = T1;
RETURN();
}
#if 0 // unused
void OPPROTO glue(op_store_T2_gpr_gpr, REG) (void)
{
regs->gpr[REG] = T2;
env->gpr[REG] = T2;
RETURN();
}
#endif
@ -60,40 +60,40 @@ void OPPROTO glue(op_store_T2_gpr_gpr, REG) (void)
#if defined(TARGET_PPCEMB)
void OPPROTO glue(op_load_gpr64_T0_gpr, REG) (void)
{
T0_64 = regs->gpr[REG];
T0_64 = env->gpr[REG];
RETURN();
}
void OPPROTO glue(op_load_gpr64_T1_gpr, REG) (void)
{
T1_64 = regs->gpr[REG];
T1_64 = env->gpr[REG];
RETURN();
}
#if 0 // unused
void OPPROTO glue(op_load_gpr64_T2_gpr, REG) (void)
{
T2_64 = regs->gpr[REG];
T2_64 = env->gpr[REG];
RETURN();
}
#endif
void OPPROTO glue(op_store_T0_gpr64_gpr, REG) (void)
{
regs->gpr[REG] = T0_64;
env->gpr[REG] = T0_64;
RETURN();
}
void OPPROTO glue(op_store_T1_gpr64_gpr, REG) (void)
{
regs->gpr[REG] = T1_64;
env->gpr[REG] = T1_64;
RETURN();
}
#if 0 // unused
void OPPROTO glue(op_store_T2_gpr64_gpr, REG) (void)
{
regs->gpr[REG] = T2_64;
env->gpr[REG] = T2_64;
RETURN();
}
#endif
@ -103,57 +103,57 @@ void OPPROTO glue(op_store_T2_gpr64_gpr, REG) (void)
/* Condition register moves */
void OPPROTO glue(op_load_crf_T0_crf, REG) (void)
{
T0 = regs->crf[REG];
T0 = env->crf[REG];
RETURN();
}
void OPPROTO glue(op_load_crf_T1_crf, REG) (void)
{
T1 = regs->crf[REG];
T1 = env->crf[REG];
RETURN();
}
void OPPROTO glue(op_store_T0_crf_crf, REG) (void)
{
regs->crf[REG] = T0;
env->crf[REG] = T0;
RETURN();
}
void OPPROTO glue(op_store_T1_crf_crf, REG) (void)
{
regs->crf[REG] = T1;
env->crf[REG] = T1;
RETURN();
}
/* Floating point condition and status register moves */
void OPPROTO glue(op_load_fpscr_T0_fpscr, REG) (void)
{
T0 = regs->fpscr[REG];
T0 = env->fpscr[REG];
RETURN();
}
#if REG == 0
void OPPROTO glue(op_store_T0_fpscr_fpscr, REG) (void)
{
regs->fpscr[REG] = (regs->fpscr[REG] & 0x9) | (T0 & ~0x9);
env->fpscr[REG] = (env->fpscr[REG] & 0x9) | (T0 & ~0x9);
RETURN();
}
void OPPROTO glue(op_clear_fpscr_fpscr, REG) (void)
{
regs->fpscr[REG] = (regs->fpscr[REG] & 0x9);
env->fpscr[REG] = (env->fpscr[REG] & 0x9);
RETURN();
}
#else
void OPPROTO glue(op_store_T0_fpscr_fpscr, REG) (void)
{
regs->fpscr[REG] = T0;
env->fpscr[REG] = T0;
RETURN();
}
void OPPROTO glue(op_clear_fpscr_fpscr, REG) (void)
{
regs->fpscr[REG] = 0x0;
env->fpscr[REG] = 0x0;
RETURN();
}
#endif

15
target-ppc/translate.c
View File

@ -118,7 +118,7 @@ GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
GEN8(gen_op_load_fpscr_T0, gen_op_load_fpscr_T0_fpscr);
GEN8(gen_op_store_T0_fpscr, gen_op_store_T0_fpscr_fpscr);
GEN8(gen_op_clear_fpscr, gen_op_clear_fpscr_fpscr);
static inline void gen_op_store_T0_fpscri(int n, uint8_t param)
static inline void gen_op_store_T0_fpscri (int n, uint8_t param)
{
gen_op_set_T0(param);
gen_op_store_T0_fpscr(n);
@ -1312,7 +1312,7 @@ static inline void gen_rldcl (DisasContext *ctx, int mbn)
mb = MB(ctx->opcode) | (mbn << 5);
gen_rldnm(ctx, mb, 63);
}
GEN_PPC64_R2(rldcl, 0x1E, 0x08)
GEN_PPC64_R2(rldcl, 0x1E, 0x08);
/* rldcr - rldcr. */
static inline void gen_rldcr (DisasContext *ctx, int men)
{
@ -1321,7 +1321,7 @@ static inline void gen_rldcr (DisasContext *ctx, int men)
me = MB(ctx->opcode) | (men << 5);
gen_rldnm(ctx, 0, me);
}
GEN_PPC64_R2(rldcr, 0x1E, 0x09)
GEN_PPC64_R2(rldcr, 0x1E, 0x09);
/* rldimi - rldimi. */
static inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
{
@ -1355,7 +1355,7 @@ static inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
if (unlikely(Rc(ctx->opcode) != 0))
gen_set_Rc0(ctx);
}
GEN_PPC64_R4(rldimi, 0x1E, 0x06)
GEN_PPC64_R4(rldimi, 0x1E, 0x06);
#endif
/*** Integer shift ***/
@ -2601,8 +2601,7 @@ GEN_HANDLER(stfiwx, 0x1F, 0x17, 0x1E, 0x00000001, PPC_FLOAT)
}
/*** Branch ***/
static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
static inline void gen_goto_tb (DisasContext *ctx, int n, target_ulong dest)
{
TranslationBlock *tb;
tb = ctx->tb;
@ -2669,7 +2668,7 @@ GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
#define BCOND_LR 1
#define BCOND_CTR 2
static inline void gen_bcond(DisasContext *ctx, int type)
static inline void gen_bcond (DisasContext *ctx, int type)
{
target_ulong target = 0;
target_ulong li;
@ -5585,7 +5584,7 @@ static inline uint32_t load_xer (CPUState *env)
(xer_cmp << XER_CMP);
}
void cpu_dump_state(CPUState *env, FILE *f,
void cpu_dump_state (CPUState *env, FILE *f,
int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
int flags)
{