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target/arm: Convert Neon 3-reg-same logic ops to decodetree

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Convert the Neon logic ops in the 3-reg-same grouping to decodetree.
Note that for the logic ops the 'size' field forms part of their
decode and the actual operations are always bitwise.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-16-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2020-04-30 19:09:42 +01:00
parent a4e143ac5b
commit 35a548edb6
3 changed files with 32 additions and 37 deletions
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12
target/arm/neon-dp.decode
View File

@ -42,5 +42,17 @@
@3same .... ... . . . size:2 .... .... .... . q:1 . . .... \
&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
@3same_logic .... ... . . . .. .... .... .... . q:1 .. .... \
&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0
VAND_3s 1111 001 0 0 . 00 .... .... 0001 ... 1 .... @3same_logic
VBIC_3s 1111 001 0 0 . 01 .... .... 0001 ... 1 .... @3same_logic
VORR_3s 1111 001 0 0 . 10 .... .... 0001 ... 1 .... @3same_logic
VORN_3s 1111 001 0 0 . 11 .... .... 0001 ... 1 .... @3same_logic
VEOR_3s 1111 001 1 0 . 00 .... .... 0001 ... 1 .... @3same_logic
VBSL_3s 1111 001 1 0 . 01 .... .... 0001 ... 1 .... @3same_logic
VBIT_3s 1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic
VBIF_3s 1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic
VADD_3s 1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same
VSUB_3s 1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same

19
target/arm/translate-neon.inc.c
View File

@ -598,3 +598,22 @@ static bool do_3same(DisasContext *s, arg_3same *a, GVecGen3Fn fn)
DO_3SAME(VADD, tcg_gen_gvec_add)
DO_3SAME(VSUB, tcg_gen_gvec_sub)
DO_3SAME(VAND, tcg_gen_gvec_and)
DO_3SAME(VBIC, tcg_gen_gvec_andc)
DO_3SAME(VORR, tcg_gen_gvec_or)
DO_3SAME(VORN, tcg_gen_gvec_orc)
DO_3SAME(VEOR, tcg_gen_gvec_xor)
/* These insns are all gvec_bitsel but with the inputs in various orders. */
#define DO_3SAME_BITSEL(INSN, O1, O2, O3) \
static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \
uint32_t rn_ofs, uint32_t rm_ofs, \
uint32_t oprsz, uint32_t maxsz) \
{ \
tcg_gen_gvec_bitsel(vece, rd_ofs, O1, O2, O3, oprsz, maxsz); \
} \
DO_3SAME(INSN, gen_##INSN##_3s)
DO_3SAME_BITSEL(VBSL, rd_ofs, rn_ofs, rm_ofs)
DO_3SAME_BITSEL(VBIT, rm_ofs, rn_ofs, rd_ofs)
DO_3SAME_BITSEL(VBIF, rm_ofs, rd_ofs, rn_ofs)

38
target/arm/translate.c
View File

@ -4848,43 +4848,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
}
return 1;
case NEON_3R_LOGIC: /* Logic ops. */
switch ((u << 2) | size) {
case 0: /* VAND */
tcg_gen_gvec_and(0, rd_ofs, rn_ofs, rm_ofs,
vec_size, vec_size);
break;
case 1: /* VBIC */
tcg_gen_gvec_andc(0, rd_ofs, rn_ofs, rm_ofs,
vec_size, vec_size);
break;
case 2: /* VORR */
tcg_gen_gvec_or(0, rd_ofs, rn_ofs, rm_ofs,
vec_size, vec_size);
break;
case 3: /* VORN */
tcg_gen_gvec_orc(0, rd_ofs, rn_ofs, rm_ofs,
vec_size, vec_size);
break;
case 4: /* VEOR */
tcg_gen_gvec_xor(0, rd_ofs, rn_ofs, rm_ofs,
vec_size, vec_size);
break;
case 5: /* VBSL */
tcg_gen_gvec_bitsel(MO_8, rd_ofs, rd_ofs, rn_ofs, rm_ofs,
vec_size, vec_size);
break;
case 6: /* VBIT */
tcg_gen_gvec_bitsel(MO_8, rd_ofs, rm_ofs, rn_ofs, rd_ofs,
vec_size, vec_size);
break;
case 7: /* VBIF */
tcg_gen_gvec_bitsel(MO_8, rd_ofs, rm_ofs, rd_ofs, rn_ofs,
vec_size, vec_size);
break;
}
return 0;
case NEON_3R_VQADD:
tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
rn_ofs, rm_ofs, vec_size, vec_size,
@ -4962,6 +4925,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
return 0;
case NEON_3R_VADD_VSUB:
case NEON_3R_LOGIC:
/* Already handled by decodetree */
return 1;
}