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PPC: Bamboo: Integrate SoC instatiation, use qdev for PCI
Now that we have the SoC init function in the same file, let's integrate it with the board initialization. While at it, also make use of the newly qdev'ified PCI host controller. Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Alexander Graf
parent
3960b04d62
commit
34ba1dc873
@ -27,6 +27,7 @@
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#include "ppc.h"
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#include "ppc405.h"
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#include "sysemu.h"
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#include "sysbus.h"
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#define BINARY_DEVICE_TREE_FILE "bamboo.dtb"
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@ -50,87 +51,6 @@ static const unsigned int ppc440ep_sdram_bank_sizes[] = {
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static target_phys_addr_t entry;
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static PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
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target_phys_addr_t config_space,
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target_phys_addr_t int_ack,
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target_phys_addr_t special_cycle,
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target_phys_addr_t registers)
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{
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return NULL;
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}
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CPUState *ppc440ep_init(MemoryRegion *address_space_mem, ram_addr_t *ram_size,
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PCIBus **pcip, const unsigned int pci_irq_nrs[4],
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int do_init, const char *cpu_model)
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{
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MemoryRegion *ram_memories
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= g_malloc(PPC440EP_SDRAM_NR_BANKS * sizeof(*ram_memories));
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target_phys_addr_t ram_bases[PPC440EP_SDRAM_NR_BANKS];
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target_phys_addr_t ram_sizes[PPC440EP_SDRAM_NR_BANKS];
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CPUState *env;
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qemu_irq *pic;
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qemu_irq *irqs;
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qemu_irq *pci_irqs;
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if (cpu_model == NULL) {
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cpu_model = "440EP";
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}
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env = cpu_init(cpu_model);
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if (!env) {
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fprintf(stderr, "Unable to initialize CPU!\n");
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exit(1);
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}
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ppc_booke_timers_init(env, 400000000, 0);
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ppc_dcr_init(env, NULL, NULL);
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/* interrupt controller */
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irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
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irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
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irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
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pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
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/* SDRAM controller */
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memset(ram_bases, 0, sizeof(ram_bases));
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memset(ram_sizes, 0, sizeof(ram_sizes));
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*ram_size = ppc4xx_sdram_adjust(*ram_size, PPC440EP_SDRAM_NR_BANKS,
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ram_memories,
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ram_bases, ram_sizes,
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ppc440ep_sdram_bank_sizes);
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/* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
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ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_memories,
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ram_bases, ram_sizes, do_init);
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/* PCI */
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pci_irqs = g_malloc(sizeof(qemu_irq) * 4);
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pci_irqs[0] = pic[pci_irq_nrs[0]];
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pci_irqs[1] = pic[pci_irq_nrs[1]];
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pci_irqs[2] = pic[pci_irq_nrs[2]];
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pci_irqs[3] = pic[pci_irq_nrs[3]];
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*pcip = ppc4xx_pci_init(env, pci_irqs,
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PPC440EP_PCI_CONFIG,
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PPC440EP_PCI_INTACK,
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PPC440EP_PCI_SPECIAL,
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PPC440EP_PCI_REGS);
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if (!*pcip)
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printf("couldn't create PCI controller!\n");
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isa_mmio_init(PPC440EP_PCI_IO, PPC440EP_PCI_IOLEN);
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if (serial_hds[0] != NULL) {
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serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
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PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
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DEVICE_BIG_ENDIAN);
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}
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if (serial_hds[1] != NULL) {
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serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
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PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
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DEVICE_BIG_ENDIAN);
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}
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return env;
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}
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static int bamboo_load_device_tree(target_phys_addr_t addr,
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uint32_t ramsize,
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target_phys_addr_t initrd_base,
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@ -245,19 +165,76 @@ static void bamboo_init(ram_addr_t ram_size,
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{
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unsigned int pci_irq_nrs[4] = { 28, 27, 26, 25 };
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MemoryRegion *address_space_mem = get_system_memory();
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MemoryRegion *ram_memories
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= g_malloc(PPC440EP_SDRAM_NR_BANKS * sizeof(*ram_memories));
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target_phys_addr_t ram_bases[PPC440EP_SDRAM_NR_BANKS];
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target_phys_addr_t ram_sizes[PPC440EP_SDRAM_NR_BANKS];
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qemu_irq *pic;
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qemu_irq *irqs;
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PCIBus *pcibus;
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CPUState *env;
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uint64_t elf_entry;
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uint64_t elf_lowaddr;
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target_phys_addr_t loadaddr = 0;
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target_long initrd_size = 0;
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DeviceState *dev;
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int success;
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int i;
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/* Setup CPU. */
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env = ppc440ep_init(address_space_mem, &ram_size, &pcibus,
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pci_irq_nrs, 1, cpu_model);
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if (cpu_model == NULL) {
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cpu_model = "440EP";
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}
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env = cpu_init(cpu_model);
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if (!env) {
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fprintf(stderr, "Unable to initialize CPU!\n");
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exit(1);
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}
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qemu_register_reset(main_cpu_reset, env);
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ppc_booke_timers_init(env, 400000000, 0);
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ppc_dcr_init(env, NULL, NULL);
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/* interrupt controller */
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irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
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irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
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irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
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pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
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/* SDRAM controller */
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memset(ram_bases, 0, sizeof(ram_bases));
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memset(ram_sizes, 0, sizeof(ram_sizes));
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ram_size = ppc4xx_sdram_adjust(ram_size, PPC440EP_SDRAM_NR_BANKS,
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ram_memories,
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ram_bases, ram_sizes,
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ppc440ep_sdram_bank_sizes);
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/* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
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ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_memories,
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ram_bases, ram_sizes, 1);
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/* PCI */
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dev = sysbus_create_varargs("ppc4xx-pcihost", PPC440EP_PCI_CONFIG,
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pic[pci_irq_nrs[0]], pic[pci_irq_nrs[1]],
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pic[pci_irq_nrs[2]], pic[pci_irq_nrs[3]],
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NULL);
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pcibus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
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if (!pcibus) {
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fprintf(stderr, "couldn't create PCI controller!\n");
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exit(1);
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}
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isa_mmio_init(PPC440EP_PCI_IO, PPC440EP_PCI_IOLEN);
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if (serial_hds[0] != NULL) {
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serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
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PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
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DEVICE_BIG_ENDIAN);
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}
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if (serial_hds[1] != NULL) {
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serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
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PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
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DEVICE_BIG_ENDIAN);
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}
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if (pcibus) {
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/* Register network interfaces. */
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