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e1000: Make little endian

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The e1000 has compatibility code to handle big endianness which makes it
mandatory to be recompiled on different targets.

With the generic mmio endianness solution, there's no need for that anymore.
We just declare all mmio to be little endian and call it a day.

Because we don't depend on the target endianness anymore, we can also
move the driver over to Makefile.objs.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Alexander Graf 2010-12-08 12:05:42 +01:00 committed by Blue Swirl
parent f23cea4d04
commit 32600a309f
3 changed files with 3 additions and 10 deletions
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1
Makefile.objs
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@ -224,6 +224,7 @@ hw-obj-$(CONFIG_NE2000_PCI) += ne2000.o
hw-obj-$(CONFIG_EEPRO100_PCI) += eepro100.o
hw-obj-$(CONFIG_PCNET_PCI) += pcnet-pci.o
hw-obj-$(CONFIG_PCNET_COMMON) += pcnet.o
hw-obj-$(CONFIG_E1000_PCI) += e1000.o
hw-obj-$(CONFIG_SMC91C111) += smc91c111.o
hw-obj-$(CONFIG_LAN9118) += lan9118.o

1
Makefile.target
View File

@ -211,7 +211,6 @@ obj-$(CONFIG_USB_OHCI) += usb-ohci.o
# PCI network cards
obj-$(CONFIG_RTL8139_PCI) += rtl8139.o
obj-$(CONFIG_E1000_PCI) += e1000.o
# Inter-VM PCI shared memory
obj-$(CONFIG_KVM) += ivshmem.o

11
hw/e1000.c
View File

@ -857,9 +857,6 @@ e1000_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
E1000State *s = opaque;
unsigned int index = (addr & 0x1ffff) >> 2;
#ifdef TARGET_WORDS_BIGENDIAN
val = bswap32(val);
#endif
if (index < NWRITEOPS && macreg_writeops[index]) {
macreg_writeops[index](s, index, val);
} else if (index < NREADOPS && macreg_readops[index]) {
@ -894,11 +891,7 @@ e1000_mmio_readl(void *opaque, target_phys_addr_t addr)
if (index < NREADOPS && macreg_readops[index])
{
uint32_t val = macreg_readops[index](s, index);
#ifdef TARGET_WORDS_BIGENDIAN
val = bswap32(val);
#endif
return val;
return macreg_readops[index](s, index);
}
DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2);
return 0;
@ -1131,7 +1124,7 @@ static int pci_e1000_init(PCIDevice *pci_dev)
pci_conf[PCI_INTERRUPT_PIN] = 1; // interrupt pin 0
d->mmio_index = cpu_register_io_memory(e1000_mmio_read,
e1000_mmio_write, d, DEVICE_NATIVE_ENDIAN);
e1000_mmio_write, d, DEVICE_LITTLE_ENDIAN);
pci_register_bar(&d->dev, 0, PNPMMIO_SIZE,
PCI_BASE_ADDRESS_SPACE_MEMORY, e1000_mmio_map);