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memory: add owner argument to initialization functions

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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2013-06-06 05:41:28 -04:00
parent 5767e4e198
commit 2c9b15cab1
319 changed files with 787 additions and 759 deletions
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14
exec.c
View File

@ -1673,7 +1673,7 @@ static subpage_t *subpage_init(AddressSpace *as, hwaddr base)
mmio->as = as;
mmio->base = base;
memory_region_init_io(&mmio->iomem, &subpage_ops, mmio,
memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio,
"subpage", TARGET_PAGE_SIZE);
mmio->iomem.subpage = true;
#if defined(DEBUG_SUBPAGE)
@ -1704,12 +1704,12 @@ MemoryRegion *iotlb_to_region(hwaddr index)
static void io_mem_init(void)
{
memory_region_init_io(&io_mem_rom, &unassigned_mem_ops, NULL, "rom", UINT64_MAX);
memory_region_init_io(&io_mem_unassigned, &unassigned_mem_ops, NULL,
memory_region_init_io(&io_mem_rom, NULL, &unassigned_mem_ops, NULL, "rom", UINT64_MAX);
memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL,
"unassigned", UINT64_MAX);
memory_region_init_io(&io_mem_notdirty, &notdirty_mem_ops, NULL,
memory_region_init_io(&io_mem_notdirty, NULL, &notdirty_mem_ops, NULL,
"notdirty", UINT64_MAX);
memory_region_init_io(&io_mem_watch, &watch_mem_ops, NULL,
memory_region_init_io(&io_mem_watch, NULL, &watch_mem_ops, NULL,
"watch", UINT64_MAX);
}
@ -1792,11 +1792,11 @@ void address_space_destroy_dispatch(AddressSpace *as)
static void memory_map_init(void)
{
system_memory = g_malloc(sizeof(*system_memory));
memory_region_init(system_memory, "system", INT64_MAX);
memory_region_init(system_memory, NULL, "system", INT64_MAX);
address_space_init(&address_space_memory, system_memory, "memory");
system_io = g_malloc(sizeof(*system_io));
memory_region_init(system_io, "io", 65536);
memory_region_init(system_io, NULL, "io", 65536);
address_space_init(&address_space_io, system_io, "I/O");
memory_listener_register(&core_memory_listener, &address_space_memory);

6
hw/acpi/core.c
View File

@ -419,7 +419,7 @@ void acpi_pm1_evt_init(ACPIREGS *ar, acpi_update_sci_fn update_sci,
MemoryRegion *parent)
{
ar->pm1.evt.update_sci = update_sci;
memory_region_init_io(&ar->pm1.evt.io, &acpi_pm_evt_ops, ar, "acpi-evt", 4);
memory_region_init_io(&ar->pm1.evt.io, NULL, &acpi_pm_evt_ops, ar, "acpi-evt", 4);
memory_region_add_subregion(parent, 0, &ar->pm1.evt.io);
}
@ -481,7 +481,7 @@ void acpi_pm_tmr_init(ACPIREGS *ar, acpi_update_sci_fn update_sci,
{
ar->tmr.update_sci = update_sci;
ar->tmr.timer = qemu_new_timer_ns(vm_clock, acpi_pm_tmr_timer, ar);
memory_region_init_io(&ar->tmr.io, &acpi_pm_tmr_ops, ar, "acpi-tmr", 4);
memory_region_init_io(&ar->tmr.io, NULL, &acpi_pm_tmr_ops, ar, "acpi-tmr", 4);
memory_region_add_subregion(parent, 8, &ar->tmr.io);
}
@ -552,7 +552,7 @@ void acpi_pm1_cnt_init(ACPIREGS *ar, MemoryRegion *parent, uint8_t s4_val)
ar->pm1.cnt.s4_val = s4_val;
ar->wakeup.notify = acpi_notify_wakeup;
qemu_register_wakeup_notifier(&ar->wakeup);
memory_region_init_io(&ar->pm1.cnt.io, &acpi_pm_cnt_ops, ar, "acpi-cnt", 2);
memory_region_init_io(&ar->pm1.cnt.io, NULL, &acpi_pm_cnt_ops, ar, "acpi-cnt", 2);
memory_region_add_subregion(parent, 4, &ar->pm1.cnt.io);
}

6
hw/acpi/ich9.c
View File

@ -205,7 +205,7 @@ static void pm_powerdown_req(Notifier *n, void *opaque)
void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
qemu_irq sci_irq)
{
memory_region_init(&pm->io, "ich9-pm", ICH9_PMIO_SIZE);
memory_region_init(&pm->io, NULL, "ich9-pm", ICH9_PMIO_SIZE);
memory_region_set_enabled(&pm->io, false);
memory_region_add_subregion(pci_address_space_io(lpc_pci),
0, &pm->io);
@ -215,11 +215,11 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
acpi_pm1_cnt_init(&pm->acpi_regs, &pm->io, 2);
acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN);
memory_region_init_io(&pm->io_gpe, &ich9_gpe_ops, pm, "apci-gpe0",
memory_region_init_io(&pm->io_gpe, NULL, &ich9_gpe_ops, pm, "apci-gpe0",
ICH9_PMIO_GPE0_LEN);
memory_region_add_subregion(&pm->io, ICH9_PMIO_GPE0_STS, &pm->io_gpe);
memory_region_init_io(&pm->io_smi, &ich9_smi_ops, pm, "apci-smi",
memory_region_init_io(&pm->io_smi, NULL, &ich9_smi_ops, pm, "apci-smi",
8);
memory_region_add_subregion(&pm->io, ICH9_PMIO_SMI_EN, &pm->io_smi);

8
hw/acpi/piix4.c
View File

@ -424,7 +424,7 @@ static int piix4_pm_initfn(PCIDevice *dev)
memory_region_add_subregion(pci_address_space_io(dev),
s->smb_io_base, &s->smb.io);
memory_region_init(&s->io, "piix4-pm", 64);
memory_region_init(&s->io, NULL, "piix4-pm", 64);
memory_region_set_enabled(&s->io, false);
memory_region_add_subregion(pci_address_space_io(dev),
0, &s->io);
@ -671,18 +671,18 @@ static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
PCIBus *bus, PIIX4PMState *s)
{
memory_region_init_io(&s->io_gpe, &piix4_gpe_ops, s, "apci-gpe0",
memory_region_init_io(&s->io_gpe, NULL, &piix4_gpe_ops, s, "apci-gpe0",
GPE_LEN);
memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe);
memory_region_init_io(&s->io_pci, &piix4_pci_ops, s, "apci-pci-hotplug",
memory_region_init_io(&s->io_pci, NULL, &piix4_pci_ops, s, "apci-pci-hotplug",
PCI_HOTPLUG_SIZE);
memory_region_add_subregion(parent, PCI_HOTPLUG_ADDR,
&s->io_pci);
pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);
qemu_for_each_cpu(piix4_init_cpu_status, &s->gpe_cpu);
memory_region_init_io(&s->io_cpu, &cpu_hotplug_ops, s, "apci-cpu-hotplug",
memory_region_init_io(&s->io_cpu, NULL, &cpu_hotplug_ops, s, "apci-cpu-hotplug",
PIIX4_PROC_LEN);
memory_region_add_subregion(parent, PIIX4_PROC_BASE, &s->io_cpu);
s->cpu_added_notifier.notify = piix4_cpu_added_req;

16
hw/alpha/typhoon.c
View File

@ -741,7 +741,7 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
/* Main memory region, 0x00.0000.0000. Real hardware supports 32GB,
but the address space hole reserved at this point is 8TB. */
memory_region_init_ram(&s->ram_region, "ram", ram_size);
memory_region_init_ram(&s->ram_region, NULL, "ram", ram_size);
vmstate_register_ram_global(&s->ram_region);
memory_region_add_subregion(addr_space, 0, &s->ram_region);
@ -750,22 +750,22 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
the flash ROM. I'm not sure that we need to implement it at all. */
/* Pchip0 CSRs, 0x801.8000.0000, 256MB. */
memory_region_init_io(&s->pchip.region, &pchip_ops, s, "pchip0", 256*MB);
memory_region_init_io(&s->pchip.region, NULL, &pchip_ops, s, "pchip0", 256*MB);
memory_region_add_subregion(addr_space, 0x80180000000ULL,
&s->pchip.region);
/* Cchip CSRs, 0x801.A000.0000, 256MB. */
memory_region_init_io(&s->cchip.region, &cchip_ops, s, "cchip0", 256*MB);
memory_region_init_io(&s->cchip.region, NULL, &cchip_ops, s, "cchip0", 256*MB);
memory_region_add_subregion(addr_space, 0x801a0000000ULL,
&s->cchip.region);
/* Dchip CSRs, 0x801.B000.0000, 256MB. */
memory_region_init_io(&s->dchip_region, &dchip_ops, s, "dchip0", 256*MB);
memory_region_init_io(&s->dchip_region, NULL, &dchip_ops, s, "dchip0", 256*MB);
memory_region_add_subregion(addr_space, 0x801b0000000ULL,
&s->dchip_region);
/* Pchip0 PCI memory, 0x800.0000.0000, 4GB. */
memory_region_init(&s->pchip.reg_mem, "pci0-mem", 4*GB);
memory_region_init(&s->pchip.reg_mem, NULL, "pci0-mem", 4*GB);
memory_region_add_subregion(addr_space, 0x80000000000ULL,
&s->pchip.reg_mem);
@ -773,7 +773,7 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
/* ??? Ideally we drop the "system" i/o space on the floor and give the
PCI subsystem the full address space reserved by the chipset.
We can't do that until the MEM and IO paths in memory.c are unified. */
memory_region_init_io(&s->pchip.reg_io, &alpha_pci_bw_io_ops, NULL,
memory_region_init_io(&s->pchip.reg_io, NULL, &alpha_pci_bw_io_ops, NULL,
"pci0-io", 32*MB);
memory_region_add_subregion(addr_space, 0x801fc000000ULL,
&s->pchip.reg_io);
@ -784,13 +784,13 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
phb->bus = b;
/* Pchip0 PCI special/interrupt acknowledge, 0x801.F800.0000, 64MB. */
memory_region_init_io(&s->pchip.reg_iack, &alpha_pci_iack_ops, b,
memory_region_init_io(&s->pchip.reg_iack, NULL, &alpha_pci_iack_ops, b,
"pci0-iack", 64*MB);
memory_region_add_subregion(addr_space, 0x801f8000000ULL,
&s->pchip.reg_iack);
/* Pchip0 PCI configuration, 0x801.FE00.0000, 16MB. */
memory_region_init_io(&s->pchip.reg_conf, &alpha_pci_conf1_ops, b,
memory_region_init_io(&s->pchip.reg_conf, NULL, &alpha_pci_conf1_ops, b,
"pci0-conf", 16*MB);
memory_region_add_subregion(addr_space, 0x801fe000000ULL,
&s->pchip.reg_conf);

8
hw/arm/armv7m.c
View File

@ -124,7 +124,7 @@ static int bitband_init(SysBusDevice *dev)
{
BitBandState *s = FROM_SYSBUS(BitBandState, dev);
memory_region_init_io(&s->iomem, &bitband_ops, &s->base, "bitband",
memory_region_init_io(&s->iomem, NULL, &bitband_ops, &s->base, "bitband",
0x02000000);
sysbus_init_mmio(dev, &s->iomem);
return 0;
@ -203,11 +203,11 @@ qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
#endif
/* Flash programming is done via the SCU, so pretend it is ROM. */
memory_region_init_ram(flash, "armv7m.flash", flash_size);
memory_region_init_ram(flash, NULL, "armv7m.flash", flash_size);
vmstate_register_ram_global(flash);
memory_region_set_readonly(flash, true);
memory_region_add_subregion(address_space_mem, 0, flash);
memory_region_init_ram(sram, "armv7m.sram", sram_size);
memory_region_init_ram(sram, NULL, "armv7m.sram", sram_size);
vmstate_register_ram_global(sram);
memory_region_add_subregion(address_space_mem, 0x20000000, sram);
armv7m_bitband_init();
@ -247,7 +247,7 @@ qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
/* Hack to map an additional page of ram at the top of the address
space. This stops qemu complaining about executing code outside RAM
when returning from an exception. */
memory_region_init_ram(hack, "armv7m.hack", 0x1000);
memory_region_init_ram(hack, NULL, "armv7m.hack", 0x1000);
vmstate_register_ram_global(hack);
memory_region_add_subregion(address_space_mem, 0xfffff000, hack);

12
hw/arm/exynos4210.c
View File

@ -241,20 +241,20 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
/*** Memory ***/
/* Chip-ID and OMR */
memory_region_init_io(&s->chipid_mem, &exynos4210_chipid_and_omr_ops,
memory_region_init_io(&s->chipid_mem, NULL, &exynos4210_chipid_and_omr_ops,
NULL, "exynos4210.chipid", sizeof(chipid_and_omr));
memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR,
&s->chipid_mem);
/* Internal ROM */
memory_region_init_ram(&s->irom_mem, "exynos4210.irom",
memory_region_init_ram(&s->irom_mem, NULL, "exynos4210.irom",
EXYNOS4210_IROM_SIZE);
vmstate_register_ram_global(&s->irom_mem);
memory_region_set_readonly(&s->irom_mem, true);
memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR,
&s->irom_mem);
/* mirror of iROM */
memory_region_init_alias(&s->irom_alias_mem, "exynos4210.irom_alias",
memory_region_init_alias(&s->irom_alias_mem, NULL, "exynos4210.irom_alias",
&s->irom_mem,
0,
EXYNOS4210_IROM_SIZE);
@ -263,7 +263,7 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
&s->irom_alias_mem);
/* Internal RAM */
memory_region_init_ram(&s->iram_mem, "exynos4210.iram",
memory_region_init_ram(&s->iram_mem, NULL, "exynos4210.iram",
EXYNOS4210_IRAM_SIZE);
vmstate_register_ram_global(&s->iram_mem);
memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR,
@ -272,14 +272,14 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
/* DRAM */
mem_size = ram_size;
if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) {
memory_region_init_ram(&s->dram1_mem, "exynos4210.dram1",
memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1",
mem_size - EXYNOS4210_DRAM_MAX_SIZE);
vmstate_register_ram_global(&s->dram1_mem);
memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR,
&s->dram1_mem);
mem_size = EXYNOS4210_DRAM_MAX_SIZE;
}
memory_region_init_ram(&s->dram0_mem, "exynos4210.dram0", mem_size);
memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size);
vmstate_register_ram_global(&s->dram0_mem);
memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR,
&s->dram0_mem);

6
hw/arm/highbank.c
View File

@ -149,7 +149,7 @@ static int highbank_regs_init(SysBusDevice *dev)
HighbankRegsState *s = FROM_SYSBUS(HighbankRegsState, dev);
s->iomem = g_new(MemoryRegion, 1);
memory_region_init_io(s->iomem, &hb_mem_ops, s->regs, "highbank_regs",
memory_region_init_io(s->iomem, NULL, &hb_mem_ops, s->regs, "highbank_regs",
0x1000);
sysbus_init_mmio(dev, s->iomem);
@ -227,12 +227,12 @@ static void highbank_init(QEMUMachineInitArgs *args)
sysmem = get_system_memory();
dram = g_new(MemoryRegion, 1);
memory_region_init_ram(dram, "highbank.dram", ram_size);
memory_region_init_ram(dram, NULL, "highbank.dram", ram_size);
/* SDRAM at address zero. */
memory_region_add_subregion(sysmem, 0, dram);
sysram = g_new(MemoryRegion, 1);
memory_region_init_ram(sysram, "highbank.sysram", 0x8000);
memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000);
memory_region_add_subregion(sysmem, 0xfff88000, sysram);
if (bios_name != NULL) {
sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);

12
hw/arm/integratorcp.c
View File

@ -249,10 +249,10 @@ static int integratorcm_init(SysBusDevice *dev)
}
memcpy(integrator_spd + 73, "QEMU-MEMORY", 11);
s->cm_init = 0x00000112;
memory_region_init_ram(&s->flash, "integrator.flash", 0x100000);
memory_region_init_ram(&s->flash, NULL, "integrator.flash", 0x100000);
vmstate_register_ram_global(&s->flash);
memory_region_init_io(&s->iomem, &integratorcm_ops, s,
memory_region_init_io(&s->iomem, NULL, &integratorcm_ops, s,
"integratorcm", 0x00800000);
sysbus_init_mmio(dev, &s->iomem);
@ -374,7 +374,7 @@ static int icp_pic_init(SysBusDevice *dev)
qdev_init_gpio_in(&dev->qdev, icp_pic_set_irq, 32);
sysbus_init_irq(dev, &s->parent_irq);
sysbus_init_irq(dev, &s->parent_fiq);
memory_region_init_io(&s->iomem, &icp_pic_ops, s, "icp-pic", 0x00800000);
memory_region_init_io(&s->iomem, NULL, &icp_pic_ops, s, "icp-pic", 0x00800000);
sysbus_init_mmio(dev, &s->iomem);
return 0;
}
@ -424,7 +424,7 @@ static void icp_control_init(hwaddr base)
MemoryRegion *io;
io = (MemoryRegion *)g_malloc0(sizeof(MemoryRegion));
memory_region_init_io(io, &icp_control_ops, NULL,
memory_region_init_io(io, NULL, &icp_control_ops, NULL,
"control", 0x00800000);
memory_region_add_subregion(get_system_memory(), base, io);
/* ??? Save/restore. */
@ -463,14 +463,14 @@ static void integratorcp_init(QEMUMachineInitArgs *args)
exit(1);
}
memory_region_init_ram(ram, "integrator.ram", ram_size);
memory_region_init_ram(ram, NULL, "integrator.ram", ram_size);
vmstate_register_ram_global(ram);
/* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */
/* ??? RAM should repeat to fill physical memory space. */
/* SDRAM at address zero*/
memory_region_add_subregion(address_space_mem, 0, ram);
/* And again at address 0x80000000 */
memory_region_init_alias(ram_alias, "ram.alias", ram, 0, ram_size);
memory_region_init_alias(ram_alias, NULL, "ram.alias", ram, 0, ram_size);
memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias);
dev = qdev_create(NULL, "integrator_core");

6
hw/arm/kzm.c
View File

@ -98,14 +98,14 @@ static void kzm_init(QEMUMachineInitArgs *args)
/* On a real system, the first 16k is a `secure boot rom' */
memory_region_init_ram(ram, "kzm.ram", ram_size);
memory_region_init_ram(ram, NULL, "kzm.ram", ram_size);
vmstate_register_ram_global(ram);
memory_region_add_subregion(address_space_mem, KZM_RAMADDRESS, ram);
memory_region_init_alias(ram_alias, "ram.alias", ram, 0, ram_size);
memory_region_init_alias(ram_alias, NULL, "ram.alias", ram, 0, ram_size);
memory_region_add_subregion(address_space_mem, 0x88000000, ram_alias);
memory_region_init_ram(sram, "kzm.sram", 0x4000);
memory_region_init_ram(sram, NULL, "kzm.sram", 0x4000);
memory_region_add_subregion(address_space_mem, 0x1FFFC000, sram);
cpu_pic = arm_pic_init_cpu(cpu);

2
hw/arm/mainstone.c
View File

@ -113,7 +113,7 @@ static void mainstone_common_init(MemoryRegion *address_space_mem,
/* Setup CPU & memory */
mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size, cpu_model);
memory_region_init_ram(rom, "mainstone.rom", MAINSTONE_ROM);
memory_region_init_ram(rom, NULL, "mainstone.rom", MAINSTONE_ROM);
vmstate_register_ram_global(rom);
memory_region_set_readonly(rom, true);
memory_region_add_subregion(address_space_mem, 0, rom);

22
hw/arm/musicpal.c
View File

@ -389,7 +389,7 @@ static int mv88w8618_eth_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->irq);
s->nic = qemu_new_nic(&net_mv88w8618_info, &s->conf,
object_get_typename(OBJECT(dev)), dev->qdev.id, s);
memory_region_init_io(&s->iomem, &mv88w8618_eth_ops, s, "mv88w8618-eth",
memory_region_init_io(&s->iomem, NULL, &mv88w8618_eth_ops, s, "mv88w8618-eth",
MP_ETH_SIZE);
sysbus_init_mmio(dev, &s->iomem);
return 0;
@ -612,7 +612,7 @@ static int musicpal_lcd_init(SysBusDevice *dev)
s->brightness = 7;
memory_region_init_io(&s->iomem, &musicpal_lcd_ops, s,
memory_region_init_io(&s->iomem, NULL, &musicpal_lcd_ops, s,
"musicpal-lcd", MP_LCD_SIZE);
sysbus_init_mmio(dev, &s->iomem);
@ -740,7 +740,7 @@ static int mv88w8618_pic_init(SysBusDevice *dev)
qdev_init_gpio_in(&dev->qdev, mv88w8618_pic_set_irq, 32);
sysbus_init_irq(dev, &s->parent_irq);
memory_region_init_io(&s->iomem, &mv88w8618_pic_ops, s,
memory_region_init_io(&s->iomem, NULL, &mv88w8618_pic_ops, s,
"musicpal-pic", MP_PIC_SIZE);
sysbus_init_mmio(dev, &s->iomem);
return 0;
@ -905,7 +905,7 @@ static int mv88w8618_pit_init(SysBusDevice *dev)
mv88w8618_timer_init(dev, &s->timer[i], 1000000);
}
memory_region_init_io(&s->iomem, &mv88w8618_pit_ops, s,
memory_region_init_io(&s->iomem, NULL, &mv88w8618_pit_ops, s,
"musicpal-pit", MP_PIT_SIZE);
sysbus_init_mmio(dev, &s->iomem);
return 0;
@ -999,7 +999,7 @@ static int mv88w8618_flashcfg_init(SysBusDevice *dev)
mv88w8618_flashcfg_state *s = FROM_SYSBUS(mv88w8618_flashcfg_state, dev);
s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
memory_region_init_io(&s->iomem, &mv88w8618_flashcfg_ops, s,
memory_region_init_io(&s->iomem, NULL, &mv88w8618_flashcfg_ops, s,
"musicpal-flashcfg", MP_FLASHCFG_SIZE);
sysbus_init_mmio(dev, &s->iomem);
return 0;
@ -1074,7 +1074,7 @@ static void musicpal_misc_init(Object *obj)
SysBusDevice *sd = SYS_BUS_DEVICE(obj);
MusicPalMiscState *s = MUSICPAL_MISC(obj);
memory_region_init_io(&s->iomem, &musicpal_misc_ops, NULL,
memory_region_init_io(&s->iomem, NULL, &musicpal_misc_ops, NULL,
"musicpal-misc", MP_MISC_SIZE);
sysbus_init_mmio(sd, &s->iomem);
}
@ -1121,7 +1121,7 @@ static int mv88w8618_wlan_init(SysBusDevice *dev)
{
MemoryRegion *iomem = g_new(MemoryRegion, 1);
memory_region_init_io(iomem, &mv88w8618_wlan_ops, NULL,
memory_region_init_io(iomem, NULL, &mv88w8618_wlan_ops, NULL,
"musicpal-wlan", MP_WLAN_SIZE);
sysbus_init_mmio(dev, iomem);
return 0;
@ -1327,7 +1327,7 @@ static int musicpal_gpio_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->irq);
memory_region_init_io(&s->iomem, &musicpal_gpio_ops, s,
memory_region_init_io(&s->iomem, NULL, &musicpal_gpio_ops, s,
"musicpal-gpio", MP_GPIO_SIZE);
sysbus_init_mmio(dev, &s->iomem);
@ -1484,7 +1484,7 @@ static int musicpal_key_init(SysBusDevice *dev)
{
musicpal_key_state *s = FROM_SYSBUS(musicpal_key_state, dev);
memory_region_init(&s->iomem, "dummy", 0);
memory_region_init(&s->iomem, NULL, "dummy", 0);
sysbus_init_mmio(dev, &s->iomem);
s->kbd_extended = 0;
@ -1564,11 +1564,11 @@ static void musicpal_init(QEMUMachineInitArgs *args)
cpu_pic = arm_pic_init_cpu(cpu);
/* For now we use a fixed - the original - RAM size */
memory_region_init_ram(ram, "musicpal.ram", MP_RAM_DEFAULT_SIZE);
memory_region_init_ram(ram, NULL, "musicpal.ram", MP_RAM_DEFAULT_SIZE);
vmstate_register_ram_global(ram);
memory_region_add_subregion(address_space_mem, 0, ram);
memory_region_init_ram(sram, "musicpal.sram", MP_SRAM_SIZE);
memory_region_init_ram(sram, NULL, "musicpal.sram", MP_SRAM_SIZE);
vmstate_register_ram_global(sram);
memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram);

52
hw/arm/omap1.c
View File

@ -264,7 +264,7 @@ static struct omap_mpu_timer_s *omap_mpu_timer_init(MemoryRegion *system_memory,
omap_mpu_timer_reset(s);
omap_timer_clk_setup(s);
memory_region_init_io(&s->iomem, &omap_mpu_timer_ops, s,
memory_region_init_io(&s->iomem, NULL, &omap_mpu_timer_ops, s,
"omap-mpu-timer", 0x100);
memory_region_add_subregion(system_memory, base, &s->iomem);
@ -392,7 +392,7 @@ static struct omap_watchdog_timer_s *omap_wd_timer_init(MemoryRegion *memory,
omap_wd_timer_reset(s);
omap_timer_clk_setup(&s->timer);
memory_region_init_io(&s->iomem, &omap_wd_timer_ops, s,
memory_region_init_io(&s->iomem, NULL, &omap_wd_timer_ops, s,
"omap-wd-timer", 0x100);
memory_region_add_subregion(memory, base, &s->iomem);
@ -498,7 +498,7 @@ static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory,
omap_os_timer_reset(s);
omap_timer_clk_setup(&s->timer);
memory_region_init_io(&s->iomem, &omap_os_timer_ops, s,
memory_region_init_io(&s->iomem, NULL, &omap_os_timer_ops, s,
"omap-os-timer", 0x800);
memory_region_add_subregion(memory, base, &s->iomem);
@ -731,7 +731,7 @@ static void omap_ulpd_pm_init(MemoryRegion *system_memory,
hwaddr base,
struct omap_mpu_state_s *mpu)
{
memory_region_init_io(&mpu->ulpd_pm_iomem, &omap_ulpd_pm_ops, mpu,
memory_region_init_io(&mpu->ulpd_pm_iomem, NULL, &omap_ulpd_pm_ops, mpu,
"omap-ulpd-pm", 0x800);
memory_region_add_subregion(system_memory, base, &mpu->ulpd_pm_iomem);
omap_ulpd_pm_reset(mpu);
@ -949,7 +949,7 @@ static void omap_pin_cfg_init(MemoryRegion *system_memory,
hwaddr base,
struct omap_mpu_state_s *mpu)
{
memory_region_init_io(&mpu->pin_cfg_iomem, &omap_pin_cfg_ops, mpu,
memory_region_init_io(&mpu->pin_cfg_iomem, NULL, &omap_pin_cfg_ops, mpu,
"omap-pin-cfg", 0x800);
memory_region_add_subregion(system_memory, base, &mpu->pin_cfg_iomem);
omap_pin_cfg_reset(mpu);
@ -1021,16 +1021,16 @@ static const MemoryRegionOps omap_id_ops = {
static void omap_id_init(MemoryRegion *memory, struct omap_mpu_state_s *mpu)
{
memory_region_init_io(&mpu->id_iomem, &omap_id_ops, mpu,
memory_region_init_io(&mpu->id_iomem, NULL, &omap_id_ops, mpu,
"omap-id", 0x100000000ULL);
memory_region_init_alias(&mpu->id_iomem_e18, "omap-id-e18", &mpu->id_iomem,
memory_region_init_alias(&mpu->id_iomem_e18, NULL, "omap-id-e18", &mpu->id_iomem,
0xfffe1800, 0x800);
memory_region_add_subregion(memory, 0xfffe1800, &mpu->id_iomem_e18);
memory_region_init_alias(&mpu->id_iomem_ed4, "omap-id-ed4", &mpu->id_iomem,
memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-ed4", &mpu->id_iomem,
0xfffed400, 0x100);
memory_region_add_subregion(memory, 0xfffed400, &mpu->id_iomem_ed4);
if (!cpu_is_omap15xx(mpu)) {
memory_region_init_alias(&mpu->id_iomem_ed4, "omap-id-e20",
memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-e20",
&mpu->id_iomem, 0xfffe2000, 0x800);
memory_region_add_subregion(memory, 0xfffe2000, &mpu->id_iomem_e20);
}
@ -1115,7 +1115,7 @@ static void omap_mpui_reset(struct omap_mpu_state_s *s)
static void omap_mpui_init(MemoryRegion *memory, hwaddr base,
struct omap_mpu_state_s *mpu)
{
memory_region_init_io(&mpu->mpui_iomem, &omap_mpui_ops, mpu,
memory_region_init_io(&mpu->mpui_iomem, NULL, &omap_mpui_ops, mpu,
"omap-mpui", 0x100);
memory_region_add_subregion(memory, base, &mpu->mpui_iomem);
@ -1227,7 +1227,7 @@ static struct omap_tipb_bridge_s *omap_tipb_bridge_init(
s->abort = abort_irq;
omap_tipb_bridge_reset(s);
memory_region_init_io(&s->iomem, &omap_tipb_bridge_ops, s,
memory_region_init_io(&s->iomem, NULL, &omap_tipb_bridge_ops, s,
"omap-tipb-bridge", 0x100);
memory_region_add_subregion(memory, base, &s->iomem);
@ -1336,7 +1336,7 @@ static void omap_tcmi_reset(struct omap_mpu_state_s *mpu)
static void omap_tcmi_init(MemoryRegion *memory, hwaddr base,
struct omap_mpu_state_s *mpu)
{
memory_region_init_io(&mpu->tcmi_iomem, &omap_tcmi_ops, mpu,
memory_region_init_io(&mpu->tcmi_iomem, NULL, &omap_tcmi_ops, mpu,
"omap-tcmi", 0x100);
memory_region_add_subregion(memory, base, &mpu->tcmi_iomem);
omap_tcmi_reset(mpu);
@ -1418,7 +1418,7 @@ static struct dpll_ctl_s *omap_dpll_init(MemoryRegion *memory,
hwaddr base, omap_clk clk)
{
struct dpll_ctl_s *s = g_malloc0(sizeof(*s));
memory_region_init_io(&s->iomem, &omap_dpll_ops, s, "omap-dpll", 0x100);
memory_region_init_io(&s->iomem, NULL, &omap_dpll_ops, s, "omap-dpll", 0x100);
s->dpll = clk;
omap_dpll_reset(s);
@ -1831,9 +1831,9 @@ static void omap_clkm_reset(struct omap_mpu_state_s *s)
static void omap_clkm_init(MemoryRegion *memory, hwaddr mpu_base,
hwaddr dsp_base, struct omap_mpu_state_s *s)
{
memory_region_init_io(&s->clkm_iomem, &omap_clkm_ops, s,
memory_region_init_io(&s->clkm_iomem, NULL, &omap_clkm_ops, s,
"omap-clkm", 0x100);
memory_region_init_io(&s->clkdsp_iomem, &omap_clkdsp_ops, s,
memory_region_init_io(&s->clkdsp_iomem, NULL, &omap_clkdsp_ops, s,
"omap-clkdsp", 0x1000);
s->clkm.arm_idlect1 = 0x03ff;
@ -2090,7 +2090,7 @@ static struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *memory,
s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16);
omap_mpuio_reset(s);
memory_region_init_io(&s->iomem, &omap_mpuio_ops, s,
memory_region_init_io(&s->iomem, NULL, &omap_mpuio_ops, s,
"omap-mpuio", 0x800);
memory_region_add_subregion(memory, base, &s->iomem);
@ -2281,7 +2281,7 @@ static struct omap_uwire_s *omap_uwire_init(MemoryRegion *system_memory,
s->txdrq = dma;
omap_uwire_reset(s);
memory_region_init_io(&s->iomem, &omap_uwire_ops, s, "omap-uwire", 0x800);
memory_region_init_io(&s->iomem, NULL, &omap_uwire_ops, s, "omap-uwire", 0x800);
memory_region_add_subregion(system_memory, base, &s->iomem);
return s;
@ -2393,7 +2393,7 @@ static struct omap_pwl_s *omap_pwl_init(MemoryRegion *system_memory,
omap_pwl_reset(s);
memory_region_init_io(&s->iomem, &omap_pwl_ops, s,
memory_region_init_io(&s->iomem, NULL, &omap_pwl_ops, s,
"omap-pwl", 0x800);
memory_region_add_subregion(system_memory, base, &s->iomem);
@ -2500,7 +2500,7 @@ static struct omap_pwt_s *omap_pwt_init(MemoryRegion *system_memory,
s->clk = clk;
omap_pwt_reset(s);
memory_region_init_io(&s->iomem, &omap_pwt_ops, s,
memory_region_init_io(&s->iomem, NULL, &omap_pwt_ops, s,
"omap-pwt", 0x800);
memory_region_add_subregion(system_memory, base, &s->iomem);
return s;
@ -2919,7 +2919,7 @@ static struct omap_rtc_s *omap_rtc_init(MemoryRegion *system_memory,
omap_rtc_reset(s);
memory_region_init_io(&s->iomem, &omap_rtc_ops, s,
memory_region_init_io(&s->iomem, NULL, &omap_rtc_ops, s,
"omap-rtc", 0x800);
memory_region_add_subregion(system_memory, base, &s->iomem);
@ -3452,7 +3452,7 @@ static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory,
s->source_timer = qemu_new_timer_ns(vm_clock, omap_mcbsp_source_tick, s);
omap_mcbsp_reset(s);
memory_region_init_io(&s->iomem, &omap_mcbsp_ops, s, "omap-mcbsp", 0x800);
memory_region_init_io(&s->iomem, NULL, &omap_mcbsp_ops, s, "omap-mcbsp", 0x800);
memory_region_add_subregion(system_memory, base, &s->iomem);
return s;
@ -3627,7 +3627,7 @@ static struct omap_lpg_s *omap_lpg_init(MemoryRegion *system_memory,
omap_lpg_reset(s);
memory_region_init_io(&s->iomem, &omap_lpg_ops, s, "omap-lpg", 0x800);
memory_region_init_io(&s->iomem, NULL, &omap_lpg_ops, s, "omap-lpg", 0x800);
memory_region_add_subregion(system_memory, base, &s->iomem);
omap_clk_adduser(clk, qemu_allocate_irqs(omap_lpg_clk_update, s, 1)[0]);
@ -3666,7 +3666,7 @@ static const MemoryRegionOps omap_mpui_io_ops = {
static void omap_setup_mpui_io(MemoryRegion *system_memory,
struct omap_mpu_state_s *mpu)
{
memory_region_init_io(&mpu->mpui_io_iomem, &omap_mpui_io_ops, mpu,
memory_region_init_io(&mpu->mpui_io_iomem, NULL, &omap_mpui_io_ops, mpu,
"omap-mpui-io", 0x7fff);
memory_region_add_subregion(system_memory, OMAP_MPUI_BASE,
&mpu->mpui_io_iomem);
@ -3747,7 +3747,7 @@ static void omap_setup_dsp_mapping(MemoryRegion *system_memory,
for (; map->phys_dsp; map ++) {
io = g_new(MemoryRegion, 1);
memory_region_init_alias(io, map->name,
memory_region_init_alias(io, NULL, map->name,
system_memory, map->phys_mpu, map->size);
memory_region_add_subregion(system_memory, map->phys_dsp, io);
}
@ -3851,10 +3851,10 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
omap_clk_init(s);
/* Memory-mapped stuff */
memory_region_init_ram(&s->emiff_ram, "omap1.dram", s->sdram_size);
memory_region_init_ram(&s->emiff_ram, NULL, "omap1.dram", s->sdram_size);
vmstate_register_ram_global(&s->emiff_ram);
memory_region_add_subregion(system_memory, OMAP_EMIFF_BASE, &s->emiff_ram);
memory_region_init_ram(&s->imif_ram, "omap1.sram", s->sram_size);
memory_region_init_ram(&s->imif_ram, NULL, "omap1.sram", s->sram_size);
vmstate_register_ram_global(&s->imif_ram);
memory_region_add_subregion(system_memory, OMAP_IMIF_BASE, &s->imif_ram);

16
hw/arm/omap2.c
View File

@ -603,7 +603,7 @@ static struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
AUD_register_card("OMAP EAC", &s->codec.card);
memory_region_init_io(&s->iomem, &omap_eac_ops, s, "omap.eac",
memory_region_init_io(&s->iomem, NULL, &omap_eac_ops, s, "omap.eac",
omap_l4_region_size(ta, 0));
omap_l4_attach(ta, 0, &s->iomem);
@ -791,11 +791,11 @@ static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
s->chr = chr ?: qemu_chr_new("null", "null", NULL);
memory_region_init_io(&s->iomem, &omap_sti_ops, s, "omap.sti",
memory_region_init_io(&s->iomem, NULL, &omap_sti_ops, s, "omap.sti",
omap_l4_region_size(ta, 0));
omap_l4_attach(ta, 0, &s->iomem);
memory_region_init_io(&s->iomem_fifo, &omap_sti_fifo_ops, s,
memory_region_init_io(&s->iomem_fifo, NULL, &omap_sti_fifo_ops, s,
"omap.sti.fifo", 0x10000);
memory_region_add_subregion(sysmem, channel_base, &s->iomem_fifo);
@ -1809,9 +1809,9 @@ static struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
s->mpu = mpu;
omap_prcm_coldreset(s);
memory_region_init_io(&s->iomem0, &omap_prcm_ops, s, "omap.pcrm0",
memory_region_init_io(&s->iomem0, NULL, &omap_prcm_ops, s, "omap.pcrm0",
omap_l4_region_size(ta, 0));
memory_region_init_io(&s->iomem1, &omap_prcm_ops, s, "omap.pcrm1",
memory_region_init_io(&s->iomem1, NULL, &omap_prcm_ops, s, "omap.pcrm1",
omap_l4_region_size(ta, 1));
omap_l4_attach(ta, 0, &s->iomem0);
omap_l4_attach(ta, 1, &s->iomem1);
@ -2185,7 +2185,7 @@ static struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
s->mpu = mpu;
omap_sysctl_reset(s);
memory_region_init_io(&s->iomem, &omap_sysctl_ops, s, "omap.sysctl",
memory_region_init_io(&s->iomem, NULL, &omap_sysctl_ops, s, "omap.sysctl",
omap_l4_region_size(ta, 0));
omap_l4_attach(ta, 0, &s->iomem);
@ -2267,10 +2267,10 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
omap_clk_init(s);
/* Memory-mapped stuff */
memory_region_init_ram(&s->sdram, "omap2.dram", s->sdram_size);
memory_region_init_ram(&s->sdram, NULL, "omap2.dram", s->sdram_size);
vmstate_register_ram_global(&s->sdram);
memory_region_add_subregion(sysmem, OMAP2_Q2_BASE, &s->sdram);
memory_region_init_ram(&s->sram, "omap2.sram", s->sram_size);
memory_region_init_ram(&s->sram, NULL, "omap2.sram", s->sram_size);
vmstate_register_ram_global(&s->sram);
memory_region_add_subregion(sysmem, OMAP2_SRAM_BASE, &s->sram);

14
hw/arm/omap_sx1.c
View File

@ -120,23 +120,23 @@ static void sx1_init(QEMUMachineInitArgs *args, const int version)
mpu = omap310_mpu_init(address_space, sx1_binfo.ram_size, args->cpu_model);
/* External Flash (EMIFS) */
memory_region_init_ram(flash, "omap_sx1.flash0-0", flash_size);
memory_region_init_ram(flash, NULL, "omap_sx1.flash0-0", flash_size);
vmstate_register_ram_global(flash);
memory_region_set_readonly(flash, true);
memory_region_add_subregion(address_space, OMAP_CS0_BASE, flash);
memory_region_init_io(&cs[0], &static_ops, &cs0val,
memory_region_init_io(&cs[0], NULL, &static_ops, &cs0val,
"sx1.cs0", OMAP_CS0_SIZE - flash_size);
memory_region_add_subregion(address_space,
OMAP_CS0_BASE + flash_size, &cs[0]);
memory_region_init_io(&cs[2], &static_ops, &cs2val,
memory_region_init_io(&cs[2], NULL, &static_ops, &cs2val,
"sx1.cs2", OMAP_CS2_SIZE);
memory_region_add_subregion(address_space,
OMAP_CS2_BASE, &cs[2]);
memory_region_init_io(&cs[3], &static_ops, &cs3val,
memory_region_init_io(&cs[3], NULL, &static_ops, &cs3val,
"sx1.cs3", OMAP_CS3_SIZE);
memory_region_add_subregion(address_space,
OMAP_CS2_BASE, &cs[3]);
@ -162,12 +162,12 @@ static void sx1_init(QEMUMachineInitArgs *args, const int version)
if ((version == 1) &&
(dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {
memory_region_init_ram(flash_1, "omap_sx1.flash1-0", flash1_size);
memory_region_init_ram(flash_1, NULL, "omap_sx1.flash1-0", flash1_size);
vmstate_register_ram_global(flash_1);
memory_region_set_readonly(flash_1, true);
memory_region_add_subregion(address_space, OMAP_CS1_BASE, flash_1);
memory_region_init_io(&cs[1], &static_ops, &cs1val,
memory_region_init_io(&cs[1], NULL, &static_ops, &cs1val,
"sx1.cs1", OMAP_CS1_SIZE - flash1_size);
memory_region_add_subregion(address_space,
OMAP_CS1_BASE + flash1_size, &cs[1]);
@ -182,7 +182,7 @@ static void sx1_init(QEMUMachineInitArgs *args, const int version)
}
fl_idx++;
} else {
memory_region_init_io(&cs[1], &static_ops, &cs1val,
memory_region_init_io(&cs[1], NULL, &static_ops, &cs1val,
"sx1.cs1", OMAP_CS1_SIZE);
memory_region_add_subregion(address_space,
OMAP_CS1_BASE, &cs[1]);

10
hw/arm/palm.c
View File

@ -211,22 +211,22 @@ static void palmte_init(QEMUMachineInitArgs *args)
mpu = omap310_mpu_init(address_space_mem, sdram_size, cpu_model);
/* External Flash (EMIFS) */
memory_region_init_ram(flash, "palmte.flash", flash_size);
memory_region_init_ram(flash, NULL, "palmte.flash", flash_size);
vmstate_register_ram_global(flash);
memory_region_set_readonly(flash, true);
memory_region_add_subregion(address_space_mem, OMAP_CS0_BASE, flash);
memory_region_init_io(&cs[0], &static_ops, &cs0val, "palmte-cs0",
memory_region_init_io(&cs[0], NULL, &static_ops, &cs0val, "palmte-cs0",
OMAP_CS0_SIZE - flash_size);
memory_region_add_subregion(address_space_mem, OMAP_CS0_BASE + flash_size,
&cs[0]);
memory_region_init_io(&cs[1], &static_ops, &cs1val, "palmte-cs1",
memory_region_init_io(&cs[1], NULL, &static_ops, &cs1val, "palmte-cs1",
OMAP_CS1_SIZE);
memory_region_add_subregion(address_space_mem, OMAP_CS1_BASE, &cs[1]);
memory_region_init_io(&cs[2], &static_ops, &cs2val, "palmte-cs2",
memory_region_init_io(&cs[2], NULL, &static_ops, &cs2val, "palmte-cs2",
OMAP_CS2_SIZE);
memory_region_add_subregion(address_space_mem, OMAP_CS2_BASE, &cs[2]);
memory_region_init_io(&cs[3], &static_ops, &cs3val, "palmte-cs3",
memory_region_init_io(&cs[3], NULL, &static_ops, &cs3val, "palmte-cs3",
OMAP_CS3_SIZE);
memory_region_add_subregion(address_space_mem, OMAP_CS3_BASE, &cs[3]);

30
hw/arm/pxa2xx.c
View File

@ -764,7 +764,7 @@ static int pxa2xx_ssp_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->irq);
memory_region_init_io(&s->iomem, &pxa2xx_ssp_ops, s, "pxa2xx-ssp", 0x1000);
memory_region_init_io(&s->iomem, NULL, &pxa2xx_ssp_ops, s, "pxa2xx-ssp", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
register_savevm(&dev->qdev, "pxa2xx_ssp", -1, 0,
pxa2xx_ssp_save, pxa2xx_ssp_load, s);
@ -1131,7 +1131,7 @@ static int pxa2xx_rtc_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->rtc_irq);
memory_region_init_io(&s->iomem, &pxa2xx_rtc_ops, s, "pxa2xx-rtc", 0x10000);
memory_region_init_io(&s->iomem, NULL, &pxa2xx_rtc_ops, s, "pxa2xx-rtc", 0x10000);
sysbus_init_mmio(dev, &s->iomem);
return 0;
@ -1481,7 +1481,7 @@ static int pxa2xx_i2c_initfn(SysBusDevice *dev)
s->bus = i2c_init_bus(&dev->qdev, "i2c");
memory_region_init_io(&s->iomem, &pxa2xx_i2c_ops, s,
memory_region_init_io(&s->iomem, NULL, &pxa2xx_i2c_ops, s,
"pxa2xx-i2x", s->region_size);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
@ -1720,7 +1720,7 @@ static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem,
pxa2xx_i2s_reset(s);
memory_region_init_io(&s->iomem, &pxa2xx_i2s_ops, s,
memory_region_init_io(&s->iomem, NULL, &pxa2xx_i2s_ops, s,
"pxa2xx-i2s", 0x100000);
memory_region_add_subregion(sysmem, base, &s->iomem);
@ -1978,7 +1978,7 @@ static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem,
pxa2xx_fir_reset(s);
memory_region_init_io(&s->iomem, &pxa2xx_fir_ops, s, "pxa2xx-fir", 0x1000);
memory_region_init_io(&s->iomem, NULL, &pxa2xx_fir_ops, s, "pxa2xx-fir", 0x1000);
memory_region_add_subregion(sysmem, base, &s->iomem);
if (chr) {
@ -2027,10 +2027,10 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space,
s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
/* SDRAM & Internal Memory Storage */
memory_region_init_ram(&s->sdram, "pxa270.sdram", sdram_size);
memory_region_init_ram(&s->sdram, NULL, "pxa270.sdram", sdram_size);
vmstate_register_ram_global(&s->sdram);
memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram);
memory_region_init_ram(&s->internal, "pxa270.internal", 0x40000);
memory_region_init_ram(&s->internal, NULL, "pxa270.internal", 0x40000);
vmstate_register_ram_global(&s->internal);
memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE,
&s->internal);
@ -2083,7 +2083,7 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space,
s->cm_base = 0x41300000;
s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
s->clkcfg = 0x00000009; /* Turbo mode active */
memory_region_init_io(&s->cm_iomem, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
@ -2093,12 +2093,12 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space,
s->mm_regs[MDMRS >> 2] = 0x00020002;
s->mm_regs[MDREFR >> 2] = 0x03ca4000;
s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
memory_region_init_io(&s->mm_iomem, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000);
memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000);
memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem);
vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s);
s->pm_base = 0x40f00000;
memory_region_init_io(&s->pm_iomem, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100);
memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100);
memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem);
vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);
@ -2158,10 +2158,10 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
/* SDRAM & Internal Memory Storage */
memory_region_init_ram(&s->sdram, "pxa255.sdram", sdram_size);
memory_region_init_ram(&s->sdram, NULL, "pxa255.sdram", sdram_size);
vmstate_register_ram_global(&s->sdram);
memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram);
memory_region_init_ram(&s->internal, "pxa255.internal",
memory_region_init_ram(&s->internal, NULL, "pxa255.internal",
PXA2XX_INTERNAL_SIZE);
vmstate_register_ram_global(&s->internal);
memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE,
@ -2214,7 +2214,7 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
s->cm_base = 0x41300000;
s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
s->clkcfg = 0x00000009; /* Turbo mode active */
memory_region_init_io(&s->cm_iomem, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
@ -2224,12 +2224,12 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
s->mm_regs[MDMRS >> 2] = 0x00020002;
s->mm_regs[MDREFR >> 2] = 0x03ca4000;
s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
memory_region_init_io(&s->mm_iomem, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000);
memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000);
memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem);
vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s);
s->pm_base = 0x40f00000;
memory_region_init_io(&s->pm_iomem, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100);
memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100);
memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem);
vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);

2
hw/arm/pxa2xx_gpio.c
View File

@ -283,7 +283,7 @@ static int pxa2xx_gpio_initfn(SysBusDevice *dev)
qdev_init_gpio_in(&dev->qdev, pxa2xx_gpio_set, s->lines);
qdev_init_gpio_out(&dev->qdev, s->handler, s->lines);
memory_region_init_io(&s->iomem, &pxa_gpio_ops, s, "pxa2xx-gpio", 0x1000);
memory_region_init_io(&s->iomem, NULL, &pxa_gpio_ops, s, "pxa2xx-gpio", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq0);
sysbus_init_irq(dev, &s->irq1);

2
hw/arm/pxa2xx_pic.c
View File

@ -278,7 +278,7 @@ DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu)
qdev_init_gpio_in(dev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS);
/* Enable IC memory-mapped registers access. */
memory_region_init_io(&s->iomem, &pxa2xx_pic_ops, s,
memory_region_init_io(&s->iomem, NULL, &pxa2xx_pic_ops, s,
"pxa2xx-pic", 0x00100000);
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);

8
hw/arm/realview.c
View File

@ -114,18 +114,18 @@ static void realview_init(QEMUMachineInitArgs *args,
/* Core tile RAM. */
low_ram_size = ram_size - 0x20000000;
ram_size = 0x20000000;
memory_region_init_ram(ram_lo, "realview.lowmem", low_ram_size);
memory_region_init_ram(ram_lo, NULL, "realview.lowmem", low_ram_size);
vmstate_register_ram_global(ram_lo);
memory_region_add_subregion(sysmem, 0x20000000, ram_lo);
}
memory_region_init_ram(ram_hi, "realview.highmem", ram_size);
memory_region_init_ram(ram_hi, NULL, "realview.highmem", ram_size);
vmstate_register_ram_global(ram_hi);
low_ram_size = ram_size;
if (low_ram_size > 0x10000000)
low_ram_size = 0x10000000;
/* SDRAM at address zero. */
memory_region_init_alias(ram_alias, "realview.alias",
memory_region_init_alias(ram_alias, NULL, "realview.alias",
ram_hi, 0, low_ram_size);
memory_region_add_subregion(sysmem, 0, ram_alias);
if (is_pb) {
@ -318,7 +318,7 @@ static void realview_init(QEMUMachineInitArgs *args,
startup code. I guess this works on real hardware because the
BootROM happens to be in ROM/flash or in memory that isn't clobbered
until after Linux boots the secondary CPUs. */
memory_region_init_ram(ram_hack, "realview.hack", 0x1000);
memory_region_init_ram(ram_hack, NULL, "realview.hack", 0x1000);
vmstate_register_ram_global(ram_hack);
memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack);

4
hw/arm/spitz.c
View File

@ -169,7 +169,7 @@ static int sl_nand_init(SysBusDevice *dev) {
nand = drive_get(IF_MTD, 0, 0);
s->nand = nand_init(nand ? nand->bdrv : NULL, s->manf_id, s->chip_id);
memory_region_init_io(&s->iomem, &sl_ops, s, "sl", 0x40);
memory_region_init_io(&s->iomem, NULL, &sl_ops, s, "sl", 0x40);
sysbus_init_mmio(dev, &s->iomem);
return 0;
@ -896,7 +896,7 @@ static void spitz_common_init(QEMUMachineInitArgs *args,
sl_flash_register(mpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
memory_region_init_ram(rom, "spitz.rom", SPITZ_ROM);
memory_region_init_ram(rom, NULL, "spitz.rom", SPITZ_ROM);
vmstate_register_ram_global(rom);
memory_region_set_readonly(rom, true);
memory_region_add_subregion(address_space_mem, 0, rom);

8
hw/arm/stellaris.c
View File

@ -307,7 +307,7 @@ static int stellaris_gptm_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->irq);
qdev_init_gpio_out(&dev->qdev, &s->trigger, 1);
memory_region_init_io(&s->iomem, &gptm_ops, s,
memory_region_init_io(&s->iomem, NULL, &gptm_ops, s,
"gptm", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
@ -669,7 +669,7 @@ static int stellaris_sys_init(uint32_t base, qemu_irq irq,
s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16);
s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16);
memory_region_init_io(&s->iomem, &ssys_ops, s, "ssys", 0x00001000);
memory_region_init_io(&s->iomem, NULL, &ssys_ops, s, "ssys", 0x00001000);
memory_region_add_subregion(get_system_memory(), base, &s->iomem);
ssys_reset(s);
vmstate_register(NULL, -1, &vmstate_stellaris_sys, s);
@ -862,7 +862,7 @@ static int stellaris_i2c_init(SysBusDevice * dev)
bus = i2c_init_bus(&dev->qdev, "i2c");
s->bus = bus;
memory_region_init_io(&s->iomem, &stellaris_i2c_ops, s,
memory_region_init_io(&s->iomem, NULL, &stellaris_i2c_ops, s,
"i2c", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
/* ??? For now we only implement the master interface. */
@ -1145,7 +1145,7 @@ static int stellaris_adc_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->irq[n]);
}
memory_region_init_io(&s->iomem, &stellaris_adc_ops, s,
memory_region_init_io(&s->iomem, NULL, &stellaris_adc_ops, s,
"adc", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
stellaris_adc_reset(s);

14
hw/arm/strongarm.c
View File

@ -173,7 +173,7 @@ static int strongarm_pic_initfn(SysBusDevice *dev)
StrongARMPICState *s = FROM_SYSBUS(StrongARMPICState, dev);
qdev_init_gpio_in(&dev->qdev, strongarm_pic_set_irq, SA_PIC_SRCS);
memory_region_init_io(&s->iomem, &strongarm_pic_ops, s, "pic", 0x1000);
memory_region_init_io(&s->iomem, NULL, &strongarm_pic_ops, s, "pic", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
sysbus_init_irq(dev, &s->fiq);
@ -383,7 +383,7 @@ static int strongarm_rtc_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->rtc_irq);
sysbus_init_irq(dev, &s->rtc_hz_irq);
memory_region_init_io(&s->iomem, &strongarm_rtc_ops, s, "rtc", 0x10000);
memory_region_init_io(&s->iomem, NULL, &strongarm_rtc_ops, s, "rtc", 0x10000);
sysbus_init_mmio(dev, &s->iomem);
return 0;
@ -637,7 +637,7 @@ static int strongarm_gpio_initfn(SysBusDevice *dev)
qdev_init_gpio_in(&dev->qdev, strongarm_gpio_set, 28);
qdev_init_gpio_out(&dev->qdev, s->handler, 28);
memory_region_init_io(&s->iomem, &strongarm_gpio_ops, s, "gpio", 0x1000);
memory_region_init_io(&s->iomem, NULL, &strongarm_gpio_ops, s, "gpio", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
for (i = 0; i < 11; i++) {
@ -808,7 +808,7 @@ static int strongarm_ppc_init(SysBusDevice *dev)
qdev_init_gpio_in(&dev->qdev, strongarm_ppc_set, 22);
qdev_init_gpio_out(&dev->qdev, s->handler, 22);
memory_region_init_io(&s->iomem, &strongarm_ppc_ops, s, "ppc", 0x1000);
memory_region_init_io(&s->iomem, NULL, &strongarm_ppc_ops, s, "ppc", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
@ -1204,7 +1204,7 @@ static int strongarm_uart_init(SysBusDevice *dev)
{
StrongARMUARTState *s = FROM_SYSBUS(StrongARMUARTState, dev);
memory_region_init_io(&s->iomem, &strongarm_uart_ops, s, "uart", 0x10000);
memory_region_init_io(&s->iomem, NULL, &strongarm_uart_ops, s, "uart", 0x10000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
@ -1496,7 +1496,7 @@ static int strongarm_ssp_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->irq);
memory_region_init_io(&s->iomem, &strongarm_ssp_ops, s, "ssp", 0x1000);
memory_region_init_io(&s->iomem, NULL, &strongarm_ssp_ops, s, "ssp", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
s->bus = ssi_create_bus(&dev->qdev, "ssi");
@ -1571,7 +1571,7 @@ StrongARMState *sa1110_init(MemoryRegion *sysmem,
exit(1);
}
memory_region_init_ram(&s->sdram, "strongarm.sdram", sdram_size);
memory_region_init_ram(&s->sdram, NULL, "strongarm.sdram", sdram_size);
vmstate_register_ram_global(&s->sdram);
memory_region_add_subregion(sysmem, SA_SDCS0, &s->sdram);

2
hw/arm/tosa.c
View File

@ -222,7 +222,7 @@ static void tosa_init(QEMUMachineInitArgs *args)
mpu = pxa255_init(address_space_mem, tosa_binfo.ram_size);
memory_region_init_ram(rom, "tosa.rom", TOSA_ROM);
memory_region_init_ram(rom, NULL, "tosa.rom", TOSA_ROM);
vmstate_register_ram_global(rom);
memory_region_set_readonly(rom, true);
memory_region_add_subregion(address_space_mem, 0, rom);

4
hw/arm/versatilepb.c
View File

@ -154,7 +154,7 @@ static int vpb_sic_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->parent[i]);
}
s->irq = 31;
memory_region_init_io(&s->iomem, &vpb_sic_ops, s, "vpb-sic", 0x1000);
memory_region_init_io(&s->iomem, NULL, &vpb_sic_ops, s, "vpb-sic", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
return 0;
}
@ -193,7 +193,7 @@ static void versatile_init(QEMUMachineInitArgs *args, int board_id)
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
memory_region_init_ram(ram, "versatile.ram", args->ram_size);
memory_region_init_ram(ram, NULL, "versatile.ram", args->ram_size);
vmstate_register_ram_global(ram);
/* ??? RAM should repeat to fill physical memory space. */
/* SDRAM at address zero. */

12
hw/arm/vexpress.c
View File

@ -196,7 +196,7 @@ static void a9_daughterboard_init(const VEDBoardInfo *daughterboard,
exit(1);
}
memory_region_init_ram(ram, "vexpress.highmem", ram_size);
memory_region_init_ram(ram, NULL, "vexpress.highmem", ram_size);
vmstate_register_ram_global(ram);
low_ram_size = ram_size;
if (low_ram_size > 0x4000000) {
@ -206,7 +206,7 @@ static void a9_daughterboard_init(const VEDBoardInfo *daughterboard,
* address space should in theory be remappable to various
* things including ROM or RAM; we always map the RAM there.
*/
memory_region_init_alias(lowram, "vexpress.lowmem", ram, 0, low_ram_size);
memory_region_init_alias(lowram, NULL, "vexpress.lowmem", ram, 0, low_ram_size);
memory_region_add_subregion(sysmem, 0x0, lowram);
memory_region_add_subregion(sysmem, 0x60000000, ram);
@ -323,7 +323,7 @@ static void a15_daughterboard_init(const VEDBoardInfo *daughterboard,
}
}
memory_region_init_ram(ram, "vexpress.highmem", ram_size);
memory_region_init_ram(ram, NULL, "vexpress.highmem", ram_size);
vmstate_register_ram_global(ram);
/* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */
memory_region_add_subregion(sysmem, 0x80000000, ram);
@ -357,7 +357,7 @@ static void a15_daughterboard_init(const VEDBoardInfo *daughterboard,
/* 0x2b060000: SP805 watchdog: not modelled */
/* 0x2b0a0000: PL341 dynamic memory controller: not modelled */
/* 0x2e000000: system SRAM */
memory_region_init_ram(sram, "vexpress.a15sram", 0x10000);
memory_region_init_ram(sram, NULL, "vexpress.a15sram", 0x10000);
vmstate_register_ram_global(sram);
memory_region_add_subregion(sysmem, 0x2e000000, sram);
@ -491,12 +491,12 @@ static void vexpress_common_init(const VEDBoardInfo *daughterboard,
}
sram_size = 0x2000000;
memory_region_init_ram(sram, "vexpress.sram", sram_size);
memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size);
vmstate_register_ram_global(sram);
memory_region_add_subregion(sysmem, map[VE_SRAM], sram);
vram_size = 0x800000;
memory_region_init_ram(vram, "vexpress.vram", vram_size);
memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size);
vmstate_register_ram_global(vram);
memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram);

4
hw/arm/xilinx_zynq.c
View File

@ -132,12 +132,12 @@ static void zynq_init(QEMUMachineInitArgs *args)
}
/* DDR remapped to address zero. */
memory_region_init_ram(ext_ram, "zynq.ext_ram", ram_size);
memory_region_init_ram(ext_ram, NULL, "zynq.ext_ram", ram_size);
vmstate_register_ram_global(ext_ram);
memory_region_add_subregion(address_space_mem, 0, ext_ram);
/* 256K of on-chip memory */
memory_region_init_ram(ocm_ram, "zynq.ocm_ram", 256 << 10);
memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 << 10);
vmstate_register_ram_global(ocm_ram);
memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram);

4
hw/audio/ac97.c
View File

@ -1378,8 +1378,8 @@ static int ac97_initfn (PCIDevice *dev)
c[PCI_INTERRUPT_LINE] = 0x00; /* intr_ln interrupt line rw */
c[PCI_INTERRUPT_PIN] = 0x01; /* intr_pn interrupt pin ro */
memory_region_init_io (&s->io_nam, &ac97_io_nam_ops, s, "ac97-nam", 1024);
memory_region_init_io (&s->io_nabm, &ac97_io_nabm_ops, s, "ac97-nabm", 256);
memory_region_init_io (&s->io_nam, NULL, &ac97_io_nam_ops, s, "ac97-nam", 1024);
memory_region_init_io (&s->io_nabm, NULL, &ac97_io_nabm_ops, s, "ac97-nabm", 256);
pci_register_bar (&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nam);
pci_register_bar (&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nabm);
qemu_register_reset (ac97_on_reset, s);

2
hw/audio/cs4231.c
View File

@ -144,7 +144,7 @@ static int cs4231_init1(SysBusDevice *dev)
{
CSState *s = FROM_SYSBUS(CSState, dev);
memory_region_init_io(&s->iomem, &cs_mem_ops, s, "cs4321", CS_SIZE);
memory_region_init_io(&s->iomem, NULL, &cs_mem_ops, s, "cs4321", CS_SIZE);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);

2
hw/audio/cs4231a.c
View File

@ -648,7 +648,7 @@ static void cs4231a_initfn (Object *obj)
{
CSState *s = CS4231A (obj);
memory_region_init_io (&s->ioports, &cs_ioport_ops, s, "cs4231a", 4);
memory_region_init_io (&s->ioports, NULL, &cs_ioport_ops, s, "cs4231a", 4);
}
static void cs4231a_realizefn (DeviceState *dev, Error **errp)

2
hw/audio/es1370.c
View File

@ -1035,7 +1035,7 @@ static int es1370_initfn (PCIDevice *dev)
c[PCI_MIN_GNT] = 0x0c;
c[PCI_MAX_LAT] = 0x80;
memory_region_init_io (&s->io, &es1370_io_ops, s, "es1370", 256);
memory_region_init_io (&s->io, NULL, &es1370_io_ops, s, "es1370", 256);
pci_register_bar (&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
qemu_register_reset (es1370_on_reset, s);

2
hw/audio/intel-hda.c
View File

@ -1135,7 +1135,7 @@ static int intel_hda_init(PCIDevice *pci)
/* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
conf[0x40] = 0x01;
memory_region_init_io(&d->mmio, &intel_hda_mmio_ops, d,
memory_region_init_io(&d->mmio, NULL, &intel_hda_mmio_ops, d,
"intel-hda", 0x4000);
pci_register_bar(&d->pci, 0, 0, &d->mmio);
if (d->msi) {

2
hw/audio/marvell_88w8618.c
View File

@ -244,7 +244,7 @@ static int mv88w8618_audio_init(SysBusDevice *dev)
wm8750_data_req_set(s->wm, mv88w8618_audio_callback, s);
memory_region_init_io(&s->iomem, &mv88w8618_audio_ops, s,
memory_region_init_io(&s->iomem, NULL, &mv88w8618_audio_ops, s,
"audio", MP_AUDIO_SIZE);
sysbus_init_mmio(dev, &s->iomem);

2
hw/audio/milkymist-ac97.c
View File

@ -300,7 +300,7 @@ static int milkymist_ac97_init(SysBusDevice *dev)
s->voice_out = AUD_open_out(&s->card, s->voice_out,
"mm_ac97.out", s, ac97_out_cb, &as);
memory_region_init_io(&s->regs_region, &ac97_mmio_ops, s,
memory_region_init_io(&s->regs_region, NULL, &ac97_mmio_ops, s,
"milkymist-ac97", R_MAX * 4);
sysbus_init_mmio(dev, &s->regs_region);

2
hw/audio/pcspk.c
View File

@ -167,7 +167,7 @@ static void pcspk_initfn(Object *obj)
{
PCSpkState *s = PC_SPEAKER(obj);
memory_region_init_io(&s->ioport, &pcspk_io_ops, s, "elcr", 1);
memory_region_init_io(&s->ioport, NULL, &pcspk_io_ops, s, "elcr", 1);
}
static void pcspk_realizefn(DeviceState *dev, Error **errp)

2
hw/audio/pl041.c
View File

@ -543,7 +543,7 @@ static int pl041_init(SysBusDevice *dev)
}
/* Connect the device to the sysbus */
memory_region_init_io(&s->iomem, &pl041_ops, s, "pl041", 0x1000);
memory_region_init_io(&s->iomem, NULL, &pl041_ops, s, "pl041", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);

4
hw/block/fdc.c
View File

@ -2149,7 +2149,7 @@ static int sysbus_fdc_init1(SysBusDevice *dev)
FDCtrl *fdctrl = &sys->state;
int ret;
memory_region_init_io(&fdctrl->iomem, &fdctrl_mem_ops, fdctrl, "fdc", 0x08);
memory_region_init_io(&fdctrl->iomem, NULL, &fdctrl_mem_ops, fdctrl, "fdc", 0x08);
sysbus_init_mmio(dev, &fdctrl->iomem);
sysbus_init_irq(dev, &fdctrl->irq);
qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
@ -2165,7 +2165,7 @@ static int sun4m_fdc_init1(SysBusDevice *dev)
{
FDCtrl *fdctrl = &(FROM_SYSBUS(FDCtrlSysBus, dev)->state);
memory_region_init_io(&fdctrl->iomem, &fdctrl_mem_strict_ops, fdctrl,
memory_region_init_io(&fdctrl->iomem, NULL, &fdctrl_mem_strict_ops, fdctrl,
"fdctrl", 0x08);
sysbus_init_mmio(dev, &fdctrl->iomem);
sysbus_init_irq(dev, &fdctrl->irq);

2
hw/block/nvme.c
View File

@ -777,7 +777,7 @@ static int nvme_init(PCIDevice *pci_dev)
n->sq = g_malloc0(sizeof(*n->sq)*n->num_queues);
n->cq = g_malloc0(sizeof(*n->cq)*n->num_queues);
memory_region_init_io(&n->iomem, &nvme_mmio_ops, n, "nvme", n->reg_size);
memory_region_init_io(&n->iomem, NULL, &nvme_mmio_ops, n, "nvme", n->reg_size);
pci_register_bar(&n->parent_obj, 0,
PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64,
&n->iomem);

8
hw/block/onenand.c
View File

@ -113,9 +113,9 @@ static void onenand_mem_setup(OneNANDState *s)
/* XXX: We should use IO_MEM_ROMD but we broke it earlier...
* Both 0x0000 ... 0x01ff and 0x8000 ... 0x800f can be used to
* write boot commands. Also take note of the BWPS bit. */
memory_region_init(&s->container, "onenand", 0x10000 << s->shift);
memory_region_init(&s->container, NULL, "onenand", 0x10000 << s->shift);
memory_region_add_subregion(&s->container, 0, &s->iomem);
memory_region_init_alias(&s->mapped_ram, "onenand-mapped-ram",
memory_region_init_alias(&s->mapped_ram, NULL, "onenand-mapped-ram",
&s->ram, 0x0200 << s->shift,
0xbe00 << s->shift);
memory_region_add_subregion_overlap(&s->container,
@ -768,7 +768,7 @@ static int onenand_initfn(SysBusDevice *dev)
s->blockwp = g_malloc(s->blocks);
s->density_mask = (s->id.dev & 0x08)
? (1 << (6 + ((s->id.dev >> 4) & 7))) : 0;
memory_region_init_io(&s->iomem, &onenand_ops, s, "onenand",
memory_region_init_io(&s->iomem, NULL, &onenand_ops, s, "onenand",
0x10000 << s->shift);
if (!s->bdrv) {
s->image = memset(g_malloc(size + (size >> 5)),
@ -782,7 +782,7 @@ static int onenand_initfn(SysBusDevice *dev)
}
s->otp = memset(g_malloc((64 + 2) << PAGE_SHIFT),
0xff, (64 + 2) << PAGE_SHIFT);
memory_region_init_ram(&s->ram, "onenand.ram", 0xc000 << s->shift);
memory_region_init_ram(&s->ram, NULL, "onenand.ram", 0xc000 << s->shift);
vmstate_register_ram_global(&s->ram);
ram = memory_region_get_ram_ptr(&s->ram);
s->boot[0] = ram + (0x0000 << s->shift);

6
hw/block/pc_sysfw.c
View File

@ -59,7 +59,7 @@ static void pc_isa_bios_init(MemoryRegion *rom_memory,
isa_bios_size = 128 * 1024;
}
isa_bios = g_malloc(sizeof(*isa_bios));
memory_region_init_ram(isa_bios, "isa-bios", isa_bios_size);
memory_region_init_ram(isa_bios, NULL, "isa-bios", isa_bios_size);
vmstate_register_ram_global(isa_bios);
memory_region_add_subregion_overlap(rom_memory,
0x100000 - isa_bios_size,
@ -162,7 +162,7 @@ static void old_pc_system_rom_init(MemoryRegion *rom_memory, bool isapc_ram_fw)
goto bios_error;
}
bios = g_malloc(sizeof(*bios));
memory_region_init_ram(bios, "pc.bios", bios_size);
memory_region_init_ram(bios, NULL, "pc.bios", bios_size);
vmstate_register_ram_global(bios);
if (!isapc_ram_fw) {
memory_region_set_readonly(bios, true);
@ -183,7 +183,7 @@ static void old_pc_system_rom_init(MemoryRegion *rom_memory, bool isapc_ram_fw)
isa_bios_size = 128 * 1024;
}
isa_bios = g_malloc(sizeof(*isa_bios));
memory_region_init_alias(isa_bios, "isa-bios", bios,
memory_region_init_alias(isa_bios, NULL, "isa-bios", bios,
bios_size - isa_bios_size, isa_bios_size);
memory_region_add_subregion_overlap(rom_memory,
0x100000 - isa_bios_size,

3
hw/block/pflash_cfi01.c
View File

@ -579,7 +579,8 @@ static int pflash_cfi01_init(SysBusDevice *dev)
#endif
memory_region_init_rom_device(
&pfl->mem, pfl->be ? &pflash_cfi01_ops_be : &pflash_cfi01_ops_le, pfl,
&pfl->mem, NULL,
pfl->be ? &pflash_cfi01_ops_be : &pflash_cfi01_ops_le, pfl,
pfl->name, total_len);
vmstate_register_ram(&pfl->mem, DEVICE(pfl));
pfl->storage = memory_region_get_ram_ptr(&pfl->mem);

6
hw/block/pflash_cfi02.c
View File

@ -100,10 +100,10 @@ static void pflash_setup_mappings(pflash_t *pfl)
unsigned i;
hwaddr size = memory_region_size(&pfl->orig_mem);
memory_region_init(&pfl->mem, "pflash", pfl->mappings * size);
memory_region_init(&pfl->mem, NULL, "pflash", pfl->mappings * size);
pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings);
for (i = 0; i < pfl->mappings; ++i) {
memory_region_init_alias(&pfl->mem_mappings[i], "pflash-alias",
memory_region_init_alias(&pfl->mem_mappings[i], NULL, "pflash-alias",
&pfl->orig_mem, 0, size);
memory_region_add_subregion(&pfl->mem, i * size, &pfl->mem_mappings[i]);
}
@ -600,7 +600,7 @@ static int pflash_cfi02_init(SysBusDevice *dev)
return NULL;
#endif
memory_region_init_rom_device(&pfl->orig_mem, pfl->be ?
memory_region_init_rom_device(&pfl->orig_mem, NULL, pfl->be ?
&pflash_cfi02_ops_be : &pflash_cfi02_ops_le,
pfl, pfl->name, chip_len);
vmstate_register_ram(&pfl->orig_mem, DEVICE(pfl));

2
hw/char/cadence_uart.c
View File

@ -442,7 +442,7 @@ static int cadence_uart_init(SysBusDevice *dev)
{
UartState *s = FROM_SYSBUS(UartState, dev);
memory_region_init_io(&s->iomem, &uart_ops, s, "uart", 0x1000);
memory_region_init_io(&s->iomem, NULL, &uart_ops, s, "uart", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);

2
hw/char/debugcon.c
View File

@ -103,7 +103,7 @@ static void debugcon_isa_realizefn(DeviceState *dev, Error **errp)
error_propagate(errp, err);
return;
}
memory_region_init_io(&s->io, &debugcon_ops, s,
memory_region_init_io(&s->io, NULL, &debugcon_ops, s,
TYPE_ISA_DEBUGCON_DEVICE, 1);
memory_region_add_subregion(isa_address_space_io(d),
isa->iobase, &s->io);

2
hw/char/escc.c
View File

@ -886,7 +886,7 @@ static int escc_init1(SysBusDevice *dev)
s->chn[0].otherchn = &s->chn[1];
s->chn[1].otherchn = &s->chn[0];
memory_region_init_io(&s->mmio, &escc_mem_ops, s, "escc",
memory_region_init_io(&s->mmio, NULL, &escc_mem_ops, s, "escc",
ESCC_SIZE << s->it_shift);
sysbus_init_mmio(dev, &s->mmio);

2
hw/char/etraxfs_ser.c
View File

@ -211,7 +211,7 @@ static int etraxfs_ser_init(SysBusDevice *dev)
struct etrax_serial *s = FROM_SYSBUS(typeof (*s), dev);
sysbus_init_irq(dev, &s->irq);
memory_region_init_io(&s->mmio, &ser_ops, s, "etraxfs-serial", R_MAX * 4);
memory_region_init_io(&s->mmio, NULL, &ser_ops, s, "etraxfs-serial", R_MAX * 4);
sysbus_init_mmio(dev, &s->mmio);
s->chr = qemu_char_get_next_serial();

2
hw/char/exynos4210_uart.c
View File

@ -630,7 +630,7 @@ static int exynos4210_uart_init(SysBusDevice *dev)
Exynos4210UartState *s = FROM_SYSBUS(Exynos4210UartState, dev);
/* memory mapping */
memory_region_init_io(&s->iomem, &exynos4210_uart_ops, s, "exynos4210.uart",
memory_region_init_io(&s->iomem, NULL, &exynos4210_uart_ops, s, "exynos4210.uart",
EXYNOS4210_UART_REGS_MEM_SIZE);
sysbus_init_mmio(dev, &s->iomem);

2
hw/char/grlib_apbuart.c
View File

@ -242,7 +242,7 @@ static int grlib_apbuart_init(SysBusDevice *dev)
sysbus_init_irq(dev, &uart->irq);
memory_region_init_io(&uart->iomem, &grlib_apbuart_ops, uart,
memory_region_init_io(&uart->iomem, NULL, &grlib_apbuart_ops, uart,
"uart", UART_REG_SIZE);
sysbus_init_mmio(dev, &uart->iomem);

2
hw/char/imx_serial.c
View File

@ -386,7 +386,7 @@ static int imx_serial_init(SysBusDevice *dev)
IMXSerialState *s = FROM_SYSBUS(IMXSerialState, dev);
memory_region_init_io(&s->iomem, &imx_serial_ops, s, "imx-serial", 0x1000);
memory_region_init_io(&s->iomem, NULL, &imx_serial_ops, s, "imx-serial", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);

2
hw/char/lm32_uart.c
View File

@ -250,7 +250,7 @@ static int lm32_uart_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->irq);
memory_region_init_io(&s->iomem, &uart_ops, s, "uart", R_MAX * 4);
memory_region_init_io(&s->iomem, NULL, &uart_ops, s, "uart", R_MAX * 4);
sysbus_init_mmio(dev, &s->iomem);
s->chr = qemu_char_get_next_serial();

2
hw/char/mcf_uart.c
View File

@ -302,6 +302,6 @@ void mcf_uart_mm_init(MemoryRegion *sysmem,
mcf_uart_state *s;
s = mcf_uart_init(irq, chr);
memory_region_init_io(&s->iomem, &mcf_uart_ops, s, "uart", 0x40);
memory_region_init_io(&s->iomem, NULL, &mcf_uart_ops, s, "uart", 0x40);
memory_region_add_subregion(sysmem, base, &s->iomem);
}

2
hw/char/milkymist-uart.c
View File

@ -196,7 +196,7 @@ static int milkymist_uart_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->irq);
memory_region_init_io(&s->regs_region, &uart_mmio_ops, s,
memory_region_init_io(&s->regs_region, NULL, &uart_mmio_ops, s,
"milkymist-uart", R_MAX * 4);
sysbus_init_mmio(dev, &s->regs_region);

2
hw/char/omap_uart.c
View File

@ -168,7 +168,7 @@ struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem,
struct omap_uart_s *s = omap_uart_init(base, irq,
fclk, iclk, txdma, rxdma, label, chr);
memory_region_init_io(&s->iomem, &omap_uart_ops, s, "omap.uart", 0x100);
memory_region_init_io(&s->iomem, NULL, &omap_uart_ops, s, "omap.uart", 0x100);
s->ta = ta;

2
hw/char/parallel.c
View File

@ -587,7 +587,7 @@ bool parallel_mm_init(MemoryRegion *address_space,
s->it_shift = it_shift;
qemu_register_reset(parallel_reset, s);
memory_region_init_io(&s->iomem, &parallel_mm_ops, s,
memory_region_init_io(&s->iomem, NULL, &parallel_mm_ops, s,
"parallel", 8 << it_shift);
memory_region_add_subregion(address_space, base, &s->iomem);
return true;

2
hw/char/pl011.c
View File

@ -265,7 +265,7 @@ static int pl011_init(SysBusDevice *dev, const unsigned char *id)
{
pl011_state *s = FROM_SYSBUS(pl011_state, dev);
memory_region_init_io(&s->iomem, &pl011_ops, s, "pl011", 0x1000);
memory_region_init_io(&s->iomem, NULL, &pl011_ops, s, "pl011", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
s->id = id;

2
hw/char/serial-isa.c
View File

@ -72,7 +72,7 @@ static void serial_isa_realizefn(DeviceState *dev, Error **errp)
serial_realize_core(s, errp);
qdev_set_legacy_instance_id(dev, isa->iobase, 3);
memory_region_init_io(&s->io, &serial_io_ops, s, "serial", 8);
memory_region_init_io(&s->io, NULL, &serial_io_ops, s, "serial", 8);
isa_register_ioport(isadev, &s->io, isa->iobase);
}

6
hw/char/serial-pci.c
View File

@ -63,7 +63,7 @@ static int serial_pci_init(PCIDevice *dev)
pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
s->irq = pci->dev.irq[0];
memory_region_init_io(&s->io, &serial_io_ops, s, "serial", 8);
memory_region_init_io(&s->io, NULL, &serial_io_ops, s, "serial", 8);
pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
return 0;
}
@ -102,7 +102,7 @@ static int multi_serial_pci_init(PCIDevice *dev)
assert(pci->ports <= PCI_SERIAL_MAX_PORTS);
pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
memory_region_init(&pci->iobar, "multiserial", 8 * pci->ports);
memory_region_init(&pci->iobar, NULL, "multiserial", 8 * pci->ports);
pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->iobar);
pci->irqs = qemu_allocate_irqs(multi_serial_irq_mux, pci,
pci->ports);
@ -118,7 +118,7 @@ static int multi_serial_pci_init(PCIDevice *dev)
}
s->irq = pci->irqs[i];
pci->name[i] = g_strdup_printf("uart #%d", i+1);
memory_region_init_io(&s->io, &serial_io_ops, s, pci->name[i], 8);
memory_region_init_io(&s->io, NULL, &serial_io_ops, s, pci->name[i], 8);
memory_region_add_subregion(&pci->iobar, 8 * i, &s->io);
}
return 0;

4
hw/char/serial.c
View File

@ -703,7 +703,7 @@ SerialState *serial_init(int base, qemu_irq irq, int baudbase,
vmstate_register(NULL, base, &vmstate_serial, s);
memory_region_init_io(&s->io, &serial_io_ops, s, "serial", 8);
memory_region_init_io(&s->io, NULL, &serial_io_ops, s, "serial", 8);
memory_region_add_subregion(system_io, base, &s->io);
return s;
@ -766,7 +766,7 @@ SerialState *serial_mm_init(MemoryRegion *address_space,
}
vmstate_register(NULL, base, &vmstate_serial, s);
memory_region_init_io(&s->io, &serial_mm_ops[end], s,
memory_region_init_io(&s->io, NULL, &serial_mm_ops[end], s,
"serial", 8 << it_shift);
memory_region_add_subregion(address_space, base, &s->io);

6
hw/char/sh_serial.c
View File

@ -383,14 +383,14 @@ void sh_serial_init(MemoryRegion *sysmem,
sh_serial_clear_fifo(s);
memory_region_init_io(&s->iomem, &sh_serial_ops, s,
memory_region_init_io(&s->iomem, NULL, &sh_serial_ops, s,
"serial", 0x100000000ULL);
memory_region_init_alias(&s->iomem_p4, "serial-p4", &s->iomem,
memory_region_init_alias(&s->iomem_p4, NULL, "serial-p4", &s->iomem,
0, 0x28);
memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);
memory_region_init_alias(&s->iomem_a7, "serial-a7", &s->iomem,
memory_region_init_alias(&s->iomem_a7, NULL, "serial-a7", &s->iomem,
0, 0x28);
memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);

12
hw/char/tpci200.c
View File

@ -588,17 +588,17 @@ static int tpci200_initfn(PCIDevice *pci_dev)
pci_set_long(c + 0x48, 0x00024C06);
pci_set_long(c + 0x4C, 0x00000003);
memory_region_init_io(&s->mmio, &tpci200_cfg_ops,
memory_region_init_io(&s->mmio, NULL, &tpci200_cfg_ops,
s, "tpci200_mmio", 128);
memory_region_init_io(&s->io, &tpci200_cfg_ops,
memory_region_init_io(&s->io, NULL, &tpci200_cfg_ops,
s, "tpci200_io", 128);
memory_region_init_io(&s->las0, &tpci200_las0_ops,
memory_region_init_io(&s->las0, NULL, &tpci200_las0_ops,
s, "tpci200_las0", 256);
memory_region_init_io(&s->las1, &tpci200_las1_ops,
memory_region_init_io(&s->las1, NULL, &tpci200_las1_ops,
s, "tpci200_las1", 1024);
memory_region_init_io(&s->las2, &tpci200_las2_ops,
memory_region_init_io(&s->las2, NULL, &tpci200_las2_ops,
s, "tpci200_las2", 1024*1024*32);
memory_region_init_io(&s->las3, &tpci200_las3_ops,
memory_region_init_io(&s->las3, NULL, &tpci200_las3_ops,
s, "tpci200_las3", 1024*1024*16);
pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mmio);
pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io);

2
hw/char/xilinx_uartlite.c
View File

@ -199,7 +199,7 @@ static int xilinx_uartlite_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->irq);
uart_update_status(s);
memory_region_init_io(&s->mmio, &uart_ops, s, "xlnx.xps-uartlite",
memory_region_init_io(&s->mmio, NULL, &uart_ops, s, "xlnx.xps-uartlite",
R_MAX * 4);
sysbus_init_mmio(dev, &s->mmio);

2
hw/core/empty_slot.c
View File

@ -70,7 +70,7 @@ static int empty_slot_init1(SysBusDevice *dev)
{
EmptySlot *s = FROM_SYSBUS(EmptySlot, dev);
memory_region_init_io(&s->iomem, &empty_slot_ops, s,
memory_region_init_io(&s->iomem, NULL, &empty_slot_ops, s,
"empty-slot", s->size);
sysbus_init_mmio(dev, &s->iomem);
return 0;

2
hw/cpu/a15mpcore.c
View File

@ -68,7 +68,7 @@ static int a15mp_priv_init(SysBusDevice *dev)
* 0x5000-0x5fff -- GIC virtual interface control (not modelled)
* 0x6000-0x7fff -- GIC virtual CPU interface (not modelled)
*/
memory_region_init(&s->container, "a15mp-priv-container", 0x8000);
memory_region_init(&s->container, NULL, "a15mp-priv-container", 0x8000);
memory_region_add_subregion(&s->container, 0x1000,
sysbus_mmio_get_region(busdev, 0));
memory_region_add_subregion(&s->container, 0x2000,

2
hw/cpu/a9mpcore.c
View File

@ -71,7 +71,7 @@ static int a9mp_priv_init(SysBusDevice *dev)
*
* We should implement the global timer but don't currently do so.
*/
memory_region_init(&s->container, "a9mp-priv-container", 0x2000);
memory_region_init(&s->container, NULL, "a9mp-priv-container", 0x2000);
memory_region_add_subregion(&s->container, 0,
sysbus_mmio_get_region(scubusdev, 0));
/* GIC CPU interface */

4
hw/cpu/arm11mpcore.c
View File

@ -87,8 +87,8 @@ static void mpcore_priv_map_setup(ARM11MPCorePriveState *s)
SysBusDevice *gicbusdev = SYS_BUS_DEVICE(s->gic);
SysBusDevice *timerbusdev = SYS_BUS_DEVICE(s->mptimer);
SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(s->wdtimer);
memory_region_init(&s->container, "mpcode-priv-container", 0x2000);
memory_region_init_io(&s->iomem, &mpcore_scu_ops, s, "mpcore-scu", 0x100);
memory_region_init(&s->container, NULL, "mpcode-priv-container", 0x2000);
memory_region_init_io(&s->iomem, NULL, &mpcore_scu_ops, s, "mpcore-scu", 0x100);
memory_region_add_subregion(&s->container, 0, &s->iomem);
/* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs
* at 0x200, 0x300...

2
hw/cpu/icc_bus.c
View File

@ -95,7 +95,7 @@ static void icc_bridge_init(Object *obj)
/* Do not change order of registering regions,
* APIC must be first registered region, board maps it by 0 index
*/
memory_region_init(&s->apic_container, "icc-apic-container",
memory_region_init(&s->apic_container, NULL, "icc-apic-container",
APIC_SPACE_SIZE);
sysbus_init_mmio(sb, &s->apic_container);
s->icc_bus.apic_address_space = &s->apic_container;

8
hw/cris/axis_dev88.c
View File

@ -269,13 +269,13 @@ void axisdev88_init(QEMUMachineInitArgs *args)
env = &cpu->env;
/* allocate RAM */
memory_region_init_ram(phys_ram, "axisdev88.ram", ram_size);
memory_region_init_ram(phys_ram, NULL, "axisdev88.ram", ram_size);
vmstate_register_ram_global(phys_ram);
memory_region_add_subregion(address_space_mem, 0x40000000, phys_ram);
/* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the
internal memory. */
memory_region_init_ram(phys_intmem, "axisdev88.chipram", INTMEM_SIZE);
memory_region_init_ram(phys_intmem, NULL, "axisdev88.chipram", INTMEM_SIZE);
vmstate_register_ram_global(phys_intmem);
memory_region_add_subregion(address_space_mem, 0x38000000, phys_intmem);
@ -283,13 +283,13 @@ void axisdev88_init(QEMUMachineInitArgs *args)
nand = drive_get(IF_MTD, 0, 0);
nand_state.nand = nand_init(nand ? nand->bdrv : NULL,
NAND_MFR_STMICRO, 0x39);
memory_region_init_io(&nand_state.iomem, &nand_ops, &nand_state,
memory_region_init_io(&nand_state.iomem, NULL, &nand_ops, &nand_state,
"nand", 0x05000000);
memory_region_add_subregion(address_space_mem, 0x10000000,
&nand_state.iomem);
gpio_state.nand = &nand_state;
memory_region_init_io(&gpio_state.iomem, &gpio_ops, &gpio_state,
memory_region_init_io(&gpio_state.iomem, NULL, &gpio_ops, &gpio_state,
"gpio", 0x5c);
memory_region_add_subregion(address_space_mem, 0x3001a000,
&gpio_state.iomem);

16
hw/display/cirrus_vga.c
View File

@ -2840,21 +2840,21 @@ static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci,
}
/* Register ioport 0x3b0 - 0x3df */
memory_region_init_io(&s->cirrus_vga_io, &cirrus_vga_io_ops, s,
memory_region_init_io(&s->cirrus_vga_io, NULL, &cirrus_vga_io_ops, s,
"cirrus-io", 0x30);
memory_region_add_subregion(system_io, 0x3b0, &s->cirrus_vga_io);
memory_region_init(&s->low_mem_container,
memory_region_init(&s->low_mem_container, NULL,
"cirrus-lowmem-container",
0x20000);
memory_region_init_io(&s->low_mem, &cirrus_vga_mem_ops, s,
memory_region_init_io(&s->low_mem, NULL, &cirrus_vga_mem_ops, s,
"cirrus-low-memory", 0x20000);
memory_region_add_subregion(&s->low_mem_container, 0, &s->low_mem);
for (i = 0; i < 2; ++i) {
static const char *names[] = { "vga.bank0", "vga.bank1" };
MemoryRegion *bank = &s->cirrus_bank[i];
memory_region_init_alias(bank, names[i], &s->vga.vram, 0, 0x8000);
memory_region_init_alias(bank, NULL, names[i], &s->vga.vram, 0, 0x8000);
memory_region_set_enabled(bank, false);
memory_region_add_subregion_overlap(&s->low_mem_container, i * 0x8000,
bank, 1);
@ -2866,13 +2866,13 @@ static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci,
memory_region_set_coalescing(&s->low_mem);
/* I/O handler for LFB */
memory_region_init_io(&s->cirrus_linear_io, &cirrus_linear_io_ops, s,
memory_region_init_io(&s->cirrus_linear_io, NULL, &cirrus_linear_io_ops, s,
"cirrus-linear-io", s->vga.vram_size_mb
* 1024 * 1024);
memory_region_set_flush_coalesced(&s->cirrus_linear_io);
/* I/O handler for LFB */
memory_region_init_io(&s->cirrus_linear_bitblt_io,
memory_region_init_io(&s->cirrus_linear_bitblt_io, NULL,
&cirrus_linear_bitblt_io_ops,
s,
"cirrus-bitblt-mmio",
@ -2880,7 +2880,7 @@ static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci,
memory_region_set_flush_coalesced(&s->cirrus_linear_bitblt_io);
/* I/O handler for memory-mapped I/O */
memory_region_init_io(&s->cirrus_mmio_io, &cirrus_mmio_io_ops, s,
memory_region_init_io(&s->cirrus_mmio_io, NULL, &cirrus_mmio_io_ops, s,
"cirrus-mmio", CIRRUS_PNPMMIO_SIZE);
memory_region_set_flush_coalesced(&s->cirrus_mmio_io);
@ -2965,7 +2965,7 @@ static int pci_cirrus_vga_initfn(PCIDevice *dev)
/* setup PCI */
memory_region_init(&s->pci_bar, "cirrus-pci-bar0", 0x2000000);
memory_region_init(&s->pci_bar, NULL, "cirrus-pci-bar0", 0x2000000);
/* XXX: add byte swapping apertures */
memory_region_add_subregion(&s->pci_bar, 0, &s->cirrus_linear_io);

2
hw/display/exynos4210_fimd.c
View File

@ -1902,7 +1902,7 @@ static int exynos4210_fimd_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->irq[1]);
sysbus_init_irq(dev, &s->irq[2]);
memory_region_init_io(&s->iomem, &exynos4210_fimd_mmio_ops, s,
memory_region_init_io(&s->iomem, NULL, &exynos4210_fimd_mmio_ops, s,
"exynos4210.fimd", FIMD_REGS_SIZE);
sysbus_init_mmio(dev, &s->iomem);
s->console = graphic_console_init(DEVICE(dev), &exynos4210_fimd_ops, s);

4
hw/display/g364fb.c
View File

@ -486,8 +486,8 @@ static void g364fb_init(DeviceState *dev, G364State *s)
s->con = graphic_console_init(dev, &g364fb_ops, s);
memory_region_init_io(&s->mem_ctrl, &g364fb_ctrl_ops, s, "ctrl", 0x180000);
memory_region_init_ram_ptr(&s->mem_vram, "vram",
memory_region_init_io(&s->mem_ctrl, NULL, &g364fb_ctrl_ops, s, "ctrl", 0x180000);
memory_region_init_ram_ptr(&s->mem_vram, NULL, "vram",
s->vram_size, s->vram);
vmstate_register_ram(&s->mem_vram, dev);
memory_region_set_coalescing(&s->mem_vram);

2
hw/display/jazz_led.c
View File

@ -264,7 +264,7 @@ static int jazz_led_init(SysBusDevice *dev)
{
LedState *s = FROM_SYSBUS(LedState, dev);
memory_region_init_io(&s->iomem, &led_ops, s, "led", 1);
memory_region_init_io(&s->iomem, NULL, &led_ops, s, "led", 1);
sysbus_init_mmio(dev, &s->iomem);
s->con = graphic_console_init(DEVICE(dev), &jazz_led_ops, s);

2
hw/display/milkymist-tmu2.c
View File

@ -447,7 +447,7 @@ static int milkymist_tmu2_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->irq);
memory_region_init_io(&s->regs_region, &tmu2_mmio_ops, s,
memory_region_init_io(&s->regs_region, NULL, &tmu2_mmio_ops, s,
"milkymist-tmu2", R_MAX * 4);
sysbus_init_mmio(dev, &s->regs_region);

2
hw/display/milkymist-vgafb.c
View File

@ -279,7 +279,7 @@ static int milkymist_vgafb_init(SysBusDevice *dev)
{
MilkymistVgafbState *s = FROM_SYSBUS(typeof(*s), dev);
memory_region_init_io(&s->regs_region, &vgafb_mmio_ops, s,
memory_region_init_io(&s->regs_region, NULL, &vgafb_mmio_ops, s,
"milkymist-vgafb", R_MAX * 4);
sysbus_init_mmio(dev, &s->regs_region);

10
hw/display/omap_dss.c
View File

@ -1053,15 +1053,15 @@ struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
s->drq = drq;
omap_dss_reset(s);
memory_region_init_io(&s->iomem_diss1, &omap_diss_ops, s, "omap.diss1",
memory_region_init_io(&s->iomem_diss1, NULL, &omap_diss_ops, s, "omap.diss1",
omap_l4_region_size(ta, 0));
memory_region_init_io(&s->iomem_disc1, &omap_disc_ops, s, "omap.disc1",
memory_region_init_io(&s->iomem_disc1, NULL, &omap_disc_ops, s, "omap.disc1",
omap_l4_region_size(ta, 1));
memory_region_init_io(&s->iomem_rfbi1, &omap_rfbi_ops, s, "omap.rfbi1",
memory_region_init_io(&s->iomem_rfbi1, NULL, &omap_rfbi_ops, s, "omap.rfbi1",
omap_l4_region_size(ta, 2));
memory_region_init_io(&s->iomem_venc1, &omap_venc_ops, s, "omap.venc1",
memory_region_init_io(&s->iomem_venc1, NULL, &omap_venc_ops, s, "omap.venc1",
omap_l4_region_size(ta, 3));
memory_region_init_io(&s->iomem_im3, &omap_im3_ops, s,
memory_region_init_io(&s->iomem_im3, NULL, &omap_im3_ops, s,
"omap.im3", 0x1000);
omap_l4_attach(ta, 0, &s->iomem_diss1);

2
hw/display/omap_lcdc.c
View File

@ -403,7 +403,7 @@ struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem,
s->sysmem = sysmem;
omap_lcdc_reset(s);
memory_region_init_io(&s->iomem, &omap_lcdc_ops, s, "omap.lcdc", 0x100);
memory_region_init_io(&s->iomem, NULL, &omap_lcdc_ops, s, "omap.lcdc", 0x100);
memory_region_add_subregion(sysmem, base, &s->iomem);
s->con = graphic_console_init(NULL, &omap_ops, s);

2
hw/display/pl110.c
View File

@ -453,7 +453,7 @@ static int pl110_init(SysBusDevice *dev)
{
pl110_state *s = FROM_SYSBUS(pl110_state, dev);
memory_region_init_io(&s->iomem, &pl110_ops, s, "pl110", 0x1000);
memory_region_init_io(&s->iomem, NULL, &pl110_ops, s, "pl110", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
qdev_init_gpio_in(&s->busdev.qdev, pl110_mux_ctrl_set, 1);

2
hw/display/pxa2xx_lcd.c
View File

@ -1009,7 +1009,7 @@ PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem,
pxa2xx_lcdc_orientation(s, graphic_rotate);
memory_region_init_io(&s->iomem, &pxa2xx_lcdc_ops, s,
memory_region_init_io(&s->iomem, NULL, &pxa2xx_lcdc_ops, s,
"pxa2xx-lcd-controller", 0x00100000);
memory_region_add_subregion(sysmem, base, &s->iomem);

10
hw/display/qxl.c
View File

@ -1981,18 +1981,18 @@ static int qxl_init_common(PCIQXLDevice *qxl)
pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
qxl->rom_size = qxl_rom_size();
memory_region_init_ram(&qxl->rom_bar, "qxl.vrom", qxl->rom_size);
memory_region_init_ram(&qxl->rom_bar, NULL, "qxl.vrom", qxl->rom_size);
vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev);
init_qxl_rom(qxl);
init_qxl_ram(qxl);
qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces);
memory_region_init_ram(&qxl->vram_bar, "qxl.vram", qxl->vram_size);
memory_region_init_ram(&qxl->vram_bar, NULL, "qxl.vram", qxl->vram_size);
vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev);
memory_region_init_alias(&qxl->vram32_bar, "qxl.vram32", &qxl->vram_bar,
memory_region_init_alias(&qxl->vram32_bar, NULL, "qxl.vram32", &qxl->vram_bar,
0, qxl->vram32_size);
memory_region_init_io(&qxl->io_bar, &qxl_io_ops, qxl,
memory_region_init_io(&qxl->io_bar, NULL, &qxl_io_ops, qxl,
"qxl-ioports", io_size);
if (qxl->id == 0) {
vga_dirty_log_start(&qxl->vga);
@ -2093,7 +2093,7 @@ static int qxl_init_secondary(PCIDevice *dev)
qxl->id = device_id++;
qxl_init_ramsize(qxl);
memory_region_init_ram(&qxl->vga.vram, "qxl.vgavram", qxl->vga.vram_size);
memory_region_init_ram(&qxl->vga.vram, NULL, "qxl.vgavram", qxl->vga.vram_size);
vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev);
qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
qxl->vga.con = graphic_console_init(DEVICE(dev), &qxl_ops, qxl);

8
hw/display/sm501.c
View File

@ -1408,23 +1408,23 @@ void sm501_init(MemoryRegion *address_space_mem, uint32_t base,
s->dc_crt_control = 0x00010000;
/* allocate local memory */
memory_region_init_ram(&s->local_mem_region, "sm501.local",
memory_region_init_ram(&s->local_mem_region, NULL, "sm501.local",
local_mem_bytes);
vmstate_register_ram_global(&s->local_mem_region);
s->local_mem = memory_region_get_ram_ptr(&s->local_mem_region);
memory_region_add_subregion(address_space_mem, base, &s->local_mem_region);
/* map mmio */
memory_region_init_io(sm501_system_config, &sm501_system_config_ops, s,
memory_region_init_io(sm501_system_config, NULL, &sm501_system_config_ops, s,
"sm501-system-config", 0x6c);
memory_region_add_subregion(address_space_mem, base + MMIO_BASE_OFFSET,
sm501_system_config);
memory_region_init_io(sm501_disp_ctrl, &sm501_disp_ctrl_ops, s,
memory_region_init_io(sm501_disp_ctrl, NULL, &sm501_disp_ctrl_ops, s,
"sm501-disp-ctrl", 0x1000);
memory_region_add_subregion(address_space_mem,
base + MMIO_BASE_OFFSET + SM501_DC,
sm501_disp_ctrl);
memory_region_init_io(sm501_2d_engine, &sm501_2d_engine_ops, s,
memory_region_init_io(sm501_2d_engine, NULL, &sm501_2d_engine_ops, s,
"sm501-2d-engine", 0x54);
memory_region_add_subregion(address_space_mem,
base + MMIO_BASE_OFFSET + SM501_2D_ENGINE,

4
hw/display/tc6393xb.c
View File

@ -578,10 +578,10 @@ TC6393xbState *tc6393xb_init(MemoryRegion *sysmem, uint32_t base, qemu_irq irq)
nand = drive_get(IF_MTD, 0, 0);
s->flash = nand_init(nand ? nand->bdrv : NULL, NAND_MFR_TOSHIBA, 0x76);
memory_region_init_io(&s->iomem, &tc6393xb_ops, s, "tc6393xb", 0x10000);
memory_region_init_io(&s->iomem, NULL, &tc6393xb_ops, s, "tc6393xb", 0x10000);
memory_region_add_subregion(sysmem, base, &s->iomem);
memory_region_init_ram(&s->vram, "tc6393xb.vram", 0x100000);
memory_region_init_ram(&s->vram, NULL, "tc6393xb.vram", 0x100000);
vmstate_register_ram_global(&s->vram);
s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
memory_region_add_subregion(sysmem, base + 0x100000, &s->vram);

16
hw/display/tcx.c
View File

@ -528,7 +528,7 @@ static int tcx_init1(SysBusDevice *dev)
int size;
uint8_t *vram_base;
memory_region_init_ram(&s->vram_mem, "tcx.vram",
memory_region_init_ram(&s->vram_mem, NULL, "tcx.vram",
s->vram_size * (1 + 4 + 4));
vmstate_register_ram_global(&s->vram_mem);
vram_base = memory_region_get_ram_ptr(&s->vram_mem);
@ -536,21 +536,21 @@ static int tcx_init1(SysBusDevice *dev)
/* 8-bit plane */
s->vram = vram_base;
size = s->vram_size;
memory_region_init_alias(&s->vram_8bit, "tcx.vram.8bit",
memory_region_init_alias(&s->vram_8bit, NULL, "tcx.vram.8bit",
&s->vram_mem, vram_offset, size);
sysbus_init_mmio(dev, &s->vram_8bit);
vram_offset += size;
vram_base += size;
/* DAC */
memory_region_init_io(&s->dac, &tcx_dac_ops, s, "tcx.dac", TCX_DAC_NREGS);
memory_region_init_io(&s->dac, NULL, &tcx_dac_ops, s, "tcx.dac", TCX_DAC_NREGS);
sysbus_init_mmio(dev, &s->dac);
/* TEC (dummy) */
memory_region_init_io(&s->tec, &dummy_ops, s, "tcx.tec", TCX_TEC_NREGS);
memory_region_init_io(&s->tec, NULL, &dummy_ops, s, "tcx.tec", TCX_TEC_NREGS);
sysbus_init_mmio(dev, &s->tec);
/* THC: NetBSD writes here even with 8-bit display: dummy */
memory_region_init_io(&s->thc24, &dummy_ops, s, "tcx.thc24",
memory_region_init_io(&s->thc24, NULL, &dummy_ops, s, "tcx.thc24",
TCX_THC_NREGS_24);
sysbus_init_mmio(dev, &s->thc24);
@ -559,7 +559,7 @@ static int tcx_init1(SysBusDevice *dev)
size = s->vram_size * 4;
s->vram24 = (uint32_t *)vram_base;
s->vram24_offset = vram_offset;
memory_region_init_alias(&s->vram_24bit, "tcx.vram.24bit",
memory_region_init_alias(&s->vram_24bit, NULL, "tcx.vram.24bit",
&s->vram_mem, vram_offset, size);
sysbus_init_mmio(dev, &s->vram_24bit);
vram_offset += size;
@ -569,14 +569,14 @@ static int tcx_init1(SysBusDevice *dev)
size = s->vram_size * 4;
s->cplane = (uint32_t *)vram_base;
s->cplane_offset = vram_offset;
memory_region_init_alias(&s->vram_cplane, "tcx.vram.cplane",
memory_region_init_alias(&s->vram_cplane, NULL, "tcx.vram.cplane",
&s->vram_mem, vram_offset, size);
sysbus_init_mmio(dev, &s->vram_cplane);
s->con = graphic_console_init(DEVICE(dev), &tcx24_ops, s);
} else {
/* THC 8 bit (dummy) */
memory_region_init_io(&s->thc8, &dummy_ops, s, "tcx.thc8",
memory_region_init_io(&s->thc8, NULL, &dummy_ops, s, "tcx.thc8",
TCX_THC_NREGS_8);
sysbus_init_mmio(dev, &s->thc8);

4
hw/display/vga-isa-mm.c
View File

@ -105,13 +105,13 @@ static void vga_mm_init(ISAVGAMMState *s, hwaddr vram_base,
s->it_shift = it_shift;
s_ioport_ctrl = g_malloc(sizeof(*s_ioport_ctrl));
memory_region_init_io(s_ioport_ctrl, &vga_mm_ctrl_ops, s,
memory_region_init_io(s_ioport_ctrl, NULL, &vga_mm_ctrl_ops, s,
"vga-mm-ctrl", 0x100000);
memory_region_set_flush_coalesced(s_ioport_ctrl);
vga_io_memory = g_malloc(sizeof(*vga_io_memory));
/* XXX: endianness? */
memory_region_init_io(vga_io_memory, &vga_mem_ops, &s->vga,
memory_region_init_io(vga_io_memory, NULL, &vga_mem_ops, &s->vga,
"vga-mem", 0x20000);
vmstate_register(NULL, 0, &vmstate_vga_common, s);

6
hw/display/vga-pci.c
View File

@ -157,10 +157,10 @@ static int pci_std_vga_initfn(PCIDevice *dev)
/* mmio bar for vga register access */
if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_MMIO)) {
memory_region_init(&d->mmio, "vga.mmio", 4096);
memory_region_init_io(&d->ioport, &pci_vga_ioport_ops, d,
memory_region_init(&d->mmio, NULL, "vga.mmio", 4096);
memory_region_init_io(&d->ioport, NULL, &pci_vga_ioport_ops, d,
"vga ioports remapped", PCI_VGA_IOPORT_SIZE);
memory_region_init_io(&d->bochs, &pci_vga_bochs_ops, d,
memory_region_init_io(&d->bochs, NULL, &pci_vga_bochs_ops, d,
"bochs dispi interface", PCI_VGA_BOCHS_SIZE);
memory_region_add_subregion(&d->mmio, PCI_VGA_IOPORT_OFFSET,

8
hw/display/vga.c
View File

@ -198,7 +198,7 @@ static void vga_update_memory_access(VGACommonState *s)
}
base += isa_mem_base;
region = g_malloc(sizeof(*region));
memory_region_init_alias(region, "vga.chain4", &s->vram, offset, size);
memory_region_init_alias(region, NULL, "vga.chain4", &s->vram, offset, size);
memory_region_add_subregion_overlap(s->legacy_address_space, base,
region, 2);
s->chain4_alias = region;
@ -2292,7 +2292,7 @@ void vga_common_init(VGACommonState *s)
s->vram_size_mb = s->vram_size >> 20;
s->is_vbe_vmstate = 1;
memory_region_init_ram(&s->vram, "vga.vram", s->vram_size);
memory_region_init_ram(&s->vram, NULL, "vga.vram", s->vram_size);
vmstate_register_ram_global(&s->vram);
xen_register_framebuffer(&s->vram);
s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
@ -2343,7 +2343,7 @@ MemoryRegion *vga_init_io(VGACommonState *s,
*vbe_ports = vbe_portio_list;
vga_mem = g_malloc(sizeof(*vga_mem));
memory_region_init_io(vga_mem, &vga_mem_ops, s,
memory_region_init_io(vga_mem, NULL, &vga_mem_ops, s,
"vga-lowmem", 0x20000);
memory_region_set_flush_coalesced(vga_mem);
@ -2385,7 +2385,7 @@ void vga_init_vbe(VGACommonState *s, MemoryRegion *system_memory)
/* With pc-0.12 and below we map both the PCI BAR and the fixed VBE region,
* so use an alias to avoid double-mapping the same region.
*/
memory_region_init_alias(&s->vram_vbe, "vram.vbe",
memory_region_init_alias(&s->vram_vbe, NULL, "vram.vbe",
&s->vram, 0, memory_region_size(&s->vram));
/* XXX: use optimized standard vga accesses */
memory_region_add_subregion(system_memory,

4
hw/display/vmware_vga.c
View File

@ -1194,7 +1194,7 @@ static void vmsvga_init(DeviceState *dev, struct vmsvga_state_s *s,
s->vga.con = graphic_console_init(dev, &vmsvga_ops, s);
s->fifo_size = SVGA_FIFO_SIZE;
memory_region_init_ram(&s->fifo_ram, "vmsvga.fifo", s->fifo_size);
memory_region_init_ram(&s->fifo_ram, NULL, "vmsvga.fifo", s->fifo_size);
vmstate_register_ram_global(&s->fifo_ram);
s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram);
@ -1257,7 +1257,7 @@ static int pci_vmsvga_initfn(PCIDevice *dev)
s->card.config[PCI_LATENCY_TIMER] = 0x40; /* Latency timer */
s->card.config[PCI_INTERRUPT_LINE] = 0xff; /* End */
memory_region_init_io(&s->io_bar, &vmsvga_io_ops, &s->chip,
memory_region_init_io(&s->io_bar, NULL, &vmsvga_io_ops, &s->chip,
"vmsvga-io", 0x10);
memory_region_set_flush_coalesced(&s->io_bar);
pci_register_bar(&s->card, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);

2
hw/dma/etraxfs_dma.c
View File

@ -773,7 +773,7 @@ void *etraxfs_dmac_init(hwaddr base, int nr_channels)
ctrl->nr_channels = nr_channels;
ctrl->channels = g_malloc0(sizeof ctrl->channels[0] * nr_channels);
memory_region_init_io(&ctrl->mmio, &dma_ops, ctrl, "etraxfs-dma",
memory_region_init_io(&ctrl->mmio, NULL, &dma_ops, ctrl, "etraxfs-dma",
nr_channels * 0x2000);
memory_region_add_subregion(get_system_memory(), base, &ctrl->mmio);

4
hw/dma/i8257.c
View File

@ -523,7 +523,7 @@ static void dma_init2(struct dma_cont *d, int base, int dshift,
d->dshift = dshift;
d->cpu_request_exit = cpu_request_exit;
memory_region_init_io(&d->channel_io, &channel_io_ops, d,
memory_region_init_io(&d->channel_io, NULL, &channel_io_ops, d,
"dma-chan", 8 << d->dshift);
memory_region_add_subregion(isa_address_space_io(NULL),
base, &d->channel_io);
@ -535,7 +535,7 @@ static void dma_init2(struct dma_cont *d, int base, int dshift,
"dma-pageh");
}
memory_region_init_io(&d->cont_io, &cont_io_ops, d, "dma-cont",
memory_region_init_io(&d->cont_io, NULL, &cont_io_ops, d, "dma-cont",
8 << d->dshift);
memory_region_add_subregion(isa_address_space_io(NULL),
base + (8 << d->dshift), &d->cont_io);

4
hw/dma/omap_dma.c
View File

@ -1663,7 +1663,7 @@ struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs,
omap_dma_reset(s->dma);
omap_dma_clk_update(s, 0, 1);
memory_region_init_io(&s->iomem, &omap_dma_ops, s, "omap.dma", memsize);
memory_region_init_io(&s->iomem, NULL, &omap_dma_ops, s, "omap.dma", memsize);
memory_region_add_subregion(sysmem, base, &s->iomem);
mpu->drq = s->dma->drq;
@ -2085,7 +2085,7 @@ struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs,
omap_dma_reset(s->dma);
omap_dma_clk_update(s, 0, !!s->dma->freq);
memory_region_init_io(&s->iomem, &omap_dma4_ops, s, "omap.dma4", 0x1000);
memory_region_init_io(&s->iomem, NULL, &omap_dma4_ops, s, "omap.dma4", 0x1000);
memory_region_add_subregion(sysmem, base, &s->iomem);
mpu->drq = s->dma->drq;

2
hw/dma/pl080.c
View File

@ -359,7 +359,7 @@ static int pl08x_init(SysBusDevice *dev, int nchannels)
{
pl080_state *s = FROM_SYSBUS(pl080_state, dev);
memory_region_init_io(&s->iomem, &pl080_ops, s, "pl080", 0x1000);
memory_region_init_io(&s->iomem, NULL, &pl080_ops, s, "pl080", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
s->nchannels = nchannels;

2
hw/dma/pl330.c
View File

@ -1528,7 +1528,7 @@ static void pl330_realize(DeviceState *dev, Error **errp)
PL330State *s = PL330(dev);
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq_abort);
memory_region_init_io(&s->iomem, &pl330_ops, s, "dma", PL330_IOMEM_SIZE);
memory_region_init_io(&s->iomem, NULL, &pl330_ops, s, "dma", PL330_IOMEM_SIZE);
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
s->timer = qemu_new_timer_ns(vm_clock, pl330_exec_cycle_timer, s);

2
hw/dma/puv3_dma.c
View File

@ -80,7 +80,7 @@ static int puv3_dma_init(SysBusDevice *dev)
s->reg_CFG[i] = 0x0;
}
memory_region_init_io(&s->iomem, &puv3_dma_ops, s, "puv3_dma",
memory_region_init_io(&s->iomem, NULL, &puv3_dma_ops, s, "puv3_dma",
PUV3_REGS_OFFSET);
sysbus_init_mmio(dev, &s->iomem);

2
hw/dma/pxa2xx_dma.c
View File

@ -465,7 +465,7 @@ static int pxa2xx_dma_init(SysBusDevice *dev)
qdev_init_gpio_in(&dev->qdev, pxa2xx_dma_request, PXA2XX_DMA_NUM_REQUESTS);
memory_region_init_io(&s->iomem, &pxa2xx_dma_ops, s,
memory_region_init_io(&s->iomem, NULL, &pxa2xx_dma_ops, s,
"pxa2xx.dma", 0x00010000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);

4
hw/dma/rc4030.c
View File

@ -814,10 +814,10 @@ void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
register_savevm(NULL, "rc4030", 0, 2, rc4030_save, rc4030_load, s);
rc4030_reset(s);
memory_region_init_io(&s->iomem_chipset, &rc4030_ops, s,
memory_region_init_io(&s->iomem_chipset, NULL, &rc4030_ops, s,
"rc4030.chipset", 0x300);
memory_region_add_subregion(sysmem, 0x80000000, &s->iomem_chipset);
memory_region_init_io(&s->iomem_jazzio, &jazzio_ops, s,
memory_region_init_io(&s->iomem_jazzio, NULL, &jazzio_ops, s,
"rc4030.jazzio", 0x00001000);
memory_region_add_subregion(sysmem, 0xf0000000, &s->iomem_jazzio);

2
hw/dma/sparc32_dma.c
View File

@ -274,7 +274,7 @@ static int sparc32_dma_init1(SysBusDevice *dev)
sysbus_init_irq(dev, &s->irq);
reg_size = s->is_ledma ? DMA_ETH_SIZE : DMA_SIZE;
memory_region_init_io(&s->iomem, &dma_mem_ops, s, "dma", reg_size);
memory_region_init_io(&s->iomem, NULL, &dma_mem_ops, s, "dma", reg_size);
sysbus_init_mmio(dev, &s->iomem);
qdev_init_gpio_in(&dev->qdev, dma_set_irq, 1);

2
hw/dma/sun4m_iommu.c
View File

@ -349,7 +349,7 @@ static int iommu_init1(SysBusDevice *dev)
sysbus_init_irq(dev, &s->irq);
memory_region_init_io(&s->iomem, &iommu_mem_ops, s, "iommu",
memory_region_init_io(&s->iomem, NULL, &iommu_mem_ops, s, "iommu",
IOMMU_NREGS * sizeof(uint32_t));
sysbus_init_mmio(dev, &s->iomem);

2
hw/dma/xilinx_axidma.c
View File

@ -590,7 +590,7 @@ static void xilinx_axidma_init(Object *obj)
sysbus_init_irq(sbd, &s->streams[0].irq);
sysbus_init_irq(sbd, &s->streams[1].irq);
memory_region_init_io(&s->iomem, &axidma_ops, s,
memory_region_init_io(&s->iomem, NULL, &axidma_ops, s,
"xlnx.axi-dma", R_MAX * 4 * 2);
sysbus_init_mmio(sbd, &s->iomem);
}

6
hw/gpio/omap_gpio.c
View File

@ -677,7 +677,7 @@ static int omap_gpio_init(SysBusDevice *dev)
qdev_init_gpio_in(&dev->qdev, omap_gpio_set, 16);
qdev_init_gpio_out(&dev->qdev, s->omap1.handler, 16);
sysbus_init_irq(dev, &s->omap1.irq);
memory_region_init_io(&s->iomem, &omap_gpio_ops, &s->omap1,
memory_region_init_io(&s->iomem, NULL, &omap_gpio_ops, &s->omap1,
"omap.gpio", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
return 0;
@ -692,7 +692,7 @@ static int omap2_gpio_init(SysBusDevice *dev)
}
if (s->mpu_model < omap3430) {
s->modulecount = (s->mpu_model < omap2430) ? 4 : 5;
memory_region_init_io(&s->iomem, &omap2_gpif_top_ops, s,
memory_region_init_io(&s->iomem, NULL, &omap2_gpif_top_ops, s,
"omap2.gpio", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
} else {
@ -712,7 +712,7 @@ static int omap2_gpio_init(SysBusDevice *dev)
sysbus_init_irq(dev, &m->irq[0]); /* mpu irq */
sysbus_init_irq(dev, &m->irq[1]); /* dsp irq */
sysbus_init_irq(dev, &m->wkup);
memory_region_init_io(&m->iomem, &omap2_gpio_module_ops, m,
memory_region_init_io(&m->iomem, NULL, &omap2_gpio_module_ops, m,
"omap.gpio-module", 0x1000);
sysbus_init_mmio(dev, &m->iomem);
}

2
hw/gpio/pl061.c
View File

@ -276,7 +276,7 @@ static int pl061_init(SysBusDevice *dev, const unsigned char *id)
{
pl061_state *s = FROM_SYSBUS(pl061_state, dev);
s->id = id;
memory_region_init_io(&s->iomem, &pl061_ops, s, "pl061", 0x1000);
memory_region_init_io(&s->iomem, NULL, &pl061_ops, s, "pl061", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
qdev_init_gpio_in(&dev->qdev, pl061_set_irq, 8);

2
hw/gpio/puv3_gpio.c
View File

@ -112,7 +112,7 @@ static int puv3_gpio_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW7]);
sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOHIGH]);
memory_region_init_io(&s->iomem, &puv3_gpio_ops, s, "puv3_gpio",
memory_region_init_io(&s->iomem, NULL, &puv3_gpio_ops, s, "puv3_gpio",
PUV3_REGS_OFFSET);
sysbus_init_mmio(dev, &s->iomem);

2
hw/gpio/zaurus.c
View File

@ -169,7 +169,7 @@ static int scoop_init(SysBusDevice *dev)
s->status = 0x02;
qdev_init_gpio_out(&s->busdev.qdev, s->handler, 16);
qdev_init_gpio_in(&s->busdev.qdev, scoop_gpio_set, 16);
memory_region_init_io(&s->iomem, &scoop_ops, s, "scoop", 0x1000);
memory_region_init_io(&s->iomem, NULL, &scoop_ops, s, "scoop", 0x1000);
sysbus_init_mmio(dev, &s->iomem);

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