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sparc64: fix pstate privilege bits
- refactor code to handle hpstate only if available for current cpu - conditionally set hypervisor bit in hpstate register - reorder softmmu indices so user accessable ones go first, translation context macros supervisor() and hypervisor() adjusted as well - disable sparcv8 registers for TARGET_SPARC64 - fix cpu_mmu_index to use sparcv9 bits only Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Igor V. Kovalenko
Blue Swirl
parent
b8e9fc0625
commit
2aae2b8e0a
@ -92,12 +92,14 @@
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#define PSR_CARRY_SHIFT 20
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#define PSR_CARRY (1 << PSR_CARRY_SHIFT)
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#define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
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#if !defined(TARGET_SPARC64)
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#define PSR_EF (1<<12)
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#define PSR_PIL 0xf00
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#define PSR_S (1<<7)
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#define PSR_PS (1<<6)
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#define PSR_ET (1<<5)
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#define PSR_CWP 0x1f
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#endif
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#define CC_SRC (env->cc_src)
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#define CC_SRC2 (env->cc_src2)
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@ -341,14 +343,16 @@ typedef struct CPUSPARCState {
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uint32_t wim; /* window invalid mask */
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#endif
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target_ulong tbr; /* trap base register */
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#if !defined(TARGET_SPARC64)
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int psrs; /* supervisor mode (extracted from PSR) */
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int psrps; /* previous supervisor mode */
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#if !defined(TARGET_SPARC64)
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int psret; /* enable traps */
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#endif
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uint32_t psrpil; /* interrupt blocking level */
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uint32_t pil_in; /* incoming interrupt level bitmap */
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#if !defined(TARGET_SPARC64)
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int psref; /* enable fpu */
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#endif
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target_ulong version;
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int interrupt_index;
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uint32_t nwindows;
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@ -508,21 +512,41 @@ int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
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#define CPU_SAVE_VERSION 6
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/* MMU modes definitions */
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#define MMU_MODE0_SUFFIX _user
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#define MMU_MODE1_SUFFIX _kernel
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#ifdef TARGET_SPARC64
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#define MMU_MODE2_SUFFIX _hypv
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#define MMU_MODE3_SUFFIX _nucleus
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#define MMU_MODE4_SUFFIX _user_secondary
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#define MMU_MODE5_SUFFIX _kernel_secondary
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#endif
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#if defined (TARGET_SPARC64)
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#define MMU_USER_IDX 0
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#define MMU_MODE0_SUFFIX _user
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#define MMU_USER_SECONDARY_IDX 1
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#define MMU_MODE1_SUFFIX _user_secondary
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#define MMU_KERNEL_IDX 2
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#define MMU_MODE2_SUFFIX _kernel
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#define MMU_KERNEL_SECONDARY_IDX 3
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#define MMU_MODE3_SUFFIX _kernel_secondary
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#define MMU_NUCLEUS_IDX 4
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#define MMU_MODE4_SUFFIX _nucleus
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#define MMU_HYPV_IDX 5
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#define MMU_MODE5_SUFFIX _hypv
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#else
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#define MMU_USER_IDX 0
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#define MMU_MODE0_SUFFIX _user
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#define MMU_KERNEL_IDX 1
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#define MMU_HYPV_IDX 2
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#ifdef TARGET_SPARC64
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#define MMU_NUCLEUS_IDX 3
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#define MMU_USER_SECONDARY_IDX 4
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#define MMU_KERNEL_SECONDARY_IDX 5
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#define MMU_MODE1_SUFFIX _kernel
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#endif
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#if defined (TARGET_SPARC64)
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static inline int cpu_has_hypervisor(CPUState *env1)
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{
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return env1->def->features & CPU_FEATURE_HYPV;
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}
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static inline int cpu_hypervisor_mode(CPUState *env1)
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{
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return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV);
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}
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static inline int cpu_supervisor_mode(CPUState *env1)
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{
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return env1->pstate & PS_PRIV;
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}
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#endif
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static inline int cpu_mmu_index(CPUState *env1)
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@ -532,12 +556,13 @@ static inline int cpu_mmu_index(CPUState *env1)
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#elif !defined(TARGET_SPARC64)
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return env1->psrs;
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#else
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if (!env1->psrs)
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return MMU_USER_IDX;
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else if ((env1->hpstate & HS_PRIV) == 0)
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return MMU_KERNEL_IDX;
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else
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if (cpu_hypervisor_mode(env1)) {
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return MMU_HYPV_IDX;
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} else if (cpu_supervisor_mode(env1)) {
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return MMU_KERNEL_IDX;
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} else {
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return MMU_USER_IDX;
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}
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#endif
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}
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@ -746,12 +746,12 @@ void cpu_reset(CPUSPARCState *env)
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#else
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#if !defined(TARGET_SPARC64)
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env->psret = 0;
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#endif
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env->psrs = 1;
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env->psrps = 1;
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#endif
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#ifdef TARGET_SPARC64
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env->pstate = PS_PRIV|PS_RED|PS_PEF|PS_AG;
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env->hpstate = HS_PRIV;
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env->hpstate = cpu_has_hypervisor(env) ? HS_PRIV : 0;
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env->tl = env->maxtl;
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cpu_tsptr(env)->tt = TT_POWER_ON_RESET;
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env->lsu = 0;
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@ -1404,11 +1404,7 @@ static target_ulong get_psr(void)
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(env->psrps? PSR_PS : 0) |
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(env->psret? PSR_ET : 0) | env->cwp;
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#else
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return env->version | (env->psr & PSR_ICC) |
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(env->psref? PSR_EF : 0) |
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(env->psrpil << 8) |
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(env->psrs? PSR_S : 0) |
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(env->psrps? PSR_PS : 0) | env->cwp;
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return env->psr & PSR_ICC;
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#endif
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}
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@ -1427,17 +1423,19 @@ target_ulong cpu_get_psr(CPUState *env1)
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static void put_psr(target_ulong val)
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{
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env->psr = val & PSR_ICC;
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#if !defined (TARGET_SPARC64)
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env->psref = (val & PSR_EF)? 1 : 0;
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env->psrpil = (val & PSR_PIL) >> 8;
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#endif
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#if ((!defined (TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY))
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cpu_check_irqs(env);
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#endif
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#if !defined (TARGET_SPARC64)
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env->psrs = (val & PSR_S)? 1 : 0;
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env->psrps = (val & PSR_PS)? 1 : 0;
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#if !defined (TARGET_SPARC64)
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env->psret = (val & PSR_ET)? 1 : 0;
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#endif
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set_cwp(val & PSR_CWP);
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#endif
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env->cc_op = CC_OP_FLAGS;
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}
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@ -2326,7 +2324,7 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
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asi &= 0xff;
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if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
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|| ((env->def->features & CPU_FEATURE_HYPV)
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|| (cpu_has_hypervisor(env)
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&& asi >= 0x30 && asi < 0x80
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&& !(env->hpstate & HS_PRIV)))
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raise_exception(TT_PRIV_ACT);
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@ -2361,8 +2359,7 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
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case 0xe2: // UA2007 Primary block init
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case 0xe3: // UA2007 Secondary block init
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if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
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if ((env->def->features & CPU_FEATURE_HYPV)
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&& env->hpstate & HS_PRIV) {
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if (cpu_hypervisor_mode(env)) {
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switch(size) {
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case 1:
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ret = ldub_hypv(addr);
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@ -2678,7 +2675,7 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
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asi &= 0xff;
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if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
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|| ((env->def->features & CPU_FEATURE_HYPV)
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|| (cpu_has_hypervisor(env)
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&& asi >= 0x30 && asi < 0x80
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&& !(env->hpstate & HS_PRIV)))
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raise_exception(TT_PRIV_ACT);
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@ -2722,8 +2719,7 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
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case 0xe2: // UA2007 Primary block init
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case 0xe3: // UA2007 Secondary block init
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if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
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if ((env->def->features & CPU_FEATURE_HYPV)
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&& env->hpstate & HS_PRIV) {
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if (cpu_hypervisor_mode(env)) {
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switch(size) {
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case 1:
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stb_hypv(addr, val);
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@ -3048,7 +3044,7 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
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void helper_ldda_asi(target_ulong addr, int asi, int rd)
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{
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if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
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|| ((env->def->features & CPU_FEATURE_HYPV)
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|| (cpu_has_hypervisor(env)
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&& asi >= 0x30 && asi < 0x80
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&& !(env->hpstate & HS_PRIV)))
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raise_exception(TT_PRIV_ACT);
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@ -183,9 +183,9 @@ static void gen_op_store_QT0_fpr(unsigned int dst)
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#define hypervisor(dc) 0
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#endif
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#else
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#define supervisor(dc) (dc->mem_idx >= 1)
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#define supervisor(dc) (dc->mem_idx >= MMU_KERNEL_IDX)
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#ifdef TARGET_SPARC64
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#define hypervisor(dc) (dc->mem_idx == 2)
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#define hypervisor(dc) (dc->mem_idx == MMU_HYPV_IDX)
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#else
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#endif
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#endif
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