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hpet: Coding style cleanups and some refactorings
This moves the private HPET structures into the C module, simplifies some helper functions and fixes most coding style issues (biggest chunk was improper switch-case indention). No functional changes. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Jan Kiszka
Blue Swirl
parent
6982d6647e
commit
27bb0b2d6f
413
hw/hpet.c
413
hw/hpet.c
@ -37,21 +37,47 @@
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#define DPRINTF(...)
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#endif
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struct HPETState;
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typedef struct HPETTimer { /* timers */
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uint8_t tn; /*timer number*/
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QEMUTimer *qemu_timer;
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struct HPETState *state;
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/* Memory-mapped, software visible timer registers */
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uint64_t config; /* configuration/cap */
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uint64_t cmp; /* comparator */
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uint64_t fsb; /* FSB route, not supported now */
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/* Hidden register state */
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uint64_t period; /* Last value written to comparator */
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uint8_t wrap_flag; /* timer pop will indicate wrap for one-shot 32-bit
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* mode. Next pop will be actual timer expiration.
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*/
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} HPETTimer;
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typedef struct HPETState {
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uint64_t hpet_offset;
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qemu_irq *irqs;
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HPETTimer timer[HPET_NUM_TIMERS];
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/* Memory-mapped, software visible registers */
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uint64_t capability; /* capabilities */
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uint64_t config; /* configuration */
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uint64_t isr; /* interrupt status reg */
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uint64_t hpet_counter; /* main counter */
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} HPETState;
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static HPETState *hpet_statep;
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uint32_t hpet_in_legacy_mode(void)
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{
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if (hpet_statep)
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return hpet_statep->config & HPET_CFG_LEGACY;
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else
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if (!hpet_statep) {
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return 0;
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}
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return hpet_statep->config & HPET_CFG_LEGACY;
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}
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static uint32_t timer_int_route(struct HPETTimer *timer)
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{
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uint32_t route;
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route = (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
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return route;
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return (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
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}
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static uint32_t hpet_enabled(void)
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@ -108,9 +134,7 @@ static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask)
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static uint64_t hpet_get_ticks(void)
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{
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uint64_t ticks;
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ticks = ns_to_ticks(qemu_get_clock(vm_clock) + hpet_statep->hpet_offset);
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return ticks;
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return ns_to_ticks(qemu_get_clock(vm_clock) + hpet_statep->hpet_offset);
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}
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/*
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@ -121,12 +145,14 @@ static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current)
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if (t->config & HPET_TN_32BIT) {
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uint32_t diff, cmp;
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cmp = (uint32_t)t->cmp;
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diff = cmp - (uint32_t)current;
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diff = (int32_t)diff > 0 ? diff : (uint32_t)0;
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return (uint64_t)diff;
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} else {
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uint64_t diff, cmp;
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cmp = t->cmp;
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diff = cmp - current;
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diff = (int64_t)diff > 0 ? diff : (uint64_t)0;
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@ -136,7 +162,6 @@ static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current)
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static void update_irq(struct HPETTimer *timer)
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{
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qemu_irq irq;
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int route;
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if (timer->tn <= 1 && hpet_in_legacy_mode()) {
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@ -144,22 +169,20 @@ static void update_irq(struct HPETTimer *timer)
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* timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
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* timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
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*/
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if (timer->tn == 0) {
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irq=timer->state->irqs[0];
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} else
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irq=timer->state->irqs[8];
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route = (timer->tn == 0) ? 0 : 8;
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} else {
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route=timer_int_route(timer);
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irq=timer->state->irqs[route];
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route = timer_int_route(timer);
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}
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if (timer_enabled(timer) && hpet_enabled()) {
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qemu_irq_pulse(irq);
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if (!timer_enabled(timer) || !hpet_enabled()) {
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return;
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}
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qemu_irq_pulse(timer->state->irqs[route]);
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}
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static void hpet_pre_save(void *opaque)
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{
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HPETState *s = opaque;
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/* save current counter value */
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s->hpet_counter = hpet_get_ticks();
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}
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@ -212,7 +235,7 @@ static const VMStateDescription vmstate_hpet = {
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*/
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static void hpet_timer(void *opaque)
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{
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HPETTimer *t = (HPETTimer*)opaque;
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HPETTimer *t = opaque;
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uint64_t diff;
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uint64_t period = t->period;
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@ -220,20 +243,22 @@ static void hpet_timer(void *opaque)
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if (timer_is_periodic(t) && period != 0) {
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if (t->config & HPET_TN_32BIT) {
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while (hpet_time_after(cur_tick, t->cmp))
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while (hpet_time_after(cur_tick, t->cmp)) {
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t->cmp = (uint32_t)(t->cmp + t->period);
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} else
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while (hpet_time_after64(cur_tick, t->cmp))
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}
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} else {
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while (hpet_time_after64(cur_tick, t->cmp)) {
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t->cmp += period;
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}
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}
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diff = hpet_calculate_diff(t, cur_tick);
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qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock)
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+ (int64_t)ticks_to_ns(diff));
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qemu_mod_timer(t->qemu_timer,
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qemu_get_clock(vm_clock) + (int64_t)ticks_to_ns(diff));
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} else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
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if (t->wrap_flag) {
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diff = hpet_calculate_diff(t, cur_tick);
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qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock)
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+ (int64_t)ticks_to_ns(diff));
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qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock) +
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(int64_t)ticks_to_ns(diff));
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t->wrap_flag = 0;
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}
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}
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@ -260,8 +285,8 @@ static void hpet_set_timer(HPETTimer *t)
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t->wrap_flag = 1;
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}
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}
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qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock)
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+ (int64_t)ticks_to_ns(diff));
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qemu_mod_timer(t->qemu_timer,
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qemu_get_clock(vm_clock) + (int64_t)ticks_to_ns(diff));
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}
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static void hpet_del_timer(HPETTimer *t)
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@ -285,7 +310,7 @@ static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr)
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static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr)
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{
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HPETState *s = (HPETState *)opaque;
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HPETState *s = opaque;
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uint64_t cur_tick, index;
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DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr);
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@ -293,57 +318,60 @@ static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr)
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/*address range of all TN regs*/
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if (index >= 0x100 && index <= 0x3ff) {
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uint8_t timer_id = (addr - 0x100) / 0x20;
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HPETTimer *timer = &s->timer[timer_id];
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if (timer_id > HPET_NUM_TIMERS - 1) {
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DPRINTF("qemu: timer id out of range\n");
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return 0;
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}
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HPETTimer *timer = &s->timer[timer_id];
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switch ((addr - 0x100) % 0x20) {
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case HPET_TN_CFG:
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return timer->config;
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case HPET_TN_CFG + 4: // Interrupt capabilities
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return timer->config >> 32;
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case HPET_TN_CMP: // comparator register
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return timer->cmp;
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case HPET_TN_CMP + 4:
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return timer->cmp >> 32;
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case HPET_TN_ROUTE:
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return timer->fsb >> 32;
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default:
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DPRINTF("qemu: invalid hpet_ram_readl\n");
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break;
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case HPET_TN_CFG:
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return timer->config;
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case HPET_TN_CFG + 4: // Interrupt capabilities
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return timer->config >> 32;
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case HPET_TN_CMP: // comparator register
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return timer->cmp;
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case HPET_TN_CMP + 4:
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return timer->cmp >> 32;
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case HPET_TN_ROUTE:
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return timer->fsb >> 32;
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default:
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DPRINTF("qemu: invalid hpet_ram_readl\n");
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break;
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}
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} else {
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switch (index) {
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case HPET_ID:
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return s->capability;
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case HPET_PERIOD:
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return s->capability >> 32;
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case HPET_CFG:
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return s->config;
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case HPET_CFG + 4:
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DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
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return 0;
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case HPET_COUNTER:
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if (hpet_enabled())
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cur_tick = hpet_get_ticks();
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else
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cur_tick = s->hpet_counter;
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DPRINTF("qemu: reading counter = %" PRIx64 "\n", cur_tick);
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return cur_tick;
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case HPET_COUNTER + 4:
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if (hpet_enabled())
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cur_tick = hpet_get_ticks();
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else
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cur_tick = s->hpet_counter;
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DPRINTF("qemu: reading counter + 4 = %" PRIx64 "\n", cur_tick);
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return cur_tick >> 32;
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case HPET_STATUS:
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return s->isr;
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default:
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DPRINTF("qemu: invalid hpet_ram_readl\n");
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break;
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case HPET_ID:
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return s->capability;
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case HPET_PERIOD:
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return s->capability >> 32;
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case HPET_CFG:
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return s->config;
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case HPET_CFG + 4:
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DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
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return 0;
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case HPET_COUNTER:
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if (hpet_enabled()) {
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cur_tick = hpet_get_ticks();
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} else {
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cur_tick = s->hpet_counter;
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}
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DPRINTF("qemu: reading counter = %" PRIx64 "\n", cur_tick);
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return cur_tick;
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case HPET_COUNTER + 4:
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if (hpet_enabled()) {
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cur_tick = hpet_get_ticks();
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} else {
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cur_tick = s->hpet_counter;
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}
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DPRINTF("qemu: reading counter + 4 = %" PRIx64 "\n", cur_tick);
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return cur_tick >> 32;
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case HPET_STATUS:
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return s->isr;
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default:
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DPRINTF("qemu: invalid hpet_ram_readl\n");
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break;
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}
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}
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return 0;
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@ -369,7 +397,7 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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int i;
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HPETState *s = (HPETState *)opaque;
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HPETState *s = opaque;
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uint64_t old_val, new_val, val, index;
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DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value);
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@ -380,133 +408,137 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
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/*address range of all TN regs*/
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if (index >= 0x100 && index <= 0x3ff) {
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uint8_t timer_id = (addr - 0x100) / 0x20;
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DPRINTF("qemu: hpet_ram_writel timer_id = %#x \n", timer_id);
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HPETTimer *timer = &s->timer[timer_id];
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DPRINTF("qemu: hpet_ram_writel timer_id = %#x \n", timer_id);
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if (timer_id > HPET_NUM_TIMERS - 1) {
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DPRINTF("qemu: timer id out of range\n");
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return;
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}
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switch ((addr - 0x100) % 0x20) {
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case HPET_TN_CFG:
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DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n");
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val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK);
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timer->config = (timer->config & 0xffffffff00000000ULL) | val;
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if (new_val & HPET_TN_32BIT) {
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timer->cmp = (uint32_t)timer->cmp;
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timer->period = (uint32_t)timer->period;
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}
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if (new_val & HPET_TIMER_TYPE_LEVEL) {
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printf("qemu: level-triggered hpet not supported\n");
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exit (-1);
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}
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break;
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case HPET_TN_CFG + 4: // Interrupt capabilities
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DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n");
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break;
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case HPET_TN_CMP: // comparator register
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DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP \n");
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if (timer->config & HPET_TN_32BIT)
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new_val = (uint32_t)new_val;
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if (!timer_is_periodic(timer) ||
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(timer->config & HPET_TN_SETVAL))
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timer->cmp = (timer->cmp & 0xffffffff00000000ULL)
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| new_val;
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if (timer_is_periodic(timer)) {
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/*
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* FIXME: Clamp period to reasonable min value?
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* Clamp period to reasonable max value
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*/
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new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
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timer->period = (timer->period & 0xffffffff00000000ULL)
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| new_val;
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case HPET_TN_CFG:
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DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n");
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val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK);
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timer->config = (timer->config & 0xffffffff00000000ULL) | val;
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if (new_val & HPET_TN_32BIT) {
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timer->cmp = (uint32_t)timer->cmp;
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timer->period = (uint32_t)timer->period;
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}
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if (new_val & HPET_TN_TYPE_LEVEL) {
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printf("qemu: level-triggered hpet not supported\n");
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exit (-1);
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}
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break;
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case HPET_TN_CFG + 4: // Interrupt capabilities
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DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n");
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break;
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case HPET_TN_CMP: // comparator register
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DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP \n");
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if (timer->config & HPET_TN_32BIT) {
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new_val = (uint32_t)new_val;
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}
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if (!timer_is_periodic(timer)
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|| (timer->config & HPET_TN_SETVAL)) {
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timer->cmp = (timer->cmp & 0xffffffff00000000ULL) | new_val;
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}
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if (timer_is_periodic(timer)) {
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/*
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* FIXME: Clamp period to reasonable min value?
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* Clamp period to reasonable max value
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*/
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new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
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timer->period =
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(timer->period & 0xffffffff00000000ULL) | new_val;
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}
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timer->config &= ~HPET_TN_SETVAL;
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if (hpet_enabled()) {
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hpet_set_timer(timer);
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}
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break;
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case HPET_TN_CMP + 4: // comparator register high order
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DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
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if (!timer_is_periodic(timer)
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|| (timer->config & HPET_TN_SETVAL)) {
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timer->cmp = (timer->cmp & 0xffffffffULL) | new_val << 32;
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} else {
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/*
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* FIXME: Clamp period to reasonable min value?
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* Clamp period to reasonable max value
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*/
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new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
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timer->period =
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(timer->period & 0xffffffffULL) | new_val << 32;
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}
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timer->config &= ~HPET_TN_SETVAL;
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if (hpet_enabled())
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if (hpet_enabled()) {
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hpet_set_timer(timer);
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break;
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case HPET_TN_CMP + 4: // comparator register high order
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DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
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if (!timer_is_periodic(timer) ||
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(timer->config & HPET_TN_SETVAL))
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timer->cmp = (timer->cmp & 0xffffffffULL)
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| new_val << 32;
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else {
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/*
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* FIXME: Clamp period to reasonable min value?
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* Clamp period to reasonable max value
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*/
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new_val &= (timer->config
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& HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
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timer->period = (timer->period & 0xffffffffULL)
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| new_val << 32;
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}
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timer->config &= ~HPET_TN_SETVAL;
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if (hpet_enabled())
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hpet_set_timer(timer);
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break;
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case HPET_TN_ROUTE + 4:
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DPRINTF("qemu: hpet_ram_writel HPET_TN_ROUTE + 4\n");
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break;
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default:
|
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DPRINTF("qemu: invalid hpet_ram_writel\n");
|
||||
break;
|
||||
case HPET_TN_ROUTE + 4:
|
||||
DPRINTF("qemu: hpet_ram_writel HPET_TN_ROUTE + 4\n");
|
||||
break;
|
||||
default:
|
||||
DPRINTF("qemu: invalid hpet_ram_writel\n");
|
||||
break;
|
||||
}
|
||||
return;
|
||||
} else {
|
||||
switch (index) {
|
||||
case HPET_ID:
|
||||
return;
|
||||
case HPET_CFG:
|
||||
val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK);
|
||||
s->config = (s->config & 0xffffffff00000000ULL) | val;
|
||||
if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
|
||||
/* Enable main counter and interrupt generation. */
|
||||
s->hpet_offset = ticks_to_ns(s->hpet_counter)
|
||||
- qemu_get_clock(vm_clock);
|
||||
for (i = 0; i < HPET_NUM_TIMERS; i++)
|
||||
if ((&s->timer[i])->cmp != ~0ULL)
|
||||
hpet_set_timer(&s->timer[i]);
|
||||
case HPET_ID:
|
||||
return;
|
||||
case HPET_CFG:
|
||||
val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK);
|
||||
s->config = (s->config & 0xffffffff00000000ULL) | val;
|
||||
if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
|
||||
/* Enable main counter and interrupt generation. */
|
||||
s->hpet_offset =
|
||||
ticks_to_ns(s->hpet_counter) - qemu_get_clock(vm_clock);
|
||||
for (i = 0; i < HPET_NUM_TIMERS; i++) {
|
||||
if ((&s->timer[i])->cmp != ~0ULL) {
|
||||
hpet_set_timer(&s->timer[i]);
|
||||
}
|
||||
}
|
||||
else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
|
||||
/* Halt main counter and disable interrupt generation. */
|
||||
s->hpet_counter = hpet_get_ticks();
|
||||
for (i = 0; i < HPET_NUM_TIMERS; i++)
|
||||
hpet_del_timer(&s->timer[i]);
|
||||
} else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
|
||||
/* Halt main counter and disable interrupt generation. */
|
||||
s->hpet_counter = hpet_get_ticks();
|
||||
for (i = 0; i < HPET_NUM_TIMERS; i++) {
|
||||
hpet_del_timer(&s->timer[i]);
|
||||
}
|
||||
/* i8254 and RTC are disabled when HPET is in legacy mode */
|
||||
if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
|
||||
hpet_pit_disable();
|
||||
} else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
|
||||
hpet_pit_enable();
|
||||
}
|
||||
break;
|
||||
case HPET_CFG + 4:
|
||||
DPRINTF("qemu: invalid HPET_CFG+4 write \n");
|
||||
break;
|
||||
case HPET_STATUS:
|
||||
/* FIXME: need to handle level-triggered interrupts */
|
||||
break;
|
||||
case HPET_COUNTER:
|
||||
if (hpet_enabled())
|
||||
printf("qemu: Writing counter while HPET enabled!\n");
|
||||
s->hpet_counter = (s->hpet_counter & 0xffffffff00000000ULL)
|
||||
| value;
|
||||
DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n",
|
||||
value, s->hpet_counter);
|
||||
break;
|
||||
case HPET_COUNTER + 4:
|
||||
if (hpet_enabled())
|
||||
printf("qemu: Writing counter while HPET enabled!\n");
|
||||
s->hpet_counter = (s->hpet_counter & 0xffffffffULL)
|
||||
| (((uint64_t)value) << 32);
|
||||
DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n",
|
||||
value, s->hpet_counter);
|
||||
break;
|
||||
default:
|
||||
DPRINTF("qemu: invalid hpet_ram_writel\n");
|
||||
break;
|
||||
}
|
||||
/* i8254 and RTC are disabled when HPET is in legacy mode */
|
||||
if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
|
||||
hpet_pit_disable();
|
||||
} else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
|
||||
hpet_pit_enable();
|
||||
}
|
||||
break;
|
||||
case HPET_CFG + 4:
|
||||
DPRINTF("qemu: invalid HPET_CFG+4 write \n");
|
||||
break;
|
||||
case HPET_STATUS:
|
||||
/* FIXME: need to handle level-triggered interrupts */
|
||||
break;
|
||||
case HPET_COUNTER:
|
||||
if (hpet_enabled()) {
|
||||
printf("qemu: Writing counter while HPET enabled!\n");
|
||||
}
|
||||
s->hpet_counter =
|
||||
(s->hpet_counter & 0xffffffff00000000ULL) | value;
|
||||
DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n",
|
||||
value, s->hpet_counter);
|
||||
break;
|
||||
case HPET_COUNTER + 4:
|
||||
if (hpet_enabled()) {
|
||||
printf("qemu: Writing counter while HPET enabled!\n");
|
||||
}
|
||||
s->hpet_counter =
|
||||
(s->hpet_counter & 0xffffffffULL) | (((uint64_t)value) << 32);
|
||||
DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n",
|
||||
value, s->hpet_counter);
|
||||
break;
|
||||
default:
|
||||
DPRINTF("qemu: invalid hpet_ram_writel\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -533,13 +565,15 @@ static CPUWriteMemoryFunc * const hpet_ram_write[] = {
|
||||
hpet_ram_writel,
|
||||
};
|
||||
|
||||
static void hpet_reset(void *opaque) {
|
||||
static void hpet_reset(void *opaque)
|
||||
{
|
||||
HPETState *s = opaque;
|
||||
int i;
|
||||
static int count = 0;
|
||||
|
||||
for (i=0; i<HPET_NUM_TIMERS; i++) {
|
||||
for (i = 0; i < HPET_NUM_TIMERS; i++) {
|
||||
HPETTimer *timer = &s->timer[i];
|
||||
|
||||
hpet_del_timer(timer);
|
||||
timer->tn = i;
|
||||
timer->cmp = ~0ULL;
|
||||
@ -557,19 +591,22 @@ static void hpet_reset(void *opaque) {
|
||||
s->capability = 0x8086a201ULL;
|
||||
s->capability |= ((HPET_CLK_PERIOD) << 32);
|
||||
s->config = 0ULL;
|
||||
if (count > 0)
|
||||
if (count > 0) {
|
||||
/* we don't enable pit when hpet_reset is first called (by hpet_init)
|
||||
* because hpet is taking over for pit here. On subsequent invocations,
|
||||
* hpet_reset is called due to system reset. At this point control must
|
||||
* be returned to pit until SW reenables hpet.
|
||||
*/
|
||||
hpet_pit_enable();
|
||||
}
|
||||
count = 1;
|
||||
}
|
||||
|
||||
|
||||
void hpet_init(qemu_irq *irq) {
|
||||
void hpet_init(qemu_irq *irq)
|
||||
{
|
||||
int i, iomemtype;
|
||||
HPETTimer *timer;
|
||||
HPETState *s;
|
||||
|
||||
DPRINTF ("hpet_init\n");
|
||||
@ -577,8 +614,8 @@ void hpet_init(qemu_irq *irq) {
|
||||
s = qemu_mallocz(sizeof(HPETState));
|
||||
hpet_statep = s;
|
||||
s->irqs = irq;
|
||||
for (i=0; i<HPET_NUM_TIMERS; i++) {
|
||||
HPETTimer *timer = &s->timer[i];
|
||||
for (i = 0; i < HPET_NUM_TIMERS; i++) {
|
||||
timer = &s->timer[i];
|
||||
timer->qemu_timer = qemu_new_timer(vm_clock, hpet_timer, timer);
|
||||
}
|
||||
vmstate_register(-1, &vmstate_hpet, s);
|
||||
|
||||
@ -18,7 +18,6 @@
|
||||
|
||||
#define FS_PER_NS 1000000
|
||||
#define HPET_NUM_TIMERS 3
|
||||
#define HPET_TIMER_TYPE_LEVEL 0x002
|
||||
|
||||
#define HPET_CFG_ENABLE 0x001
|
||||
#define HPET_CFG_LEGACY 0x002
|
||||
@ -33,7 +32,7 @@
|
||||
#define HPET_TN_ROUTE 0x010
|
||||
#define HPET_CFG_WRITE_MASK 0x3
|
||||
|
||||
|
||||
#define HPET_TN_TYPE_LEVEL 0x002
|
||||
#define HPET_TN_ENABLE 0x004
|
||||
#define HPET_TN_PERIODIC 0x008
|
||||
#define HPET_TN_PERIODIC_CAP 0x010
|
||||
@ -46,34 +45,6 @@
|
||||
#define HPET_TN_INT_ROUTE_CAP_SHIFT 32
|
||||
#define HPET_TN_CFG_BITS_READONLY_OR_RESERVED 0xffff80b1U
|
||||
|
||||
struct HPETState;
|
||||
typedef struct HPETTimer { /* timers */
|
||||
uint8_t tn; /*timer number*/
|
||||
QEMUTimer *qemu_timer;
|
||||
struct HPETState *state;
|
||||
/* Memory-mapped, software visible timer registers */
|
||||
uint64_t config; /* configuration/cap */
|
||||
uint64_t cmp; /* comparator */
|
||||
uint64_t fsb; /* FSB route, not supported now */
|
||||
/* Hidden register state */
|
||||
uint64_t period; /* Last value written to comparator */
|
||||
uint8_t wrap_flag; /* timer pop will indicate wrap for one-shot 32-bit
|
||||
* mode. Next pop will be actual timer expiration.
|
||||
*/
|
||||
} HPETTimer;
|
||||
|
||||
typedef struct HPETState {
|
||||
uint64_t hpet_offset;
|
||||
qemu_irq *irqs;
|
||||
HPETTimer timer[HPET_NUM_TIMERS];
|
||||
|
||||
/* Memory-mapped, software visible registers */
|
||||
uint64_t capability; /* capabilities */
|
||||
uint64_t config; /* configuration */
|
||||
uint64_t isr; /* interrupt status reg */
|
||||
uint64_t hpet_counter; /* main counter */
|
||||
} HPETState;
|
||||
|
||||
#if defined TARGET_I386
|
||||
extern uint32_t hpet_in_legacy_mode(void);
|
||||
extern void hpet_init(qemu_irq *irq);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user