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linux-user: i386/signal: support FXSAVE fpstate on 32-bit emulation
Linux can use FXSAVE to save/restore XMM registers even on 32-bit systems. This requires some care in order to keep the FXSAVE area aligned to 16 bytes; for this reason, get_sigframe is changed to pass the offset into the FXSAVE area rather than the full frame size. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini
parent
5154d35bed
commit
2796f290b5
@ -39,29 +39,7 @@ struct target_xmmreg {
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uint32_t element[4];
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};
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struct target_fpstate_32 {
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/* Regular FPU environment */
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uint32_t cw;
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uint32_t sw;
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uint32_t tag;
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uint32_t ipoff;
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uint32_t cssel;
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uint32_t dataoff;
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uint32_t datasel;
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struct target_fpreg st[8];
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uint16_t status;
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uint16_t magic; /* 0xffff = regular FPU data only */
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/* FXSR FPU environment */
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uint32_t _fxsr_env[6]; /* FXSR FPU env is ignored */
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uint32_t mxcsr;
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uint32_t reserved;
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struct target_fpxreg fxsr_st[8]; /* FXSR FPU reg data is ignored */
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struct target_xmmreg xmm[8];
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uint32_t padding[56];
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};
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struct target_fpstate_64 {
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struct target_fpstate_fxsave {
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/* FXSAVE format */
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uint16_t cw;
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uint16_t sw;
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@ -75,11 +53,36 @@ struct target_fpstate_64 {
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uint32_t xmm_space[64];
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uint32_t reserved[24];
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};
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#define TARGET_FXSAVE_SIZE sizeof(struct target_fpstate_fxsave)
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QEMU_BUILD_BUG_ON(TARGET_FXSAVE_SIZE != 512);
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struct target_fpstate_32 {
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/* Regular FPU environment */
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uint32_t cw;
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uint32_t sw;
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uint32_t tag;
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uint32_t ipoff;
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uint32_t cssel;
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uint32_t dataoff;
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uint32_t datasel;
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struct target_fpreg st[8];
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uint16_t status;
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uint16_t magic; /* 0xffff = regular FPU data only */
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struct target_fpstate_fxsave fxsave;
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};
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/*
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* For simplicity, setup_frame aligns struct target_fpstate_32 to
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* 16 bytes, so ensure that the FXSAVE area is also aligned.
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*/
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QEMU_BUILD_BUG_ON(offsetof(struct target_fpstate_32, fxsave) & 15);
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#ifndef TARGET_X86_64
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# define target_fpstate target_fpstate_32
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# define TARGET_FPSTATE_FXSAVE_OFFSET offsetof(struct target_fpstate_32, fxsave)
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#else
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# define target_fpstate target_fpstate_64
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# define target_fpstate target_fpstate_fxsave
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# define TARGET_FPSTATE_FXSAVE_OFFSET 0
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#endif
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struct target_sigcontext_32 {
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@ -172,8 +175,16 @@ struct sigframe {
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struct target_fpstate fpstate_unused;
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abi_ulong extramask[TARGET_NSIG_WORDS-1];
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char retcode[8];
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struct target_fpstate fpstate;
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/*
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* This field will be 16-byte aligned in memory. Applying QEMU_ALIGNED
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* to it ensures that the base of the frame has an appropriate alignment
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* too.
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*/
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struct target_fpstate fpstate QEMU_ALIGNED(8);
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};
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#define TARGET_SIGFRAME_FXSAVE_OFFSET ( \
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offsetof(struct sigframe, fpstate) + TARGET_FPSTATE_FXSAVE_OFFSET)
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struct rt_sigframe {
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abi_ulong pretcode;
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@ -183,25 +194,35 @@ struct rt_sigframe {
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struct target_siginfo info;
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struct target_ucontext uc;
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char retcode[8];
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struct target_fpstate fpstate;
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struct target_fpstate fpstate QEMU_ALIGNED(8);
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};
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#define TARGET_RT_SIGFRAME_FXSAVE_OFFSET ( \
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offsetof(struct rt_sigframe, fpstate) + TARGET_FPSTATE_FXSAVE_OFFSET)
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#else
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struct rt_sigframe {
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abi_ulong pretcode;
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struct target_ucontext uc;
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struct target_siginfo info;
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struct target_fpstate fpstate;
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struct target_fpstate fpstate QEMU_ALIGNED(16);
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};
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#define TARGET_RT_SIGFRAME_FXSAVE_OFFSET ( \
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offsetof(struct rt_sigframe, fpstate) + TARGET_FPSTATE_FXSAVE_OFFSET)
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#endif
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/*
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* Set up a signal frame.
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*/
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/* XXX: save x87 state */
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static void fxsave_sigcontext(CPUX86State *env, struct target_fpstate_fxsave *fxsave,
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abi_ulong fxsave_addr)
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{
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/* fxsave_addr must be 16 byte aligned for fxsave */
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assert(!(fxsave_addr & 0xf));
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cpu_x86_fxsave(env, fxsave_addr);
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}
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static void setup_sigcontext(struct target_sigcontext *sc,
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struct target_fpstate *fpstate, CPUX86State *env, abi_ulong mask,
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abi_ulong fpstate_addr)
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@ -233,13 +254,14 @@ static void setup_sigcontext(struct target_sigcontext *sc,
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cpu_x86_fsave(env, fpstate_addr, 1);
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fpstate->status = fpstate->sw;
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magic = 0xffff;
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if (!(env->features[FEAT_1_EDX] & CPUID_FXSR)) {
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magic = 0xffff;
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} else {
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fxsave_sigcontext(env, &fpstate->fxsave,
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fpstate_addr + TARGET_FPSTATE_FXSAVE_OFFSET);
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magic = 0;
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}
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__put_user(magic, &fpstate->magic);
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__put_user(fpstate_addr, &sc->fpstate);
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/* non-iBCS2 extensions.. */
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__put_user(mask, &sc->oldmask);
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__put_user(env->cr[2], &sc->cr2);
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#else
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__put_user(env->regs[R_EDI], &sc->rdi);
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__put_user(env->regs[R_ESI], &sc->rsi);
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@ -269,15 +291,14 @@ static void setup_sigcontext(struct target_sigcontext *sc,
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__put_user((uint16_t)0, &sc->fs);
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__put_user(env->segs[R_SS].selector, &sc->ss);
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fxsave_sigcontext(env, fpstate, fpstate_addr);
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#endif
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__put_user(fpstate_addr, &sc->fpstate);
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/* non-iBCS2 extensions.. */
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__put_user(mask, &sc->oldmask);
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__put_user(env->cr[2], &sc->cr2);
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/* fpstate_addr must be 16 byte aligned for fxsave */
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assert(!(fpstate_addr & 0xf));
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cpu_x86_fxsave(env, fpstate_addr);
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__put_user(fpstate_addr, &sc->fpstate);
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#endif
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}
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/*
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@ -285,7 +306,7 @@ static void setup_sigcontext(struct target_sigcontext *sc,
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*/
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static inline abi_ulong
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get_sigframe(struct target_sigaction *ka, CPUX86State *env, size_t frame_size)
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get_sigframe(struct target_sigaction *ka, CPUX86State *env, size_t fxsave_offset)
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{
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unsigned long esp;
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@ -309,11 +330,11 @@ get_sigframe(struct target_sigaction *ka, CPUX86State *env, size_t frame_size)
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#endif
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}
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#ifndef TARGET_X86_64
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return (esp - frame_size) & -8ul;
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#else
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return ((esp - frame_size) & (~15ul)) - 8;
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#endif
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if (!(env->features[FEAT_1_EDX] & CPUID_FXSR)) {
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return (esp - (fxsave_offset + TARGET_FXSAVE_SIZE)) & -8ul;
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} else {
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return ((esp - TARGET_FXSAVE_SIZE) & -16ul) - fxsave_offset;
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}
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}
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#ifndef TARGET_X86_64
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@ -341,7 +362,7 @@ void setup_frame(int sig, struct target_sigaction *ka,
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struct sigframe *frame;
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int i;
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frame_addr = get_sigframe(ka, env, sizeof(*frame));
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frame_addr = get_sigframe(ka, env, TARGET_SIGFRAME_FXSAVE_OFFSET);
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trace_user_setup_frame(env, frame_addr);
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if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0))
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@ -397,7 +418,7 @@ void setup_rt_frame(int sig, struct target_sigaction *ka,
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struct rt_sigframe *frame;
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int i;
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frame_addr = get_sigframe(ka, env, sizeof(*frame));
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frame_addr = get_sigframe(ka, env, TARGET_RT_SIGFRAME_FXSAVE_OFFSET);
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trace_user_setup_rt_frame(env, frame_addr);
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if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0))
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@ -529,7 +550,11 @@ restore_sigcontext(CPUX86State *env, struct target_sigcontext *sc)
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goto badframe;
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}
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#ifndef TARGET_X86_64
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cpu_x86_frstor(env, fpstate_addr, 1);
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if (!(env->features[FEAT_1_EDX] & CPUID_FXSR)) {
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cpu_x86_frstor(env, fpstate_addr, 1);
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} else {
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cpu_x86_fxrstor(env, fpstate_addr + TARGET_FPSTATE_FXSAVE_OFFSET);
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}
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#else
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cpu_x86_fxrstor(env, fpstate_addr);
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#endif
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